Flash Memoryy

김 영 석김 영 석

충북대학교 전자정보대학

2011.3.1. .

Email: kimys@cbu.ac.kr

전자정보대학 김영석 1

ContentsVolatile Memory

Nonvolatile Memory

VTH of Floating Gate EEPROM

Fl h MFlash Memory

NOR Flash

NAND FlashNAND Flash

Limitations

Scalability

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Volatile Memory1) DRAM(Dynamic Random Access Memory)

2) SRAM(Static Random Access Memory)

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Nonvolatile Memory1) ROM (Mask Programmable Read Only Memory)

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Nonvolatile Memory2) EPROM(UV Erasable Programmable ROM)

Floating Gate

Hot Electron Injection Program

TLVVVV 2090@7512UV Erase

nmTmLVVVV oxDCG 20,9.0@7,5.12 ==== μ

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Nonvolatile Memory3) EEPROM(Electrically Erasable and Programmable ROM)

TVVVFl tVVVnmTVVVVVV oxsubDSCG

10@020:Erase10@0,20:Program =====

Program/Erase: FN(Fowler-Nordheim) Tunneling

nmTVVVFloatVVV oxsubCGSD 10@0,,20:Erase =====

4) Flash EEPROM

Erased at one time like EPROM

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cf. EEPROM: Byte Erase

HCIE>100kV/cm => Hot Electrons

Lucky Electron Model

eIIII chsubchGi/~/ /ΦΦ−

VeVi

2.3~energybarrier injection :6.1~energy thresholdionization:

ΦΦ

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FN TunnelingFowler-Nordhein Tunning Current

Oxide through Field Electric

/2

=⋅= −

FeFAJ FB

F~10MV/cm (J=0.1A/cm2)F 1 MV/cm (J .1A/cm2)

Program time (~ 1ms) : 12 order shorter than Retention Time (~ 1yr)

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VTH of Floating Gate EEPROMElectrons (injected by HCI or FN tunneling) Increase Threshold Voltage

0@ DSFGpp

CGFG VVQCVV ==+= @

FGTHiTH

DSoxppoxpp

CGFG

CCQVV

CCCC

+−=

++

)22(2 0 FFSBTHdep

FFBTHi

oxpp

VVCQ

VV

CC

φφγφ −++=−+=

+

oxC

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Flash Memory (or EEPROM)Non-volatile Memory

Electrically Erased and Programmed (Same as EEPROM)

Flash EEPROM: Erase at Once => Cost Effective/Dominant Technology

(N Fl h) EEPROM B t E(Non-Flash) EEPROM: Byte Erase

Applications: Memory Cards, USB Flash Drive, Mobile Phone, SSD

Widely Used instead of EEPROM and SRAMWidely Used instead of EEPROM and SRAM

Fast Read Access Time (Not As Fast As Volatile DRAM)

Better kinetic Shock Resistance than Hard Disks

Memory Card: Durable, Resistant to Intense Pressure, Extreme Temperature, Even in Water

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Flash MemoryFloating-gate Transistor

Control Gate (CG) on top

Floating Gate (FG) bet. CG and Channel

Fl ti G tFloating-Gate

Electrically Isolated

Electrons are Placed => VTH IncreaseElectrons are Placed > VTH Increase

Not Discharge Electrons ~ 10 years

Read

Erased State: No Electrons on FG, VTH Low

Programmed State: Electrons on FG, VTH High

TType

NOR Flash

NAND FlashNAND Flash

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NOR FlashIntel Introduced in 1988

One end to GND, the other end to Bit Line

Acts like NOR Gate: If One of the Word Lines High, the Storage Transistor pulls Bit Line LowTransistor pulls Bit Line Low

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NOR FlashProgramming: Hot Carrier Injection

Erasing: FN Tunneling

Block-Wise Erase

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NOR FlashRequire Internal Charge Pumps to get High Voltage from Battery

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NAND FlashToshiba (Dr. Masuoka) Introduced in 1980

Resembles a NAND Gate: If All word lines High, the Bit Line Pulled Low

Denser Layout than NOR FlashDenser Layout than NOR Flash

FN Tunneling for Write/Erase

USB Flash Drives, Memory Cards, Solid-State Drivesy

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Comparisons between NOR and NAND

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LimitationsEndurance

Data Retention

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Flash Market RankingsFlash Types/Company

Flash Market Share

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Flash ScalabilityDesign Rule=30nm @2011

½ Shrink every 2 years

Cf. Moore’s Law: ½ Shrink every 3 years

Mi i F t Si 20Minimum Feature Size ~ 20nm

Further Flash Density Increases will be MLC, 3-D Stacking

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