Abstract—This paper presents the design optimization of a low

power, low noise, broadband transimpedance amplifier (TIA) that finds application as a front-end stage in a fiber optic data receiver. The TIA achieves a gain of 65.5 dBΩ, a bandwidth of 2.44 GHz and an input referred current noise of 11.91 pA/Hz1/2. The design is implemented in a standard 0.18µm digital CMOS process and dissipates 18.32mW from a 1.8V supply. Keywords— Broadband Amplifier, CMOS, Design Optimization,

Fiber Optic Receiver, High Speed Data Communication, Trans-impedance Amplifier.

I. INTRODUCTION transimpedance amplifier is a critical block of any fiber optic data receiver: it affects significantly cost and

performance in terms of speed, signal to noise ratio, and sensitivity. The design of a TIA requires the attentive optimization of a number of conflicting performance metrics including gain, bandwidth, noise, and power consumption [1]. Recent advances in nanoscale technologies made it economically viable to design CMOS TIA amplifiers that meet the stringent performances required by front-end optical transceivers applications. Unfortunately, the complexity of the models required to accurately describe the behavior of CMOS nanoscale transistors prevent the derivation of closed-form analytical expression that could be effectively used in the design optimization flow of even the most simple circuits [2]. This paper describes the development of a framework for the design optimization of nanometer analog and mixed-signal integrated circuits (IC) and applies it to the implementation of a high-speed, high-gain, low-noise and low-power TIA in a 0.18µm standard CMOS technology. The design optimization framework is implemented using MATLAB and is based on the gm/ID methodology [3],[4]. The ratio between transconductance gm and bias current ID is a figure of merit measuring a transistor ability to translate current (i.e. power) into transconductance (i.e. gain). The main advantage of using a gm/ID-based methodology is the capability to maintain a unified approach for all regions of operation of a MOS transistor. Having a systematic design approach from strong inversion to weak inversion makes the gm/ID methodology an ideal tool for the optimal sizing of transistors.

This is due to the possibility of taking full advantage of the moderate inversion region to optimize the speed-power trade off. Fig. 1 illustrates the relationship between a transistor’s speed (i.e. the transistor’s transient frequency fT) and its power efficiency (i.e. gm/ID). The goal of the proposed framework is the development of a systematic design optimization approach to be used in absence of closed-form MOSFET equations.

Fig. 1 Relationship between fT*gm/ID and gm/ID for nMOS transistors

with channel length L varying from 0.18µm to 0.4µm (0.18µm CMOS process)

The rest of the paper is organized as follows. Section II

describes the TIA topology and the equations and approximations used to predict and optimize performances. Section III motivates and describes the optimization strategy used for the design of the TIA. Section IV discusses experimental results and compares them to theoretical expectations. Finally, Section V summarizes the results of our work and provides conclusions.

II. TIA CIRCUIT DESCRIPTION

A. TIA Topology The main culprit in the design of a TIA is the capacitance of

the photodiode interfacing the fiber optic and the receiver side of the communication system. The photodiode capacitance affects significantly both bandwidth and signal to noise ratio. Fig. 2 depicts the overall structure of a typical optical

5 10 15 20

40

60

80

100

120

140

160

180

200

220

240speed−power tradeoff (nMOS: L=0.18um...0.4um)

gm/ID [S/A]

g m/I D*f T [G

Hz*S

/A]

L=0.18um

L=0.4um

Design Optimization of a TIA for High Speed Data Applications using gm/ID Based

Methodology Claudio Talarico, Gaurav Agrawal and Janet Wang-Roveda

A

Advances in Robotics, Mechatronics and Circuits

ISBN: 978-1-61804-242-2 40

communication (OC) system. The goal of an OC system is to transmit and receive large volumes of data across a long distance. A typical OC system consists of three components: a transmitter, a fiber, and a receiver [5]. The transmitter is composed of a mux that aggregates multiple data streams into a single stream, a driver, and an electro-optical transducer (i.e. a laser diode) that converts the electrical data in optical form. The fiber carries the light produced by the laser from the transmitting end to the receiving end. The receiver is composed by a photodetector (i.e. a photodiode) that senses the light coming from the fiber and converts it in electrical form (i.e. a current signal), a TIA, and a demux that decomposes the data back into multiple streams.

Fig. 2 Typical Optical Communication (OC) System

The main challenge in designing a TIA is to devise a circuit topology that makes it possible to relax the limitation caused by the photodiode capacitance present at the input node of the amplifier. Over the years, several circuit techniques have been proposed. The most commonly used techniques include capacitive peaking, inductive peaking, common gate input configuration and common drain configuration [6]-[8]. In this paper the TIA is implemented using a cascade of three stages. To minimize the effect of the large input capacitance due to the photodiode the input stage is a common gate with gm boosted via pMOS current injection. The middle stage is a common source, and the output stage is a source follower. This topology provides low input impedance (thanks to the common gate), high gain (through the combination of the common gate and the common source stages), and the ability to drive a small resistive load (thanks to the low output impedance of the source follower). Despite the gm boosting technique applied to the common gate stage, the level of gm achievable with a 0.18µm CMOS technology is not adequate to achieve the bandwidth required for optical communication applications. To overcome this challenge, the three basic stages of the TIA are surrounded by a global shunt-shunt resistive feedback. As predictable the feedback causes peaking in the amplifier’s frequency response; for the proposed topology is possible to improve the closed loop stability of the TIA and eliminate peaking by using the feedback-zero compensation technique. The TIA is implemented in differential form. A differential TIA has two main advantages: 1) the signal to noise ratio (SNR) of the system is effectively doubled, and 2) the common source stage can be implemented as a differential pair, so the biasing is considerably simpler. Fig.3 illustrates the TIA’s topology.

B. TIA Circuit Analysis The main bottleneck of the proposed topology is the poor frequency response of the common source. This is due to the

large time constant τ2 at input of the common source stage. To reduce the effect of τ2 the common source stage is cascoded. Cascoding provides two main advantages: 1) it reduces miller multiplication of the gate-to-drain capacitance and 2) it increases the intrinsic gain of the stage. These advantages are at the expense of a lower voltage swing. Fortunately, for the application at hand large signal swing is not a concern. Fig. 4 shows the complete circuit of the TIA. The photodiode is modeled by the input current signal iinput and the parasitic capacitances Cpa and Cpb. Fig. 5 shows the equivalent AC half circuit of the TIA. The AC half circuit includes the feedback loading and it is annotated with all capacitances affecting frequency response.

Fig. 3 TIA Topology

(CG = common gate, CS = common source, SF = source follower)

Fig. 4 TIA Schematic

The expressions used to analyze the performances of the TIA are derived from the AC half circuit. The transimpedance forward gain of the half circuit is:

a0 =voutiin

≈ −gm1* RF

1+ gm1* RF

R1 ⋅ gm2R2 ⋅gm3RLp1+ gm3RLp

(1)

where gm1*=gm1+gm1b and RLp= RL||RF||(1/gm3b). The shunt-

shunt feedback factor is:

f0 = −1RF

(2)

The loop gain is:

Laser_Driver TIA

Laser Photodiode

demuxxu

m

ds1

dsn

ds1

dsnFiber

RLa

RLb

Cca

Ccb

RFb

RFa

CFb

CFa

Photodiode via

vib voa

vobCSCG SF

M1a M1b

R1a R1b

iinputCpa Cpb

MB1a MB1b

M2a b2M

M2Ca M2Cb

MB2

R2a R2b

MB3a

M3a

M3b

Cca

RLa

MB3b

Ccb

RLb

RFa

CFa

RFb

CFb

M1Pa M1Pb

VDD

VCAS

VGGH

VGGLvo

a

vob

VPP

Bias

Advances in Robotics, Mechatronics and Circuits

ISBN: 978-1-61804-242-2 41

T0 = a0 f0 (3) The overall closed loop transimpedance gain is:

A0 =vout,diffiinput

≈2a01+T0

(4)

where iinput=iin/2 and vout,diff=voa−vob. The time constant at the input of the common gate is:

τ in ≈ Cin RF ||1gm1*

"

#$

%

&' (5)

where Cin = CP + CF + Cgs1 +Csb1+Cddp1 and Cddp1 = Cgdp1+Cdbp1. The time constant at the output of the common gate (that is the input of the common source) is:

τ 2 ≈ R1 ⋅C2 (6) where C2=Cgd1+Cdb1+Cgs2+Cgd2(1+gm2/gm2C

*). The time constant at the node between the common source transistor and the cascode transistor is:

τ 2C ≈1g

m2C

* C2C   (7)

where C2C = Cdb2+Cgs2C+Csb2C. The time constants at the output of the common source stage (that is the input of the source follower) are:

τ 3in ≈ R2 ⋅C3in  and τ 3m ≈ Cgs3R2 + RLpgm3RLp +1

  (8)

where C3in=Cdb2C+Cgd2C+Cgd3. The time constant at the output of the source follower is:

τ 3out ≈ RLP ⋅ CF +Csb3( )  (9)

The −3dB bandwidth of the TIA is estimated using the zero value time constant (ZVTC) method:

f−3dB ≈1+T0

2π τ ifor all i∑

(10)

The input referred current noise power spectral density (PSD) is due to four primary sources: 1) the input referred current noise PSD due to RF, 2) the input referred current noise PSD due to MB1, 3) the input referred current noise PSD due to R1, and 4) the input referred current noise PSD due to M1P.

inoise2

Δf=124KTRF

+ 4KTγngmB1 +4KTR1ACG2 +

"

#$

+4KTγ pgm1PR12

ACG2

%

&'

(11)

III. OPTIMIZATION STRATEGY For nanoscale devices the traditional analog design

methodology based on modeling transistors’ behavior through closed-form “square-law” equations is inaccurate and it results

in an excessively large number of iterations. The square-law design equations are based on physical parameters (µCox, Vth, Vdsat, etc.) that for short channel transistors are ill-defined, so achieving optimal performances by properly sizing the components of the circuit is extremely difficult.

Fig. 5 TIA AC half circuit with feedback loading and relevant

capacitances

In this paper rather than using the traditional “square law” methodology we propose to use a gm/ID based methodology. When designing with nanoscale transistors the gm/ID methodology has two main advantages. First, instead of relying on ill defined physical parameters (e.g. µCox, Vth, Vdsat, etc.) we can use design parameters (e.g. gm, fT. ID, etc.) that are well defined at any scale and are easier to link with the specifications (e.g. power consumption, bandwidth, etc.). Second, devices can be modeled in the form of look up tables (or charts) rather than closed-form equations. In the case of nanoscale technologies look-up tables provides a more accurate and practical choice.

The key to optimally size transistors is to generate a set of look-up tables that are independent of the transistor gate width W. In this way the design can be carried out independently of transistors geometry. The optimization process is driven simply by the design specifications and a relevant set of figures of merit. In the proposed framework the figures of merit used are: 1) the transconductance efficiency gm/ID, 2) the transient frequency fT, 3) the intrinsic gain gmro, and 4) the current density ID/W. The look-up tables are generated characterizing the given technology through HSPICE. From an analog design perspective, a large gm/ID allows to achieve low-power and high gain circuits, while a small gm/ID is suitable for high-speed applications. Table I summarizes the properties that characterize an analog design at different levels of transconductance efficiency. Fig. 6 illustrates the trade off between transconductance efficiency and transient frequency of a 0.18µm nMOS technology at different levels of inversion Vov. Fig. 7(a)-(c) plots the transient frequency, the intrinsic gain, and the current density of a 0.18 µm nMOS technology for different values of channel length L.

Given the TIA specifications (0.18 µm CMOS technology. closed loop transimpedance gain of 60 dbΩ, 2 pF photodiode, 250Ω load, total current budget up to 16 mA, and an input referred current noise PSD up to 160×10−24 A2/Hz) the goal of the design is to maximize speed. The optimization flow

M1

R1

iin M2

M2C

R2

M3

RLRF CF RF CF

Cgd2C+Cdb2C+Cgd3

Cp

Cgs1+Csb1Csb3

Cdb2+Cgs2C+Csb2C

Cgd1+Cdb1+Cgs2+Cddp1

Cgd2

Cgs3

vin

v1

v2

vout

Advances in Robotics, Mechatronics and Circuits

ISBN: 978-1-61804-242-2 42

applied to the TIA design can be described as follows: 1. Set the loop gain T0 to an appropriate value

(T0 ≥ 10) and derive RF based on the design objectives (A0 ≥ 60 dBΩ).

2. Set gm/ID for the transistor M3 (source follower) to allow max output signal swing (that is VIN3 = VDD/2) and compute the corresponding transient frequency fT. Select and appropriate value of bias current based on Cgg3 such that the time constants associated with the source follower are not dominant. Estimate the parasitic capacitances and compute the resulting gain ACD of the source follower.

Cgg3 =gm32π fT 3

(12)

ID3 =gm3

gm3 / ID3 (13)

Fig. 8 summarizes the design exploration process described in this step.

3. Partition the amount of gain needed to meet specification between the common source and the common gate:

ACSACG =aoACD

(14)

An excessive value of ACS causes a strong miller effect at the intermediate node between the transistors M2 and M2C and results in a non optimal value of the dominant time constant τ2. Similarly an excessive value of ACG implies an excessive value of R1 and results in a suboptimal value of the dominant time constant τ2. Appropriate values of ACS and ACG are in the following ranges:

1≤ ACS ≤10 and  ao

ACDACSmax

≤ AGC ≤aoACD

(15)

4. Set gm/ID of transistor M1 and the value of R1 as the primary design variables. The values of gm1/ID1 and R1 set the value of ACG. The value of ACG set the value of ACS and therefore the value of gm2/ID2 and R2.

5. Sweep gm1/ID1 from weak inversion region (gm/ID=25 S/A) to strong inversion region (gm/ID=5 S/A) and R1 from ACG_min to ACG_max. Register the performance metrics of every feasible design in the explored space. Design feasibility and the current bias for the CG and CS are determined by the bias constrains.

6. Determine gm1/ID1, ID1, R1, ACG, gm2/ID2, ID2, R2, ACS, gm3/ID3, ID3, and ACD for the TIA design that achieves the best bandwidthS2.

7. Finally, determine transistor widths from gm/ID, the calculated ID, and the current density (ID/W) look-up tables.

TABLE I. TRANSISTOR’S PROPERTIES AT DIFFERENT LEVELS OF TRANSCONDUCTANCE EFFICIENCY

Transconductance Efficiency

Low gm/ID High gm/ID

Strong Inversion Weak Inversion

Poor power efficiency Good power efficiency

Low output voltage range High output voltage range

High Transient Frequency Low Transient Frequency

Small Transistor Large Transistor

Fig. 6 Plot of gm/ID and fT at different levels of inversion Vov

for an nMOS transistor with channel length L = 0.18µm (0.18µm CMOS process)

IV. EXPERIMENTAL RESULTS The proposed optimization framework has been applied to the design of a high gain, high speed, low noise, low power TIA implemented in a standard 0.18 µm CMOS process. The experimental results match well (within 11.3%) the analytical results obtained through the MATLAB optimization scripts. Table II summarizes and compares the results. Table III summarizes the value of all devices employed in the design of the TIA. To optimize bandwidth all transistors in the signal path have minimum channel length of L=0.18µm. In contrast, all biasing transistors have channel length of L=0.36µm. As long as using longer channel length does not causes excessive parasitic capacitance, this choice has the advantage of reducing the loading caused by the bias transistors on the signal path transistors (higher channel length implies higher output resistance) and it lowers the sensitivity of the circuit to PVT variations. Fig. 9 shows the frequency response of the TIA with and without compensation. The value of the compensation capacitance CF is calculated using MATLAB root locus plots. The closed loop zeros and poles location is determined through HSPICE pole/zero analysis. Fig. 10 shows the root locus of the amplifier without compensation. After compensation the peaking in the frequency response is completely eliminated and the phase margin is PM=45.19°. Fig.11 shows the input referred current spectral density of the

−0.2 −0.1 0 0.1 0.2 0.30

5

10

15

20

25

30

g m/I D

[S/A

]; f T [G

Hz]

Vov [V]

gm/ID and fT design tradeoff

gm/IDfT

Strong InversionWeak Inversion

Moderate Inversion

Advances in Robotics, Mechatronics and Circuits

ISBN: 978-1-61804-242-2 43

system.

Fig. 7 (a)-(c) Plots of fT, gmro, and ID/W vs. gm/ID for nMOS

transistors with channel length L varying from 0.18µm to 0.4µm (0.18µm CMOS process)

Fig. 8 Source follower design optimization:

Cgg capacitance vs. gm/ID and gain ACD

TABLE II. COMPARISON BETWEEN ANALYTICAL RESULTS AND EXPERIMENTAL RESULTS

Performance Metric Analysis Simulation % Relative Error

Gain [dBΩ] 65.37 65.50 −0.20

f3db [GHz] 2.49 2.44 2.01

Input ref. noise [pA/√Hz] 11.99 11.91 0.67

Power dissipated [mW] 20.34 18.32 11.03

Phase Margin [degrees] 47.48 45.19 5.07

TABLE III. TIA DEVICE SIZES

Device TIA Device Sizing

CPa, CPb [pF] 2

RLa, RLb [Ω] 250

R1a, R1b [Ω] 2300

R2a, R2b [Ω] 590

RFa, RFb [Ω] 1000

CFa, CFb [fF] 110

M1a, M1b [µm] L=0.18; W=160

M1Pa, M1Pb [µm] L=0.36; W=50

MB1a, MB1b [µm] L=0.36; W=150

M2a, M2b [µm] L=0.18; W=80

M2Ca, M2Cb [µm] L=0.18; W=50

MB2 [µm] L=0.36; W=460

M3a, M3b [µm] L=0.18; W=32

MB3a, MB3b [µm] L=0.36; W=220

5 10 15 200

5

10

15

20

25

30

35

gm/ID [S/A]

f T [GH

z](a) Transit frequency vs. gm/ID

L=0.4um

L=0.18um

5 10 15 2020

30

40

50

60

70

80

90

100

gm/ID [S/A]

g mur o

(b) Intrinsic gain vs. gm/ID

L=0.4um

L=0.18um

5 10 15 20100

101

102

gm/ID [S/A]

I D/W

[A/m

]

(c) Current density vs. gm/ID

L=0.18um

L=0.4um

6 8 10 12 14 16 18 200.4

0.45

0.5

0.55

0.6

0.65

0.7

0.75 Cgg [fF] (plot only Cgg < 200 fF)

gm/ID [S/A]

A CD [V

/V]

40

60

80

100

120

140

160

180

Advances in Robotics, Mechatronics and Circuits

ISBN: 978-1-61804-242-2 44

Fig. 9 TIA frequency response with and without compensation

Fig. 10 Root Locus of TIA before compensation

Fig. 11 TIA input referred current noise spectral density

V. CONCLUSION This paper presents a framework for optimizing the design

of nanometer analog and mixed analog-digital integrated

circuits. The viability and accuracy of the framework is validated by applying it to the design of a transimpedance front-end amplifier for a fiber optic receiver. The TIA consists of a cascade of a common gate, a common source and a source follower surrounded by a shunt-shunt feedback with phantom zero compensation. It achieves a transimpedance gain of 65.5 dBΩ, a bandwidth of 2.44 GHz, and an input referred current noise spectral density of 11.91 pA/√Hz. The amplifier is implemented in a standard 0.18µm digital CMOS process and it dissipates 18.32mW from a single 1.8 V supply.

REFERENCES [1] Sung Min Park and Hoi-Jun Yoo, “1.25-Gb/s Regulated Cascode CMOS

Transimpedance Amplifier for Gigabit Ethernet Applications,” IEEE Journal of Solid State Circuits, vol. 39, no. 1, pp. 112-121, Jan. 2004.

[2] B. Murmann, Analysis and Design of Elementary MOS Amplifier Stages, NTS Press, 2013.

[3] F. Silveira, D. Flandre, and P.G.A. Jesper, “A gm/ID based Methodology for the Design of CMOS Analog Circuits and its Application to the Synthsis of a Silicon-on-Insulator Micropower OTA,” IEEE Journal of Solid State Circuits, vol. 31, no.9, pp. 1314-1319, Sept. 1996.

[4] B. Murmann, Analysis and Design of Elementary MOS Amplifier Stages, NTS Press, 2013.

[5] B. Razavi, Design of Integrated Circuits for Optical Communications, 2nd ed., Hoboken, New Jersey: Wiley, 2012, pp. 1–7.

[6] H.M. Lavasani et al., “A 76 dbΩ 1.7 GHz 0.18µm CMOS Tunable TIA Using Broadband Current Pre-Amplifier for High Frequency Lateral MEMS Oscillators,” IEEE Journal of Solid State Circuits, vol.44, no.1, pp. 224-235, january 2011.

[7] Chih-Fan Liao and Shen-Iuan Liu, “10 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS,” IEEE Journal of Solid State Circuits, vol.43, no.3, pp. 642-655, March 2008.

[8] J. Salvia, P. Lajevardi, M. Hekmat and B. Murmann, “A 56MΩ CMOS TIA for MEMS Applications,” IEEE Custom Integrated Circuits Conference, pp. 199-202, 2009.

Claudio Talarico received B.S. and M.S. degrees in Electrical Engineering from University of Genova, Italy and a Ph.D. degree in Electrical Engineering from University of Hawaii. He is currently an Associate Professor of Electrical and Computer Engineering at Gonzaga University. Before joining Gonzaga University, he worked at Eastern Washington University, University of Arizona, and in industry, where he held both engineering and management positions at Siemens Semiconductors, IKOS Systems, and Marconi Communications. Dr. Talarico research interests include digital and mixed analog/digital integrated circuits and systems, computer-aided design methodologies, and design and analysis of embedded systems-on-chip. Gaurav Agrawal received M.S. degree in Electrical and Computer Engineering from the University of Texas at Austin in 2007. He is currently employed at Google and has previously held hardware-engineering positions at Cisco Systems, NVIDIA and Texas Instruments. His research interests include parallel computing, electronic design automation, and design of high-speed digital integrated circuits. Janet M. Wang-Roveda received a B.S. degree in computer science from The East China Institute in 1991, M.S., and Ph.D. degrees in electrical engineering and computer sciences from the University of California, Berkeley in 1998 and 2000, respectively. She is currently an associate professor in electrical and computer engineering department at the University of Arizona. Her primary research interests focus on robust VLSI circuit design, biomedical instrument design, Smart grid, VLSI circuit modeling and analysis, and low power multi-core system design. Dr. Roveda was a recipient of the NSF career award and the PEACASE award in 2005 and 2006, respectively. She received the best paper award in ISQED 2010 as well as best paper nominations in ASPDAC 2010, ICCAD 2007, and ISQED2005. She is the recipient of the 2008 R. Newton Graduate Research Project Award from DAC, and the 2007 USS University of Arizona Outstanding Achievement Award.

104 106 108 1010−10

0

10

20

30

40

50

60

70

80 G

ain

[dB1

]

Frequency [Hz]

TIA Frequency Response

w/o compensationwith compensation

−2.5 −2 −1.5 −1 −0.5 0 0.5x 1011

−3

−2

−1

0

1

2

3x 1011

Root Locus w/o compensation

Real Axis (seconds−1)

Imag

inar

y Ax

is (s

econ

ds−1

)

104 106 108 10100

50

100

150

200

250

300

350

400

450

500

Frequency [Hz]

noi

se c

urre

nt s

pect

ral d

ensi

ty [p

A/H

z1/2 ]

TIA input referred noise

Advances in Robotics, Mechatronics and Circuits

ISBN: 978-1-61804-242-2 45