transimpedance amplifier design using 0.18 µm cmos technology

Transimpedance Amplifier Design using 0.18 µm

CMOS Technology

by

Ryan Douglas Bespalko

A thesis submitted to the

Department of Electrical and Computer Engineering

in conformity with the requirements for

the degree of Master of Science (Engineering)

Queen’s University

Kingston, Ontario, Canada

July 2007

Copyright c© Ryan Douglas Bespalko, 2007

Abstract

This thesis examines the design of high speed transimpedance amplifiers (TIAs) in

low cost complimentary metal oxide semiconductor (CMOS) technology. Due to

aggressive scaling, CMOS has become an attractive technology for high speed analog

circuits. Besides the cost advantage, CMOS offers the potential for higher levels of

integration since the analog circuits can be integrated with digital electronics on the

same substrate.

A 2.5 Gbps transimpedance amplifier fabricated using 0.18 µm CMOS technology

is presented. The TIA uses a shunt-shunt feedback topology with a cascode gain stage.

Measurements of the transimpedance gain, group delay, and common mode rejection

ratio are presented for the TIA and show a good match to simulated results. The

noise of the TIA was characterized by measuring the noise parameters of the TIA.

The noise parameters are then used to determine the input referred noise current

spectral density.

A 10 Gbps transimpedance amplifier fabricated using 0.18 µm CMOS technology is

also presented. This TIA uses a shunt-shunt feedback topology with a common source

gain stage. In order to achieve the required bandwidth, the TIA uses a bandwidth

extension technique called shunt-series inductive peaking. A discussion of the different

methods of bandwidth extension using inductive peaking is included, and the optimal

configurations for maximally flat responses are shown for shunt inductive peaking,

series inductive peaking, and shunt-series inductive peaking. The TIA circuit topology

is optimized using a novel noise analysis that uses a high frequency noise model for the

i

transistor. The optimum transistor size and bias current are determined to minimize

the amplifier noise. Unfortunately differential measured results are not available

due to a stability problem in the amplifier. The cause of this instability is further

explored and modifications to solve the problem are discussed. Single-ended results

are presented and show reasonable agreement with simulated results. Differences in

the results are attributed to poor modelling of the on-chip spiral inductors.

ii

Acknowledgments

This section is to acknowledge the people and organizations that have generously

assisted in the completion of this thesis.

First, I’d like to thank my thesis supervisor Dr. Brian Frank for his interest and

enthusiasm over the past years. His guidance and support, as well as his extensive

knowledge of CMOS circuit design have been instrumental in making this thesis a

success. I’d also like to thank my other thesis supervisor Dr. John Cartledge for

his support, particularly in the area of photonics. His clear teaching style has made

optical communications understandable, even for a circuit designer.

Second, I’d like to thank the students in the Very High Speed Circuits lab at

Queen’s University. Thank you for the many useful discussions which have been a

great help, as well as the occasional much needed distraction during the many long

hours in the lab.

Financial support for this work has been provided by the Natural Sciences and

Engineering Research Council (NSERC), the Canadian Institute for Photonic Inno-

vations (CIPI), as well as Queen’s University.

Finally I’d like to thank my family for their continued support. You’ve always

been there to help me follow my dreams.

iii

Table of Contents

Abstract i

Acknowledgments iii

Table of Contents iv

List of Tables vii

List of Figures viii

Nomenclature xii

Chapter 1 Introduction 11.1 Fiber to the Home . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Common Access Network Architectures . . . . . . . . . . . . . 21.1.2 Multiple Access Techniques for PONs . . . . . . . . . . . . . . 31.1.3 Integrated Optical Transceiver . . . . . . . . . . . . . . . . . . 6

1.2 Challenges of CMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . 71.3 Thesis Overview and Major Contributions . . . . . . . . . . . . . . . 7

Chapter 2 Background Theory 102.1 Optical Receiver - Basic Theory . . . . . . . . . . . . . . . . . . . . . 10

2.1.1 Receiver Sensitivity . . . . . . . . . . . . . . . . . . . . . . . . 112.1.2 Integrated Transceiver . . . . . . . . . . . . . . . . . . . . . . 18

2.2 Transimpedance Amplifiers . . . . . . . . . . . . . . . . . . . . . . . . 192.3 Common TIA topologies . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3.1 Open Loop TIAs . . . . . . . . . . . . . . . . . . . . . . . . . 232.3.2 Feedback TIAs . . . . . . . . . . . . . . . . . . . . . . . . . . 252.3.3 Bandwidth Considerations . . . . . . . . . . . . . . . . . . . . 26

Chapter 3 Literature Review 313.1 Transimpedance Amplifier Topologies . . . . . . . . . . . . . . . . . . 31

3.1.1 Regulated Cascode TIA . . . . . . . . . . . . . . . . . . . . . 313.1.2 DC Coupled Common Gate TIA . . . . . . . . . . . . . . . . 333.1.3 Feedback TIAs . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.2 Bandwidth Extension . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.2.1 Shunt Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

iv

3.2.2 Series Inductive Peaking . . . . . . . . . . . . . . . . . . . . . 383.2.3 Shunt and Series Peaking . . . . . . . . . . . . . . . . . . . . . 39

Chapter 4 2.5 Gbps Transimpedance Amplifier Design 414.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414.2 The Cascode Structure . . . . . . . . . . . . . . . . . . . . . . . . . . 41

4.2.1 Miller Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424.2.2 Cascode vs. Common Source . . . . . . . . . . . . . . . . . . 44

4.3 2.5 Gbps TIA Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 454.3.1 Variable Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 464.3.2 Final Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494.5 Measured Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

4.5.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . 554.5.2 Transistor Model Verification . . . . . . . . . . . . . . . . . . 554.5.3 Transimpedance Measurements . . . . . . . . . . . . . . . . . 594.5.4 Group Delay Measurements . . . . . . . . . . . . . . . . . . . 614.5.5 Noise Measurements . . . . . . . . . . . . . . . . . . . . . . . 624.5.6 Common Mode Rejection Ratio Measurement . . . . . . . . . 66

4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Chapter 5 10 Gbps Transimpedance Amplifier 735.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735.2 Inductive Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.2.1 Shunt and Series Inductive Peaking . . . . . . . . . . . . . . . 745.2.2 Shunt-Series Inductive Peaking . . . . . . . . . . . . . . . . . 79

5.3 10 Gbps TIA Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 865.3.1 Noise Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . 885.3.2 Optimum Device Size . . . . . . . . . . . . . . . . . . . . . . . 925.3.3 Final Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 975.3.4 On-Chip Inductors . . . . . . . . . . . . . . . . . . . . . . . . 975.3.5 Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

5.4 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1015.4.1 Front-End Tuning . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.5 Measured Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1065.5.1 Inductor Measurements . . . . . . . . . . . . . . . . . . . . . . 1065.5.2 Differential Measurements . . . . . . . . . . . . . . . . . . . . 1065.5.3 Single-Ended Measurements . . . . . . . . . . . . . . . . . . . 110

5.6 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

Chapter 6 Conclusions and Future Work 1146.1 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1146.2 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

References 118

v

Appendices

Appendix A Noise Model Calculations 122A.1 High Frequency Noise Model . . . . . . . . . . . . . . . . . . . . . . . 122A.2 Common Source Transistor Model with Resistive Feedback . . . . . . 124A.3 Calculating Noise Parameters from ABCD Representation . . . . . . 126

Appendix B Noise Measurements 130B.1 Determining Device Noise Parameters . . . . . . . . . . . . . . . . . . 130

B.1.1 R. Q. Lane Method . . . . . . . . . . . . . . . . . . . . . . . . 131B.2 Noise Parameter Measurement Procedure . . . . . . . . . . . . . . . . 133

B.2.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . 133B.2.2 Source Impedance Measurement . . . . . . . . . . . . . . . . . 133B.2.3 Noise Figure Measurement . . . . . . . . . . . . . . . . . . . . 134B.2.4 Loss Compensation . . . . . . . . . . . . . . . . . . . . . . . . 135

vi

List of Tables

1.1 PON Data Transmission Rates and Wavelengths . . . . . . . . . . . . 5

1.2 GPON Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4.1 2.5 Gbps TIA Component Values . . . . . . . . . . . . . . . . . . . . 48

4.2 2.5 Gbps TIA Performance Comparison . . . . . . . . . . . . . . . . . 71

5.1 Values of m for Shunt and Series Inductive Peaking . . . . . . . . . . 76

5.2 10 Gbps TIA Component Values . . . . . . . . . . . . . . . . . . . . 99

5.3 10 Gbps TIA Performance Comparison . . . . . . . . . . . . . . . . . 113

vii

List of Figures

1.1 Common Access Network Architectures . . . . . . . . . . . . . . . . . 2

1.2 Passive Optical Network Architecture . . . . . . . . . . . . . . . . . . 4

2.1 Basic Optical Receiver Block Diagram . . . . . . . . . . . . . . . . . 11

2.2 Probability Density Function . . . . . . . . . . . . . . . . . . . . . . . 12


2.4 MIC Block Diagram for an Integrated Transceiver . . . . . . . . . . . 18

2.5 Transimpedance Amplifier . . . . . . . . . . . . . . . . . . . . . . . . 19

2.6 Input Referred Noise Current . . . . . . . . . . . . . . . . . . . . . . 20

2.7 Photodiode and Simple Transimpedance Amplifier . . . . . . . . . . . 21


2.9 Common Gate TIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.10 Feedback TIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.11 Response of a Second Order Filter to Random Data . . . . . . . . . . 28

2.12 Response of a Filter with a Low Frequency Cut-off of 20 MHz to Ran-

dom Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.1 Regulated Cascode TIA . . . . . . . . . . . . . . . . . . . . . . . . . 32

3.2 DC Coupled Common Gate TIA . . . . . . . . . . . . . . . . . . . . . 33

3.3 Feedback TIA Topologies . . . . . . . . . . . . . . . . . . . . . . . . . 35

3.4 Shunt Inductive Peaking . . . . . . . . . . . . . . . . . . . . . . . . . 37

3.5 TIA Using Series Inductive Peaking . . . . . . . . . . . . . . . . . . . 38

viii

3.6 Shunt and Series Inductive Peaking . . . . . . . . . . . . . . . . . . . 39

4.1 Common Source and Cascode Amplifiers . . . . . . . . . . . . . . . . 42

4.2 Common Source Equivalent Circuit . . . . . . . . . . . . . . . . . . . 43

4.3 Miller Theorem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

4.4 Differential Cascode TIA . . . . . . . . . . . . . . . . . . . . . . . . . 46

4.5 Cascode TIA with AGC . . . . . . . . . . . . . . . . . . . . . . . . . 47

4.6 2.5 Gbps TIA Final Schematic . . . . . . . . . . . . . . . . . . . . . . 48

4.7 Current Mirror . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

4.8 2.5 Gbps TIA Chip Photo . . . . . . . . . . . . . . . . . . . . . . . . 50

4.9 2.5 Gbps TIA Chip Plot . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.10 Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

4.11 Simulated Transimpedance Gain and Input Referred Noise Current . 52

4.12 Estimated BER for the 2.5 Gbps TIA . . . . . . . . . . . . . . . . . . 54

4.13 Simulation Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4.14 S-Parameters for a 30 Finger Common Source Transistor . . . . . . . 57

4.15 S-Parameters for a 30 Finger Common Source Transistor . . . . . . . 58

4.16 Simulated vs. Measured Transimpedance . . . . . . . . . . . . . . . . 59

4.17 Simulated and Measured Transimpedance Gain with Various AGC

Voltages - CPD = 0 fF . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.18 Simulated and Measured Transimpedance Gain with Various AGC

Voltages - CPD = 250 fF . . . . . . . . . . . . . . . . . . . . . . . . . 60

4.19 Simulated vs. Measured Phase and Group Delay - AGC = 0.0 V . . . 61

4.20 Simulated vs. Measured Phase and Group Delay - AGC = 3.0 V . . . 62

4.21 Noisy Two-port Network Representation . . . . . . . . . . . . . . . . 63

4.22 Simplified Noisy Two-port Network Representation . . . . . . . . . . 63

4.23 TIA Noise measurements AGC = 0.0 V . . . . . . . . . . . . . . . . . 67

4.24 TIA Noise measurements AGC = 3.5 V . . . . . . . . . . . . . . . . . 68

ix

4.25 Port Numbering Convention . . . . . . . . . . . . . . . . . . . . . . . 69

4.26 Measured Common Mode Rejection Ratio . . . . . . . . . . . . . . . 70

5.1 Various Methods of Inductive Peaking . . . . . . . . . . . . . . . . . 75

5.2 Bandwidth Improvement Using Shunt and Series Inductive Peaking . 78

5.3 Modified Shunt and Series Peaking for Interstage Bandwidth Extension 79

5.4 Resonance Frequencies Using Series Inductive Peaking . . . . . . . . 80

5.5 Frequency Response and Group Delay as the Series Inductance is Re-

duced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

5.6 Bandwidth Improvement Using Shunt, Series, and Shunt-Series Induc-

tive Peaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.7 Transient Response with a Bandwidth of Approximately 11 GHz . . . 84




5.11 Differential TIA Input Stage Using Shunt-Series Inductive Peaking . . 87

5.12 TIA Input Stage Half Circuit . . . . . . . . . . . . . . . . . . . . . . 88

5.13 Cascaded Networks . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.14 Cascaded Networks with Noise Sources . . . . . . . . . . . . . . . . . 90

5.15 Transimpedance Gain and Group Delay as the Transistor Size is Increased 94

5.16 Feedback Resistance versus Device Size . . . . . . . . . . . . . . . . . 94

5.17 Optimum Device Size for Various Values of the Drain Bias Current Iden 95

5.18 Optimum Current Density . . . . . . . . . . . . . . . . . . . . . . . . 96

5.19 Series Inductance versus Device Size . . . . . . . . . . . . . . . . . . 97

5.20 Transimpedance, Group Delay and Input Referred Noise Current using

the Optimum Device Size . . . . . . . . . . . . . . . . . . . . . . . . 98

5.21 10 Gbps TIA Schematic . . . . . . . . . . . . . . . . . . . . . . . . . 98

5.22 Monolithic Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

x

5.23 10 Gpbs TIA Die Photo . . . . . . . . . . . . . . . . . . . . . . . . . 101

5.24 10 Gbps TIA Chip Plot . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.25 Full Circuit Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.26 10 Gbps TIA with Front-End Tuning . . . . . . . . . . . . . . . . . . 104

5.27 Full Circuit Simulation with Front-End Tuning . . . . . . . . . . . . . 105

5.28 Inductor Test Structure Measurements . . . . . . . . . . . . . . . . . 107

5.29 10 Gbps TIA Measured Output Spectrum . . . . . . . . . . . . . . . 108

5.30 10 Gbps TIA Load and Source Stability Factor . . . . . . . . . . . . 109

5.31 10 Gbps TIA Load and Source Stability Factor with Source Connections110

5.32 10 Gbps TIA Single-ended Measurements . . . . . . . . . . . . . . . . 111

A.1 High Frequency Noise Model . . . . . . . . . . . . . . . . . . . . . . . 122

A.2 Noise Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . 123

A.3 Common Source Transistor with Feedback . . . . . . . . . . . . . . . 124

A.4 ABCD Representation with Noise . . . . . . . . . . . . . . . . . . . . 127

B.1 Noisy Two Port Network . . . . . . . . . . . . . . . . . . . . . . . . . 130

B.2 Noise Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . 134

B.3 Source Impedance Measurement Setup . . . . . . . . . . . . . . . . . 134

B.4 Loss Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

xi

Nomenclature

Latin Symbols

B Noise Bandwidth [Hz]

Bopt Optimum Source Susceptance [S]

Bcor Noise Correlation Susceptance [S]

CBP Bond Pad Capacitance [F]

CDS Drain to Source Capacitance [F]

CGD Gate to Drain Capacitance [F]

CGS Gate to Source Capacitance [F]

CPD Photodiode Capacitance [F]

D Decision Threshold [V]

F Noise Factor

Fmin Minimum Noise Factor

f3dB 3dB Bandwidth [Hz]

Ga Available Gain [dB]

Gcor Noise Correlation Conductance [S]

gm Transconductance [V/V]

gmb Back Gate Transconductance [V/V]

Gopt Optimum Source Conductance [S]

Gu Equivalent Noise Conductance [S]

I1 Pulse Shape Dependent Factor

xii

Iden Drain Current Density [A/m]

IN Input Referred Noise Current Source [A]

|in,in|2 Mean Squared Input Referred Noise Current [A2]√

|in,in|2 Input Referred Noise Current [A rms]√

d|in,in|2

dfInput Referred Noise Current Spectral Density [A/

√Hz]

k Boltzmann Constant [J/K]

LBW Bond Wire Inductance [H]

Pavg Average Optical Input Power [dBm]

Q Quality Factor

q Charge of an Electron [C]

R Responsivity [A/W]

Rb Bit Rate [bps]

rds Drain to Source Resistance [Ω]

re Extinction Ration [dB]

RFB Feedback Resistance [Ω]

Rn Equivalent Noise Resistance [Ω]

Sd1 Signal level for a 1

Sd0 Signal level for a 0

σ1 Noise power for a 1

σ0 Noise power for a 0

T Temperature [K]

Vd Drain Voltage [V]

Vg Gate Voltage [V]

VN Input Referred Noise Voltage Source [V]

|vn,out|2 Mean Squared Output Noise Voltage [V2]

Ycor Noise Correlation Impedance [Ω]

Yopt Optimum Source Impedance [Ω]

xiii

ZT Transimpedance [dBΩ]

Greek Symbols

ε Least Squares Error

Γopt Optimum Reflection Coefficient

Γout Output Reflection Coefficient

µ Stability Factor for the Load

µ′ Stability Factor for the Source

φ phase [rad]

τg Group Delay [s]

ω Angular Frequency [rad/s]

Acronyms

AC Alternating Current

ADS Advanced Design System

AGC Automatic Gain Control

APD Avalanche Photodiode

APON ATM Passive Optical Network

ATM Asynchronous Transfer Mode

BER Bit Error Rate

CMOS Complimentary Metal Oxide Semiconductor

CMRR Common Mode Rejection Ratio

DC Direct Current

DSL Digital Subscriber Line

DUT Device Under Test

EM Electro-Magnetic

EPON Ethernet Passive Optical Network

xiv

erfc Complimentary Error Function

GaAs Galium Arsenide

Gbps Giga bits per second

GPON Gigabit-capable Passive Optical Network

HDTV High Definition Television

IEEE Institute of Electrical and Electronics Engineers

InP Indium Phosphide

ISI Inter Symbol Interference

LA Limiting Amplifier

LD Laser Driver

Mbps Mega bits per second

MIC Microelectronic Integrated Circuit

nMOS n-type Metal Oxide Semiconductor

NRZ Non Return to Zero

OLT Optical Line Termination

ONU Optical Network Unit

P2P Point-to-Point

P2MP Point-to-Multi-Point

PIC Photonic Integrated Circuit

pMOS p-type Metal Oxide Semiconductor

PON Passive Optical Network

RGC Regulated Cascode

SCMA Subcarrier Multiple Access

TDMA Time Division Multiple Access

TSMC Taiwan Semiconductor Manufacturing Company

TIA Transimpedance Amplifier

VNA Vector Network Analyzer

xv

VoD Video on Demand

VoIP Voice over Internet Protocol

WDMA Wavelength Division Multiple Access

xvi

Chapter 1

Introduction

1.1 Fiber to the Home

Fiber optic networks are playing an increasingly important role in today’s communi-

cation networks, primarily in long haul and metropolitan systems. These networks

have created a large amount of low cost bandwidth that is the core of today’s net-

works. However, there still exists a large bottleneck in the last mile, or the local

access level of service between the metropolitan system and the home or business.

Due to the high cost of fiber-based implementations, hybrid fiber coax and digital

subscriber line (DSL) solutions currently dominate at the access level. However, due

to the ever expanding set of services being offered to residential homes, these tech-

nologies are having difficultly keeping up with the increased bandwidth requirements.

These services include high speed Internet, video on demand (VoD), voice over Inter-

net protocol (VoIP), and high definition television (HDTV). Other potential services

may include remote patient observation for medical purposes using video surveillance.

This would be aimed at cutting health care costs by allowing people to stay at home

during care. Another potential service would be teleworking, where people work from

home to reduce rush hour traffic [1].

DSL and cable modem technologies are constantly evolving and reaching higher

1

CHAPTER 1. INTRODUCTION 2

speeds to meet these demands. These speed increases generally come at the cost of

shorter link lengths, and result in further penetration of fiber into the access network.

Eventually, as customers continue to demand higher speed services, fiber will make

up the entire access network. The low loss and extremely wide bandwidth of optical

fiber make it capable of handling not only the current capacity, but also handling any

capacity challenges in the foreseeable future [1].

1.1.1 Common Access Network Architectures

There are three general network architectures that are considered in the access net-

work. The first is a Point-to-Point (P2P) architecture, shown in Figure 1.1 a), where

a dedicated fiber is run from the local exchange (optical line termination (OLT))

to each customer (optical network unit (ONU)). This type of architecture involves

a large initial cost since there is a lot of equipment required at the local exchange

and none of it is shared among customers. This system however, provides the largest

capacity since each link is independent and the bandwidth is not split among multiple

customers. This system also has the highest level of flexibility. Each connection can

be customized, and the services can be upgraded on a customer to customer basis.

OLT

ONU

ONU

ONU

ONU

LocalExchange

CustomerTerminations OLT

ONU

ONU

ONU

ONU

LocalExchange

CustomerTerminationsNode

Active

(a) (b)

Figure 1.1: Common Access Network Architectures a) Point-to-Point b) Active Star


The other two general architectures are both Point-to-Multi-Point (P2MP) net-

works. The first P2MP architecture is the active star shown in Figure 1.1 b). In this

system, a single fiber is run from the local exchange to an active node in the field

that is close to the end users. Individual fibers are then run from this node to each

of the customer terminations. The advantage of this system is that there is only one

fiber from the local exchange, which reduces the amount of equipment needed. The

actual terminal at the local exchange is more complex, but there is only one terminal

instead of one terminal for every customer. The disadvantage of this system is that

the active node requires power and maintenance.

The second P2MP architecture is the passive optical network (PON) shown in

Figure 1.2. In a PON, the active node in an active star architecture is replaced

with a passive optical splitter/combiner. This type of architecture benefits from the

reduced installation costs of a P2MP network and avoids the extra operational and

maintenance costs associated with an active star configuration. The only downside

is that the loss in the power splitter/combiner will result in slightly shorter link

lengths when compared to the active star configuration. For these reasons, PONs

show the most promise for implementing a fiber based solution in the access network.

The following sections will examine different PON configurations and discuss some

performance specifications for several standards that have been developed for PONs.

1.1.2 Multiple Access Techniques for PONs

Since the fiber that feeds the passive splitter/combiner in a PON is shared by every

customer, multiple access techniques need to be used to avoid data collisions. In

the downstream direction, all of the data is simply transmitted to every ONU, and

each ONU is responsible for selecting the appropriate data. In the upstream direc-

tion, multiple access techniques are needed to avoid collisions and multiplex the data

coming from each ONU.


OLT

ONU

ONU

ONU

ONU

Splitter/Combiner

Passive OpticalPower

LocalExchange

CustomerTerminations

Figure 1.2: Passive Optical Network Architecture

There are several different proposed multiple access techniques that can be used.

The first is time division multiplexing (TDMA), where each ONU is given a time

slot where it is allowed to transmit data. The OLT controls the data transfer using

message passing to each ONU to allocate it time to transmit. Ranging functions are

needed to determine the distance from each ONU to the OLT to ensure proper timing.

A second proposed method is sub-carrier multiple access (SCMA). SCMA has each

ONU modulate their packet streams on unique electrical carrier frequencies. Another

option is wavelength division multiple access (WDMA), where each ONU transmits

data at a different optical wavelength.

TDMA methods show the most promise because they are able to achieve high data

rates with moderate complexity. Standards have been developed for several different

TDMA methods. The first is the ATM PON (APON) standard that divides the data

into native ATM cells. This is outlined in the G.983 standard of the ITU-T SG15.

Another standard has been developed for an Ethernet PON (EPON), which carries

gigabit Ethernet packets. The EPON is covered in the IEEE 802.3 standard. Finally,

a third standard called the Gigabit PON (GPON) has been developed that is able

to send both ATM cells and Ethernet packets. These standards specify a number of

different bit rates for the downstream and upstream data. These values are listed in


Table 1.1 along with the upstream and downstream wavelengths.

Table 1.1: PON Data Transmission Rates and Wavelengths

APON EPON GPONDownstream Wavelength 1500 nm 1490 nm or 1510 nm 1480-1500 nmUpstream Wavelength 1300 nm 1310 nm 1260-1360 nm

Downstream Bit Rate 155 Mbps, 1.25 Gbps 1.25 Gbps,622 Mbps 2.5 Gbps

Upstream Bit Rate 155 Mbps 1.25 Gbps 155 Mbps,622 Mbps1.25 Gbps2.5 Gbps

Table 1.2 shows some important specifications from the GPON standard. The

values listed in the table concern the specifications for transmitting and receiving

data in the downstream direction at a bit rate of 2.5 Gbps. There are three separate

classes listed. Each class has different specifications for the power launched at the

transmitter, and the required sensitivity of the receiver. Class C is intended to use

an avalanche photodiode (APD), which allows for a better sensitivity.

Table 1.2: GPON Standard

Transmitter SpecificationsNominal Bit rate 2488.32 Mbps

Operating Wavelength 1480 - 1500 nmLine Code Scrambled NRZ

Class A B CMean Launched Power MIN 0 dBm 5 dBm 3 dBmMean Launched Power MAX 4 dBm 9 dBm 7 dBm

Extinction Ratio more than 10 dB

Receiver SpecificationsBit Error Rate (BER) less than 10−10

Class A B CMinimum Sensitivity -21 dBm -21 dBm -28 dBmMinimum Overload -1 dBm -1 dBm -8 dBm

Consecutive Identical Digit Immunity more than 72

The transimpedance amplifier designed in chapter 4 is designed to meet this


GPON specification for 2.5 Gbps transmission. The transimpedance amplifier de-

signed in chapter 5 has been designed for a bit rate of 10 Gbps and is intended for

future higher speed applications.

1.1.3 Integrated Optical Transceiver

While the majority of the cost of installing fiber in the access level is the digging

and ducting required to run the fiber (roughly 85% [1]), there is still a lot of room to

reduce the link cost. Since the transceivers at each termination represent 70-80% of

the total link cost (not including the digging and ducting), the total system cost can

be reduced significantly by lowering the transceiver cost.

Transceivers that are currently available use a number of discrete components that

add to the component cost, as well as the manufacturing cost of each transceiver. An

integrated solution can significantly reduce the cost, and provide better performance

because components can be optimized to work together. A two chip solution has been

proposed by researchers at Queen’s University and McMaster University consisting

of one photonic integrated circuit (PIC) and one microelectronic integrated circuit

(MIC). The PIC will integrate a wavelength multiplexer with a photodiode and laser,

while the MIC will integrate the receiver and transmitter electronics onto a single

complimentary metal oxide semiconductor (CMOS) integrated circuit. The receiver

electronics will consist of a transimpedance amplifier (TIA), and a limiting amplifier.

The transmitter electronics will consist of a pre-amplifier, and a laser driver (LD).

The focus of this thesis is work on the MIC, particularly the transimpedance amplifier

at the input of the receiver portion of the circuit.


1.2 Challenges of CMOS

Traditionally, analog circuits used in optical communication systems are implemented

using Gallium Arsenide (GaAs) or Indium Phosphide (InP) technologies. These pro-

cesses are designed for high speed circuits, and have been traditionally the only tech-

nologies able to produce the high bandwidth circuits required in optical communica-

tion systems. However, due to the aggressive scaling of the CMOS process, it is now

becoming possible to design high performance analog circuits in CMOS. The primary

advantage of moving to a CMOS process is a dramatic reduction in cost due to its

widespread use in high volume digital circuits. Another advantage of using CMOS is

its ability to integrate digital and analog circuits onto the same substrate.

1.3 Thesis Overview and Major Contributions

This thesis focuses on the design of high speed transimpedance amplifiers in CMOS

technology. The chapters of the thesis are organized as follows.

Chapter two reviews the important background theory relevant to the thesis.

First, some basic theory on optical receivers is presented and the role of the TIA in

an optical receiver is discussed. Next, a method for estimating the sensitivity of an

optical receiver is covered. Finally, the important performance specifications for a

TIA are given, and some general topologies are discussed.

In chapter three a literature review is presented of the current work that has been

done in the area of high speed transimpedance amplifier design using CMOS tech-

nology. A number of different open loop and feedback topologies are examined and

their performance is compared. A review is also done on common bandwidth exten-

sion techniques used to improve the performance of CMOS TIAs. Shunt inductive

peaking, series inductive peaking, and shunt-series inductive peaking are discussed.

Chapter four presents a 2.5 Gbps transimpedance amplifier fabricated using 0.18 µm


CMOS technology. The TIA uses a shunt-shunt feedback topology with a cascode gain

stage. The cascode topology is used to reduce the input capacitance of the amplifier

and increase the bandwidth. The amplifier has been designed to be pseudo differential

in order to improve the common mode rejection. This is important because the in-

tended application of the TIA is an integrated transceiver. The differential structure

will help reduce the impact of noise coupled into the TIA from other system com-

ponents. The TIA also has a variable gain to increase the range of acceptable input

powers such that the amplifier isn’t saturated. Simulation results show a maximum

transimpedance gain of 64 dBΩ and a bandwidth of 1.8 GHz with a photodiode ca-

pacitance of 250 fF. The average input referred noise current spectral density over the

TIA bandwidth is 9.0 pA/√

Hz. Using the variable gain control the TIA bandwidth

can be reduced to 46 dBΩ. Measured results are presented for the TIA and show a

good match to simulated results. Measurements of the transimpedance gain, group

delay, and common mode rejection ratio are presented. The noise of the TIA was

characterized by measuring the noise parameters of the TIA. The noise parameters

are then used to determine the input referred noise current spectral density.

Chapter five presents the design of a 10 Gbps transimpedance amplifier using

0.18 µm CMOS technology. This TIA uses a shunt-shunt feedback topology with a

common source gain stage. In order to achieve the required bandwidth, the TIA uses a

bandwidth extension technique called shunt-series inductive peaking. This technique

uses both a shunt and series connected inductor to create multiple resonant structures

that increase the amount of current available to charge the output capacitance. Like

the TIA in chapter four, this TIA has been designed to be pseudo differential in order

to increase the common mode rejection ratio. The chapter begins with a discussion of

the different methods of bandwidth extension using inductive peaking. The optimal

configurations for maximally flat responses are shown for shunt inductive peaking,

series inductive peaking, and shunt-series inductive peaking. Next, the TIA circuit


topology is optimized using a novel noise analysis using a high frequency noise model

for the transistor. The optimum transistor size and bias current are determined to

minimize the amplifier noise. Simulation results are presented for the amplifier, and

show that with inductive front-end tuning, the TIA can achieve a transimpedance

gain of 45 dBΩ with a bandwidth of 12 GHz. Unfortunately differential measured

results are not available due to a stability problem in the amplifier. The cause of this

instability is further explored and modifications to solve the problem are discussed.

Single-ended results are presented and show reasonable agreement with simulated

results. Differences in the results are attributed to poor modelling of the on-chip

spiral inductors.

Finally, chapter six concludes the work contained in the thesis and summarizes

the results. Areas of further work are also explored.

Chapter 2

Background Theory

2.1 Optical Receiver - Basic Theory

The most basic optical receiver consists of a photodiode and a transimpedance am-

plifier. The photodiode is a square law device, which means the detected electrical

current depends on the power of the incident optical signal. The TIA amplifies this

electrical current with sufficient bandwidth, converting it to a voltage, while adding

as little noise as possible. Generally, the TIA output signal is still not large enough to

reach detectable logic levels (approximately 500 mVp-p) so additional amplification

is added in the form of a limiting amplifier (LA). A limiting amplifier has a high gain

and a large output voltage swing. The input signal is amplified until it is saturated

at the amplifier voltage rails. This has the effect of producing a reasonably constant

output voltage swing for a wide range of input voltage levels. If the LA is DC coupled

to the TIA, DC offset compensation is required to prevent the LA from saturating at

one rail. The TIA and limiting amplifier make up what is generally called the analog

front-end of the optical receiver.

After the received signal has been boosted to detectable logic levels, a decision

circuit is used to remove the noise from the received signal. The decision circuit is

timed by a clock recovery circuit which extracts a clock signal from the received data.

10

CHAPTER 2. BACKGROUND THEORY 11

It is important that the clock driving the decision flip flop have a well-defined phase

relationship with the received data such that the signal is sampled at the optimum

point during the bit period [2]. Finally, the signal can be multiplexed down to multiple

lower bit rate signals using a de-multiplexer. A block diagram of this typical optical

receiver is shown in Figure 2.1.

t

v(t)

t

v(t)

t

i(t)

CompensationOffset

LA

DMUX

/NClock Recovery

QD

Flip Flop

Photodiode

TIA

Figure 2.1: Basic Optical Receiver Block Diagram

2.1.1 Receiver Sensitivity

The two most important performance measures of an optical receiver are the achiev-

able bit rate and the receiver sensitivity. The sensitivity of the receiver is measured as

the minimum received optical power required to achieve a specific bit error rate (BER)

(usually 10−9 or 10−10 ). The BER is defined as the ratio of incorrectly detected bits

to the total number of bits sent.

The sensitivity of the receiver is important because it determines the maximum

tolerable loss in the system which translates into a maximum link length. In long haul

applications, the longest link length is important because it can reduce the number

of optical amplifiers or signal regeneration units. In the context of PONs, a longer

available link length can increase the number of times the optical signal is split, which

can increase the number of subscribers or increase the range of individual ONUs.


The sensitivity of a receiver can be estimated from the input signal levels and

noise sources. Since the sensitivity is defined as a received optical power needed to

achieve a specified BER, we will start by estimating the BER of the system for a given

power level. The BER can be calculated using the following equation if we assume

there is no pattern dependence and that a 1 and a 0 are equally likely [3].

BER =1

2Prob(x = 1|0) + Prob(x = 0|1) (2.1)

where x is the detected bit. The BER is equal to the probability of detecting a 1

when a 0 is sent plus the probability of detecting a 0 when a 1 is sent. The factor of

one half is due to the fact that the probability of a 1 or a 0 being sent are the same.

These probabilities can be calculated if we know the probability density functions

for the received signal for both a 1 and a 0 being sent. If we assume a Gaussian

distribution for the received signal levels for a 1 and a 0, we get the following plot

shown in Figure 2.2.

−1 −0.5 0 0.5 1 1.5 20

0.5

1

1.5

2

2.5

Signal Level

Pro

babil

ity

Den

sity

Funct

ion

Sd1Sd0

σ1σ0

Decision Level

f0(x)

f1(x)

Figure 2.2: Probability Density Function


where Sd1 and Sd0 are the average received signal levels for a 1 and a 0,and σ1 and

σ0 are the variance in the received signal for a 1 and a 0. The Gaussian distribution

is given below in equation 2.2.

f1(x) =1√

2πσ1

exp

[

−(x − Sd1)2

2σ21

]

(2.2)

The first term in equation 2.1 is the area under the curve corresponding to a 0

being sent that is above the decision threshold. The second term is the area under

the curve corresponding to a 1 being sent that is below the decision threshold. This

is shown below in equation 2.3.

BER =1

2

1√2πσ1

∫ ∞

D

exp

[

−(x − Sd1)2

2σ21

]

dx +1√

2πσ0

∫ D

−∞

exp

[

−(x − Sd0)2

2σ20

]

dx

(2.3)

This equation can be simplified by replacing the integrals with the complementary

error function which is given below.

erfc(x) =2√π

∫ ∞

x

e−u2

du (2.4)

This substitution gives the following expression for the BER of the system shown

in equation 2.5.

BER =1

4

erfc

D − Sd0√2σ0

+ erfc

Sd1 − D√2σ1

(2.5)


We can simplify the analysis further by setting the detection level such that the

probability of incorrectly detecting a 1 and a 0 are equal as shown below.

D − Sd0√2σ0

=Sd1 − D√

2σ1

(2.6)

This results in the detection threshold shown in equation 2.7.

D =σ0Sd1 + σ1Sd0

σ0 + σ1

(2.7)

The BER expression in equation 2.5 can now be simplified to the following ex-

pression shown below.

BER =1

2erfc

Sd1 − Sd0√2(σ1 + σ0)

(2.8)

The BER is calculated for the signal at the input of the decision circuit in Fig-

ure 2.1. At this point the input signal has been amplified and noise has been added to

the signal by the amplifiers. If the receiver noise is referred to the input, the BER can

be calculated at the input of the receiver. This is generally what is done in practice

because the gain of the amplifiers does not need to be considered.

We can now define values for the signal levels and noise powers to estimate the

BER for the system. We will assume that a certain optical power level P1 is received

for a 1 and an optical power P0 is received for a 0. Ideally, there would be zero

optical power received for a 0, but practically this is not the case. The GPON

standard summarized in Table 1.2 specifies a minimum extinction ratio of 10 dB. The

extinction ratio re is defined as the ratio of the optical power received for a 1 to the


optical power received for a 0 as shown in equation 2.9.

re =P1

P0(2.9)

We will also assume that the probability of receiving a 1 and a 0 are equally likely,

therefore the average received optical power Pavg is the average of the optical powers

P1 and P0.

Pavg =P1 + P0

2(2.10)

The optical powers P1 and P0 can be written in terms of the average optical power

as shown below.

P1 =Pavgre

1 + re

(2.11)

P0 =Pavg

1 + re

(2.12)

The input current into the TIA for a 1 or a 0 is the received optical power multi-

plied by the responsivity R of the photodiode as shown in equation 2.13.

Sd1 =2RPavgre

1 + re

(2.13)

Sd0 =2RPavg

1 + re

(2.14)

The responsivity of the photodiode is a measure of the current produced per unit

optical power incident on the photodiode [3].


The noise power during the transmission of a 1 or a 0 is a combination of the

signal dependent shot noise from the photodiode, dark current, and the input re-

ferred noise current from the receiver. The signal dependent noise in the photodiode

results from the randomness associated with the rate of arrival of the photons at the

detector. The dark current is the portion of the current from the photodiode that

is not directly related to the incident signal and is present with no light incident on

the photodiode [3]. In this analysis the dark current will be neglected because it is

generally small compared to the circuit noise.

Expressions for the noise power of the received signal for a 1 and a 0 are shown

below.

σ21 =

4qRPavgre

1 + re

BI1 + |in,in|2 (2.15)

σ20 =

4qRPavg

1 + re

BI1 + |in,in|2 (2.16)

The first term in equations 2.15 and 2.16 is the signal dependent shot noise. This

value is derived in more detail in [3] where B is the noise bandwidth of the receiver,

q is the charge of an electron, and I1 is a term that is dependent on the received

pulse shape. The value of I1 is derived for several common pulse shapes in [3] and

is generally in the range of 0.5 ≤ I1 ≤ 2. For this analysis we will choose a value of

I1 = 1.

The second term in equations 2.15 and 2.16 is the mean squared input referred

noise current of the receiver. The input referred noise current is the noise current

that when put through the receiver, generates the appropriate noise voltage at the

input of the decision circuit.

Figure 2.3 shows plots of the BER vs. the average received input power for

various values of the circuit noise. Typical values are chosen for the properties of the


photodiode and receiver and are listed below.

R = 0.9 A/W

B = 2 GHz

I1 = 1

re = 10 dB

−28 −26 −24 −22 −20 −18 −16−20

−15

−10

−5

0

Pavg(dBm)

log

10(B

ER

)

√|in,in|2 = 0.5 µA rms







We can see from Figure 2.3 that in order to meet the GPON specification listed

in Table 1.2, the input referred noise current of the receiver needs to be less than

0.9 µA rms.

The receiver noise is largely determined by the noise properties of the TIA, since

the noise contribution of subsequent stages to the input referred noise current are

divided by the transimpedance gain of the TIA. For a high sensitivity receiver it is

important to have a low noise transimpedance amplifier with a large transimpedance

gain.


2.1.2 Integrated Transceiver

In the proposed integrated transceiver, crosstalk from other system components will

act as an additional source of noise and will degrade the receiver sensitivity. One

particular concern is the effect of the transmitter, especially the high power laser

driver on the same substrate as the sensitive TIA. This is shown below in Figure 2.4

TIA

AGC

LA

Re-timer

TIA

LD

Cross Talk

MMICTransmitter

Receiver

Offset Compensation

Clock and DataRecovery

Current ControlBias and Modulation

Figure 2.4: MIC Block Diagram for an Integrated Transceiver

The large signals from the laser driver may couple into the TIA and greatly degrade

the receiver sensitivity. This adds another requirement to the receiver circuitry. The

receiver should add as little noise to the signal and should also have strong noise

immunity. Two general methods can be used to achieve noise immunity. The electrical

isolation can be increased by using isolation trenches and placing different components

into separate well structures to reduce the amount of conducted noise that is coupled

into the TIA. Also, circuit topologies such as a differential structure can be used to

reject the noise that does reach the TIA and prevent it from being added to the signal.


2.2 Transimpedance Amplifiers

The primary function of a TIA is to convert the small current produced by the

photodiode into a voltage while adding as little noise to the output signal as possible.

The circuit is therefore characterized by several properties, including transimpedance

gain, group delay, and input referred noise current as shown in Figure 2.5.

TIAPhotodiode

f

∠ZT (f)

f

|ZT (f)|

f

√

d|in,in|2

df

f

τg(f)

VoutIin

Figure 2.5: Transimpedance Amplifier

The transimpedance gain of the TIA is the ratio of the output voltage to the input

current.

|ZT (f)| =

∣

∣

∣

∣

Vout

Iin

∣

∣

∣

∣

(2.17)

The group delay is defined as the negative of the derivative of the phase of the

transimpedance with respect to frequency.

τg(f) = − 1

2π

[

d(∠ZT (f))

df

]

(2.18)

A flat group delay means the amplifier has a linear phase response. A flat group

delay is important because variations in the group delay with frequency can cause

distortions in the output signal. The distortion is significant if the variation in the

group delay across the bandwidth of the amplifier is significant when compared to


the signal bit period.

Finally, the noise contribution of the TIA is characterized by the input referred

noise current. The input referred noise current is the noise current that could be

applied to the equivalent noiseless TIA that would produce an output noise voltage

equal to that of the original noisy circuit [2]. This is shown below in Figure 2.6.

TIA

IinVout

TIA

|vn,out|2

IinVout |in,in|2

(Noiseless) (Noiseless)

Figure 2.6: Input Referred Noise Current

The input referred noise current is related to the output noise voltage by the

following equation.

|in,in|2 =|vn,out|2|ZT |2

(2.19)

The input referred noise current is used to provide a fair comparison between

devices since it does not depend on the transimpedance gain of the device.

The most basic TIA is shown in Figure 2.7 a) where the TIA is simply a resistor

RL. The photodiode is replaced with an equivalent model in Figure 2.7 b). The

photodiode model consists of an ideal current source and a photodiode capacitance.

The photodiode current Iin passes through the resistor and is converted to a voltage

Vout. The transimpedance gain is equal to the value of the load resistance RL since

all of the photodiode current passes through RL [2].

One problem with this simple circuit is that it has a very fixed trade-off between

gain, bandwidth and noise. The transimpedance gain as mentioned is equal to the

value of RL. However, the bandwidth is determined by the RC time constant formed

between RL and the photodiode capacitance CPD. The 3 dB bandwidth of the circuit


RL

Vout

CPD RL

Vout

Iin

Photodiode

(a) (b)

Figure 2.7: a) Photodiode and Simple Transimpedance Amplifier b) Simple Tran-simpedance Amplifier with Photodiode Model

is given as follows [2].

f3dB =1

2πRLCPD

(2.20)

This shows that for a given photodiode capacitance the resistor RL determines

the bandwidth. To achieve higher bit rates, the resistor RL needs to be reduced to

increase the bandwidth, which in turn reduces the transimpedance gain.

Unfortunately it can be shown that the input referred noise current is also depen-

dent on the value of RL. Figure 2.8 shows the noise contribution from the resistor RL.

The noise from the resistor is directly referred to the input such that the mean squared

input referred noise current spectral density is constant and given in equation 2.21

Vout

CPD RLIin iRL


d|in,in|2df

=d|iRL

|2df

=4kT

RL

(2.21)


where k is the Boltzmann constant and T is the temperature in Kelvin. In order

to determine the total mean squared input referred noise current, the mean squared

noise current spectral density needs to be multiplied by the magnitude squared of

the normalized transimpedance gain and integrated from 0 to infinity. This is shown

below in equation 2.22 [3].

|in,in|2 =1

|ZTpk|2

∞∫

0

d|in,in|2df

|ZT (f)|2df (2.22)

In this case, the mean squared input referred noise current spectral density is

constant and can be removed from the integral.

|in,in|2 =d|in,in|2

df

1

|ZTpk|2

∞∫

0

|ZT (f)|2df (2.23)

The remaining portion of the equation is called the noise bandwidth of the system

and is shown in equation 2.24.

B =1

|ZTpk|2

∞∫

0

|ZT (f)|2df (2.24)

The transimpedance gain ZT (f) for this system is given below in equation 2.25.

ZT (f) =Vout

Iin

=RL

1 + j2πfCPDRL

(2.25)

In this case, the maximum transimpedance, |ZTpk|, occurs at DC and is equal to

RL. The integration results in the following noise bandwidth.


B =1

4RLCPD

(2.26)

We can now determine the total mean squared input referred noise current.

|in,in|2 =kT

R2LCPD

(2.27)

We can see from this equation that the input referred noise current is increased

as the value of RL is decreased.

Therefore, as the bit rate is increased, the value of RL is reduced in order to

increase the bandwidth of the circuit. As RL is reduced, the input referred noise

current is increased, and the transimpedance gain is reduced. The noise, gain, and

bandwidth equations for this TIA are directly coupled. More complex structures need

to be examined that reduce this trade-off.

2.3 Common TIA topologies

Generally there are two types of TIA topologies, open loop TIAs and feedback

TIAs [2]. The goal when designing a TIA, is to provide a low input impedance

in order to meet the bandwidth requirements, while also providing low noise and high

gain. The characteristics and performance of these two topologies will be discussed

below.

2.3.1 Open Loop TIAs

Open loop TIAs generally use common gate or common base topologies since these

devices are capable of providing a low input impedance. A typical common gate


TIA is shown in Figure 2.9. The transistor M1 is the common gate transistor with a

resistive load RD, while transistor M2 provides a bias current.

RD

M1

Vout

Vbias

M2CPD

Vbias

Iin

Figure 2.9: Common Gate TIA

Since all of the photodiode current passes through the load resistance RD, the

transimpedance gain is equal to RD. The input resistance of this amplifier is given

to a good approximation by [2]

Rin ≈ rds 1 + RD

1 + (gm 1 + gmb 1)rds 1

(2.28)

where rds 1 is the drain to source resistance, gm 1 is the device transconductance, and

gmb 1 is the back-gate transconductance due to the body effect. This equation assumes

that drain to source resistance rds 2 of transistor M2 is large.

For long channel devices operating in the saturation region, the value of rds is large

and this equation reduces to the following relationship, where the input resistance

is only dependent on the properties of the device, and is independent of the load

resistance RD.

Rin ≈ 1

gm + gmb

(2.29)


This is an important result because the bandwidth is independent of the tran-

simpedance gain set by RD. In reality, if RD is increased too much, the output

pole formed with the parasitic output capacitance of the common gate transistor will

determine the bandwidth.

The unfortunate downside of this TIA is that the noise current produced by the

load resistance RD and the bias transistor M2 are directly referred to the input with a

unity factor. The noise contributions from these two sources also trade-off with each

other. The load resistor can be increased in order to reduce its noise contribution.

In order to maintain the proper biasing conditions, the bias current would need to

be reduced which would increase the noise contribution of M2. If the bias current is

maintained, the supply voltage would need to be increased. In order to reduce the

noise contribution from the bias transistor, the bias current can be increased. Again,

to maintain the bias conditions, the load resistor would need to be decreased, which

would increase the noise contribution from the load resistor. If the load resistor is

kept the same, the supply voltage would again need to be increased to maintain the

transistor in saturation. Improving the noise performance of this device comes at the

cost of increased power consumption. As the supply voltage is increased, the power

consumption increases quickly for a small improvement in the noise performance.

2.3.2 Feedback TIAs

A more popular TIA topology is the shunt-shunt feedback structure shown in Fig-

ure 2.10. An ideal inverting voltage amplifier is shown with a feedback resistance

RFB. The transimpedance gain of this circuit given in the following equation [2]

ZT =A

A + 1

RFB

1 + jω RFBCPD

A+1

(2.30)


where A is the open loop voltage gain of the amplifier.

CPDIin

Vout

RFB

-A

Figure 2.10: Feedback TIA

We can see that if the voltage gain, A, of the amplifier is sufficiently high, the

transimpedance is approximately equal to RFB in the amplifier’s passband. Assuming

that the dominant pole is at the input, the bandwidth of this circuit will be given by

the following expression.

f3dB ≈ A + 1

2πRFBCPD

(2.31)

The bandwidth of the TIA is greater than that of a simple resistive network by

a factor of A+1. The noise of the feedback resistor RFB is directly referred to the

input with a unity factor, while the noise from the voltage amplifier is divided by a

factor of RFB. This is similar to the load resistor in the common gate amplifier, but

in this case RFB doesn’t carry bias current and therefore can be increased without

increasing the supply voltage.

2.3.3 Bandwidth Considerations

The previous section has covered two typical TIA topologies and discussed their

major performance parameters. We have stated that it is important to minimize the

input referred noise current and maximize the transimpedance gain to improve the

sensitivity of the device. We haven’t, however, discussed in detail the bandwidth


requirements of the TIA.

For this section we will assume that the signal is sent in a binary non-return to

zero format (NRZ) format, which is the most common. In this format the data signal

is either high or low for the entire bit period. If consecutive bits are the same, the

data signal remains at the high or low state for multiple bit periods.

At the point of detection, superimposed on the NRZ data signal will be broadband

noise that will be a combination of noise added during transmission, signal dependent

shot noise generated by the PIN photodiode, and thermal noise added by the receiver

electronics. It is clear that by reducing the bandwidth of the TIA, this broadband

noise can be filtered and reduced. However, limiting the amplifier bandwidth will

produce inter-symbol-interference (ISI), which can also generate errors in the receiver.

There is therefore a trade-off between the amount of ISI produced and the amount of

noise passed by the TIA.

It is not easy to determine this optimum bandwidth analytically since the TIA

generally has a complex transfer function with multiple poles. Figure 2.11 shows

eye diagrams of the response of a second order maximally flat butterworth filter to

random data with varying bandwidth relative to the bit rate Rb. It can be seen that

as the bandwidth is reduced from a value equal to the bit rate down to a value equal

to 0.3 times the bit rate, a significant amount of ISI is introduced. From this Figure,

we can see that the bandwidth can be reduced to approximately 0.7 times the bit rate

with minimal added ISI. There may be tighter restrictions on the optimal sampling

time when compared to the higher bandwidth signal, but there is minimal vertical

and horizontal eye closure.

Another consideration is the low frequency cut-off frequency. Often, AC coupling

is desired in circuit design in order to bias the transistors at their optimal bias point for

either optimal gain or optimal noise performance. The biasing network will introduce

a low frequency cut-off frequency. Figure 2.10 shows the effects of the low frequency


0 0.5 1 1.5 2 2.5 3−6

−4

−2

0

2

4

6

Time Normalized to Bit Period

Outp

ut

Volt

age

(mV

)

0 0.5 1 1.5 2 2.5 3−6

−4

−2

0

2

4

6

Time Normalized to Bit PeriodO

utp

ut

Volt

age

(mV

)

(a) (b)

0 0.5 1 1.5 2 2.5 3−6

−4

−2

0

2

4

6


Outp

ut

Volt

age

(mV

)

0 0.5 1 1.5 2 2.5 3−6

−4

−2

0

2

4

6


Outp

ut

Volt

age

(mV

)

(c) (d)

Figure 2.11: Response of a Second Order Filter to Random Data with a BandwidthEqual to a) Rb b) 0.7 Rb c) 0.5 Rb d) 0.3 Rb


cut-off on a 2.5 Gbps random data signal. The data signal was produced by passing

NRZ data through a first order high pass filter with a low frequency 3 dB cut-off of

20 MHz. This cut-off frequency is not practical but is used to illustrate the effects of

the low frequency cut-off frequency. The data signal has a sequence of consecutive high

bits in the middle of the sequence. It can be seen that the DC level during the series

of consecutive bits begins to droop. A long series of consecutive bits can significantly

alter the DC level of the data, which alters the optimum threshold voltage. The

GPON standard calls for the receiver to be able to tolerate 72 consecutive identical

bits. A poor low frequency cut-off has the effect of vertically closing the eye, and can

reduce the sensitivity of the system

0 2 4 6 8 10−8

−6

−4

−2

0

2

4

6

8

Time (ns)

Outp

ut

Volt

age

(mV

)

Figure 2.12: Response of a Filter with a Low Frequency Cut-off of 20 MHz to RandomData

In order to achieve a lower low frequency cut-off, the size of the bias network

components need to be increased. If these components are implemented on-chip,

they can be very large and take up a considerable amount of valuable chip space.

For this reason, these components are generally added externally. In this project, the

goal is to produce a fully integrated transceiver on a single MIC. Since this is the

case, adding external components is not desired. Instead, the TIA design will be DC

coupled to avoid external biasing components. There will be a slight performance


trade-off as the active components will not be biased at their optimum bias points.

Chapter 3

Literature Review

3.1 Transimpedance Amplifier Topologies

3.1.1 Regulated Cascode TIA

The basic principle of open loop TIAs was described in section 2.3.1. A common gate

structure is normally used because it has a low input impedance. By presenting the

photodiode with a low input impedance, the amplifier is able to isolate the photodiode

capacitance from determining the bandwidth of the system.

The ability of the common gate structure to isolate the large photodiode ca-

pacitance is limited by the gm of the input transistor. In order to lower the input

impedance, the size of the transistor can be increased, which raises the bias current

and adds to the parasitic input capacitance. A regulated cascode (RGC) structure

has been used in [4, 5, 6] to solve this problem.

The regulated cascode structure is shown below in Figure 3.1. The RGC structure

consists of a common gate transistor M1 with a resistive load R1. The resistor RS

sets the bias current through the common gate transistor. The transistor MB and

resistor RB create a local feedback loop that reduces input impedance of the amplifier

by approximately the value of its voltage gain. The regulated cascode structure is

31

CHAPTER 3. LITERATURE REVIEW 32

generally used as a current buffer and is followed by a feedback transimpedance

amplifier structure. By lowering the input impedance of the amplifier, the RGC

structure decouples the photodiode capacitance from determining the bandwidth of

the amplifier.

−A

R1 RB

MB

M1

RS

Vout

RFB

Figure 3.1: Regulated Cascode TIA

The input impedance of the RGC structure is given as follows. This approximate

result neglects the body effect.

Rin ≈ 1

gm1(1 + gmBRB)(3.1)

We found in section 2.3.1 that the input resistance of a common gate amplifier

was approximately equal to 1/gm (again neglecting the body effect). We can see from

the result in equation 3.1 that the RGC structure has an input resistance that is a

factor of 1/(1+gmBRB) lower than the common gate structure.

This RGC topology was used in [4] to create a 1.25 Gbps TIA. The RGC struc-

ture was used as a current buffer and was followed by a voltage gain stage. The TIA

achieved a transimpedance of 58 dBΩ, with a bandwidth of 950 MHz with a photo-

diode capacitance of 500 fF. The TIA had an average noise current spectral density

of 6.3 pA/√

Hz.

This same topology was used in [6] to create a 2.5 Gbps TIA. The TIA was able


to achieve a bandwidth of 2.2 GHz, and a transimpedance gain of 55.3 dBΩ, with a

photodiode capacitance of 500 fF.

The RGC topology was also used in [5] to create a 1 Gbps differential TIA. This

TIA has a 80 dBΩ differential transimpedance gain with a bandwidth of 670 MHz.

The RGC structure was also used in the TIAs used in the optical receiver analog

front-ends in [7] and [8]. In [8], the RGC structure was used in a single ended TIA

with a transimpedance gain of 54 dBΩ, and a bandwidth of 2.5 GHz, to create a

2.5 Gbps optical receiver analog front-end. In [7], a differential structure was used to

create a 10 Gbps analog front-end with a sensitivity of -12 dBm at a BER of 10−12.

Finally, the RGC structure was used in a tunable transimpedance amplifier in [9].

The RGC structure is used as a current buffer before a voltage gain stage that has

an adjustable gain and bandwidth.

3.1.2 DC Coupled Common Gate TIA

Figure 3.2 shows another type of TIA that uses a modified common gate topology.

This topology was first used in [10].

M1M2

RT

RB

Vout

IDC

Figure 3.2: DC Coupled Common Gate TIA

The importance of DC coupling in avoiding baseline wander has been discussed


in section 2.3.3. In a DC coupled common gate TIA, a significant change in the DC

input current can alter the bias point of the common gate transistor and affect the

performance of the amplifier. Variations in the DC input current will also lead to

changes in the DC output voltage which may also affect the next stage of the system.

The topology in [10] avoids this problem by using a current mirror to ensure

the bias current in the common gate structure is constant. The resistor RB sinks

any additional input current. This topology is not used as a current buffer and the

resistor RT sets the transimpedance gain as long as RB is sufficiently large.

The size of the transistor M2 is minimized such that the majority of the signal

current flows through the common gate transistor M1. Since the transistor is mini-

mally sized, it adds minimal capacitance to the input and also contributes very little

noise.

A number of TIAs have been demonstrated using this topology. A TIA was

designed in [10] using a 0.25 µm CMOS process that achieved a transimpedance

bandwidth of 42.9 dBΩ, and a bandwidth of 8.4 GHz. The measured input referred

noise current is equal to 14.6 pA/√

Hz. A second TIA was designed using a 47 GHz

SiGe HBT process that achieved a transimpedance gain of 47.3 dBΩ, and a bandwidth

of 9.8 GHz. The measured input referred noise current for this TIA is equal to

12.0 pA/√

Hz. Two TIAs with similar performance are also reported in [11].

A 25 Gbps TIA has also been designed using this topology in [12]. This TIA was

designed in a 0.13 µm CMOS process and achieves a transimpedance gain of 42 dBΩ

and a 15 GHz bandwidth.

This topology has also been used in several high speed optical receiver analog

front-ends. A 10 Gbps optical receiver analog front end has been reported in [13].

This modified common gate structure was used in a differential configuration with

a shunt peaking inductor to further improve the bandwidth. The receiver was able

to achieve a sensitivity of -13.1 dBm with a BER of 10−12 at a bit rate of 10 Gbps.


A 17 Gbps optical receiver analog front-end has been reported in [13]. A receiver

sensitivity of -12.7 dBm achieved with a BER of 10−12 at a bit rate of 12.5 Gbps.

The bit rate of 12.5 Gbps was the limit of the BER test equipment used, but an open

eye was shown for a 17 Gbps signal.

3.1.3 Feedback TIAs

A number of different feedback topologies have been reported in the literature. Fig-

ure 3.3 shows the most common feedback structures. Figure 3.3 a) shows a shunt-

shunt feedback topology with a common source gain stage. The transistor is loaded

with a resistor for broadband amplification. A source follower is used to isolate the

load resistor from the feedback resistance. Figure 3.3 b) shows a similar topology,

but with a cascode gain stage instead of a common source gain stage. By placing

a common gate transistor between the common source transistor and the load, the

Miller effect is reduced and the input capacitance of the TIA is reduced. Finally

Figure 3.3 c) shows a feedback TIA that uses a CMOS inverter as the gain stage. By

using the pMOS transistor, this topology is capable of a high gain but suffers from

the large parasitics of the larger pMOS transistor as well as the Miller effect [14].

RD

RFB

M1

M2

Vout

RD

M2

RFB

Vout

M1

M2 Vout

M1

M2

RFB

(a) (b) (c)

Figure 3.3: Feedback TIA Topologies a) Common Source b) Cascode c) CMOS In-verter

A 2.5 Gbps optical receiver has been designed in [15]. The optical receiver uses


a TIA with a shunt-shunt feedback topology that uses a resistive loaded common

source gain stage. The feedback resistance is created using transistors operating in

the linear mode. This allows for the gain to be adjusted. This TIA is able to achieve

a bandwidth of 5.9 GHz and a transimpedance gain of 59 dBΩ. The optical receiver

is able to operate with a minimum input current amplitude of 30 µAp-p.

A 5 Gbps TIA has been reported in [16]. This TIA uses a shunt-shunt feedback

topology and uses a cascode gain stage to reduce the Miller effect. A source follower

buffer is used on the output to isolate the resistor in the gain stage from the feedback

resistance. This TIA was able to achieve a bandwidth of 2.6 GHz with a photodiode

capacitance of 200 fF. The transimpedance gain was 58.7 dBΩ and the average input

referred noise current density was 13 pA/√

Hz

A 10 Gbps TIA was designed using the CMOS inverter topology in [17]. Multiple

CMOS inverter stages were cascaded using series inductive peaking. This design will

be discussed in greater detail in section 3.2.2.

3.2 Bandwidth Extension

3.2.1 Shunt Peaking

Shunt inductive peaking has long been used as a technique for extending the band-

width of a circuit. Figure 3.4 a) shows a common source amplifier with shunt inductive

peaking. If the dominant pole of the amplifier is at the output, the inductor adds a

pole and a zero to the frequency response, as shown in equation 3.2.

Vout

Vin

=gmRD

1 + jωRDCL − ω2LCL

(3.2)

This technique was first used to extend the bandwidth of a CMOS TIA using


RD

L

M1

CL

RD

M1

CL

L

RS

Cind

(a) (b)

Figure 3.4: Shunt Inductive Peaking a) Ideal b) Inductor Model

on-chip inductors in [18]. It was shown in this paper that the bandwidth of this type

of circuit could be extended as much as 85%. This maximum bandwidth comes at the

cost of peaking in the frequency response and the group delay. For a maximally flat

frequecy response it was shown that a 72% increase in bandwidth could be achieved.

If a maximally flat group delay is required, a bandwidth extension of 60% can be

achieved. The theory of shunt inductive peaking will be discussed further in chapter 5.

These bandwidth improvements are for the ideal case shown in figure 3.4 a), a

more realistic model is shown in figure 3.4 b), which includes the parasitic components

of an on-chip inductor. The advantage of shunt inductive peaking is that the Q value

of the on-chip inductor is not important since the series resistance of the inductor can

be incorporated by adjusting the value of the resistor RD. It is important to minimize

the size of the inductor to reduce the parasitic capacitance. Therefore, the minimum

trace width should be used that meets the current density rules for the metal [18].

A number of TIAs have been designed using shunt inductive peaking [7, 9, 19, 20].

Shunt inductive peaking is also frequently used in output buffers to drive a large off-

chip load capacitance [5, 12].


3.2.2 Series Inductive Peaking

Another bandwidth extension technique is series inductive peaking. By placing an

inductor in series with a capacitive load, a resonant circuit is created which will pull

more current into the load capacitance, improving the speed. As with shunt inductive

peaking, the increase in bandwidth results in a peak in the frequency response. Again,

the inductor can be selected to produce a maximally flat frequency response or group

delay with a slightly reduced bandwidth. A more detailed analysis of series inductive

peaking will be done in chapter 5.

Series inductive peaking has been used to design a 10 Gbps TIA in 0.18 µm CMOS

technology in [17]. The TIA uses a multi-stage amplifier with series inductive peaking

between stages as shown in Figure 3.5. The series inductors increase the bandwidth

of each individual stage. An added benefit is that the bandwidth is not degraded

when stages are cascaded as would be the case if series inductive peaking was not

used.

. . .

. . .Vout

Figure 3.5: TIA Using Series Inductive Peaking

Each gain stage consists of a CMOS inverter with resistive feedback. Normally

this topology is not capable of high bandwidths due to the large parasitic capacitance

added by the pMOS transistor. However, the series inductors absorb the parasitic

capacitance between the stages and increase the bandwidth. The series inductors

combine with the parasitic capacitances to create a 3rd order LC ladder filter struc-

ture. It was found that a poor match at the input and the output could produce


poor performance. M-derived half circuits were used as matching networks at the

input and output. A simulation was done to show that the five stage amplifier was

able to produce a bandwidth three times higher than the amplifier with no inductive

peaking.

The TIA reported in [17] achieved a transimpedance gain of 61 dBΩ with a band-

width of 7.2 GHz and an average input referred noise current density of 8.2 pA/√

Hz.

3.2.3 Shunt and Series Peaking

A combination of shunt and series peaking can be used to further extend the band-

width of a circuit. This principle has been demonstrated in [21]. Figure 3.6 shows

a common source amplifier with shunt and series inductive peaking. The inductors

create multiple resonant structures that improve the bandwidth of the circuit. Un-

like shunt or series peaking alone, there is still a certain amount of peaking in the

frequency response and group delay using the optimal component values. The peak-

ing, however, is reduced by the finite Q of on-chip spiral inductors. Shunt and series

peaking is analyzed in more detail in chapter 5.

RD

L1

L2

M1

CL

Figure 3.6: Shunt and Series Inductive Peaking

This article demonstrates the advantage of shunt and series peaking in broadband


circuits. Often, the gain of a broadband circuit is compromised to obtain a large

bandwidth. This has led to the use of distributed amplifiers (DAs) and cascaded

amplifiers to get past this trade-off between gain and bandwidth.

Distributed amplifiers absorb the parasitic capacitances of the gain stages in either

artificial or high impedance transmission lines at the input and output of the amplifier.

The total amplifier gain is roughly the sum of the gains from each stage. There are

several drawbacks to distributed amplifiers. Since all of the bias current for the gain

stages flows through the same loads, there is a severe trade-off between gain and

voltage headroom. Also, the finite output resistance of short channel devices can add

significant loss to the output transmission line. The loss in the transmission lines

limits the length of the line, the number of stages, and ultimately the maximum gain

that can be achieved [21].

In a cascaded amplifier, the gain of each stage is multiplied. However, the total

bandwidth is reduced as the stages are cascaded, and the bandwidth of each stage

needs to be significantly higher than the system bandwidth. Shunt and series induc-

tive peaking can be used to extend the bandwidth of each stage and make broadband

cascaded amplifiers possible.

An amplifier was designed in [21] that cascaded 5 differential pair gain stages

using shunt and series inductive peaking. The bandwidth of the amplifier with shunt

and series inductive peaking was approximately 3.5 times larger than the bandwidth

of the amplifier without inductive peaking. The final amplifier was able to achieve a

differential gain of 15 dB and a bandwidth of 22 GHz using 0.18 µm CMOS technology.

Chapter 4

2.5 Gbps Transimpedance

Amplifier Design

4.1 Introduction

This chapter presents the design of a 2.5 Gbps transimpedance amplifier designed to

meet the GPON specifications given in Table 1.2. Based on the analysis shown in

section 2.3 and chapter 3, a shunt-shunt feedback topology was chosen for this TIA

design. This is because the TIA is being designed for an integrated system with a

specific photodiode. This means the TIA doesn’t need to be able to function with a

range of photodiode capacitances and an open loop TIA is not required. By using a

feedback topology, a higher sensitivity will be achieved.

4.2 The Cascode Structure

The first step in the design was to choose an appropriate gain stage to replace the ideal

voltage gain stage shown in Figure 2.10. The important performance specifications for

the amplifier are a high gain, large bandwidth, low noise, and low input capacitance.

Two topologies were considered for this design, a common source configuration

41

CHAPTER 4. 2.5 GBPS TRANSIMPEDANCE AMPLIFIER DESIGN 42

and a cascode configuration. These two configurations are shown in Figure 4.1. The

common source transistor has a resistive load for broadband amplification. The cas-

code configuration also has a common source transistor at the input. The common

source transistor is cascaded with a common gate transistor and a resistive load.

M1

RD

Vin

Vout

RD

M2

M1Vin

Vout

(a) (b)

Figure 4.1: a) Common Source Amplifier b) Cascode Amplifier

4.2.1 Miller Effect

One of the issues to consider when comparing the two topologies is the effect of

the Miller capacitance. Figure 4.2 shows a small signal equivalent model of the

common source configuration. The gate to drain capacitance CGD, known as the

Miller capacitance, is connected between the input and output. The gate to drain

capacitance is formed as a result of the overlap between the gate and the drain caused

by lateral diffusion of the drain under the gate. For short gate length devices, this

overlap capacitance is significant compared to other parasitic capacitances and is

important to consider.

Miller’s theorem allows this capacitance to be replaced with shunt capacitances

at the input and output [22]. Miller’s theorem can be derived by looking at the

general example in Figure 4.3. A series admittance is connected between two points

with a known voltage gain of K. In order to replace this series admittance with shunt


CGSVgs

G RG CGD

CDS rds

S

D

gmVgs RL

Figure 4.2: Common Source Equivalent Circuit

admittances at the input and the output, the currents I1 and I2 must remain constant

during the transformation.

V1 V2 = KV1

YI1 I2

V1 V2 = KV1Y1 Y2

I1 I2

Figure 4.3: Miller Theorem

In the first diagram with the series admittance, we can write the following for the

currents I1 and I2.

I1 = (V1 − V1K)Y = V1(1 − K)Y (4.1)

I2 = (V1K − V1)Y = V1(K − 1)Y (4.2)

We can now equate these currents to the currents in the second diagram.

I1 = V1Y1 = V1(1 − K)Y (4.3)

I2 = KV1Y2 = V1(K − 1)Y (4.4)


The values of the shunt admittances can now be determined and are shown below.

Y1 = Y (1 − K) (4.5)

Y2 = Y (1 − 1/K) (4.6)

This is an interesting result because as the gain is increased, the input capacitance

of the amplifier is increased. This reduces the magnitude of the input pole and reduces

the bandwidth of the TIA. In the next section we will look at how this effect can be

reduced.

4.2.2 Cascode vs. Common Source

The low frequency voltage gain of the common source transistor can be calculated

using the small signal model in Figure 4.2. The voltage gain is given in the following

formula

Vout

Vin

= −gm(rds//RL) (4.7)

where gm is the transconductance of the transistor, rds is the drain to source resistance

of the transistor in saturation, and RL is the load resistance.

If we assume that rds RL we can approximate the voltage gain as follows.

Vout

Vin

= −gmRL (4.8)

The voltage gain across the common source transistor is directly proportional to

the load resistance RL. In the case of the common source gain stage, RL is equal


to the load resistance RD. In the cascode configuration, the load RL is equal to the

input resistance of the common gate transistor. The input resistance of a common

gate transistor was shown in section 2.3.1 to be as follows.

Rin ≈ 1

gm + gmb

(4.9)

In a resistively loaded common source configuration, the load resistor RD sets

the voltage gain across the common source transistor. The cascode configuration

minimizes the Miller effect by placing a common gate transistor in series with the

common source transistor. The common gate transistor presents the common source

transistor with a low input impedance which reduces the voltage gain across the

common source transistor and reduces the Miller capacitance. The common gate

transistor however, acts as a current buffer and passes the current from the common

source transistor through to the load resistor resulting in the same gain as the resistive

loaded common source amplifier. This is an ideal result as the gain will be lowered

slightly if the value of the drain to source resistance rds is low.

The cascode and common source amplifiers have same gain, but the cascode will

have a lower input capacitance. The downside of the cascode configuration is that

it requires a higher supply voltage to maintain the same gain as the common source

topology, and there will be a small noise contribution from the common gate transis-

tor.

4.3 2.5 Gbps TIA Design

For the reasons described above, a cascode gain stage was chosen for the TIA. The

schematic for the input transimpedance stage of the amplifier is shown in Figure 4.4.

A source follower was added to isolate the load resistance RD from the feedback


resistor RFB as well as the capacitance of the next stage.

RDRD

I2 I1 I2

IN+ IN-

OUT-OUT+

M3 M3

Vbias Vbias

M1 M1

M2 M2

RFB RFB

Figure 4.4: Differential Cascode TIA

The TIA has been designed to be pseudo differential. The TIA is not truly dif-

ferential because the photodiode is single ended and is only connected to one side of

the differential structure. The purpose of using a pseudo differential structure is to

improve the common mode rejection of the device. The intended application of this

TIA is to be integrated on the same substrate as other transceiver components. By

making the structure differential the input referred noise current is increased by a

factor of√

2. However, since there is significant cross-talk expected, the increase in

common mode rejection will outweigh this penalty.

4.3.1 Variable Gain

In order to avoid saturating the amplifier when a high powered signal is applied, the

TIA was designed to have a variable gain. The gain can be varied by adjusting the

value of the feedback resistance by placing a transistor operating in the linear mode in

parallel with the feedback resistor RFB as shown in Figure 4.5. As the gate voltage of


the transistor is increased, the transistor is turned on and begins to conduct, reducing

the value of the total feedback resistance. The tuning range is determined by the on

resistance of the transistor. The larger the transistor is, the smaller the on resistance

will be. This is a problem for this circuit because the parasitic diffusion capacitance

of the transistor will increase the input capacitance of the TIA. In order to avoid this

problem, the transistor is isolated from the input with a resistor.

I2

OUT-

M3

RFB 1 RFB 2

RDRD

I1

IN+ IN-

Vbias Vbias

M1 M1

M2 M2

RFB 1RFB 2

I2

M3

OUT+

AGC AGC

Figure 4.5: Cascode TIA with AGC

The feedback network consists of two series resistors, with one connected in parallel

with a transistor. When the transistor is turned on, the value of RFB 2 is shorted by

the transistor, reducing the feedback network to approximately RFB 1. The range of

the variable gain is set by the relative values of RFB 1 and RFB1 2, as well as the size

of the transistor.

4.3.2 Final Schematic

The final schematic for the 2.5 Gbps TIA is shown in Figure 4.6. A voltage gain stage

was added after the transimpedance stage. This stage uses a simple resistive loaded

differential pair. Also, for measurement purposes, an output buffer has been added to

the TIA. The output buffer is also a resistive loaded differential pair with an output

impedance that is matched to 50 Ω.


I1

M1 M1

M2 M2

IN-IN+

I3

M5

M4 M4

I2

M3

I2

M3

RD 2RD 2 RD 3RD 3

RD 1RD 1

M5

OUT+

OUT-

RFB 1

RFB 1 RFB 2

AGC

RFB 2

I4

MAGC

MAGC

Figure 4.6: 2.5 Gbps TIA Final Schematic

Table 4.1: 2.5 Gbps TIA Component Values

Transistor SizesComponent M1 M2 M3 M4 M5 MAGC

Value (2.5 µm Fingers) 17 17 40 30 35 20

Resistor ValuesComponent RD 1 RD 2 RD 3 RFB 1 RFB 2

Value 256 Ω 228 Ω 50 Ω 100 Ω 700 Ω

Current Source ValuesComponent I1 I2 I3 I4

Value 6.3 mA 3 mA 7.3 mA 11 mA


Table 4.1 documents the component values used including the transistor sizes,

the resistor values, and the bias currents for each stage. The current sources were

implemented using current mirrors. These devices were not shown in Figure 4.6 for

simplicity, but a sample circuit is shown in Figure 4.7.

M2M1

Iout

Rbias

Figure 4.7: Current Mirror

A photo of the final chip is shown in Figure 4.8 and the final layout is shown in

Figure 4.9. The total chip has an area of 730 µm by 610 µm, including the input and

output pads. It can be seen that even though the amplifier is only pseudo differential,

a set of dummy pads and a transmission line have been used for the unconnected

input to ensure the amplifier is symmetrical and to allow for differential S-parameter

characterization. It is important that the amplifier layout is symmetrical in order

to achieve a high common mode rejection ratio (CMRR). A dummy capacitance will

need to be added on the input to simulate the photodiode capacitance.

4.4 Simulation Results

The final 2.5 Gbps TIA was simulated with Agilent’s Advanced Design System (ADS)

using transistor models provided by the Taiwan Semiconductor Manufacturing Com-

pany (TSMC). In order to account for the effects of the transmission lines and pads,

Agilent’s Momentum simulator was used to do an electromagnetic (EM) simulation


610 µm

730 µm

Figure 4.8: 2.5 Gbps TIA Chip Photo

of the top metal layer. Ports were added at the pads and at the ends of the co-

planer waveguides. The active components were then connected to the ports and a

co-simulation was done.

Simulating the transimpedance amplifier without the effect of the photodiode is

not very useful. It is important to estimate the transimpedance gain with the effects

of the photodiode capacitance. Photodiode capacitances are generally between 100 fF

and 500 fF [2]. An ideal capacitance of 250 fF was added to the input of the TIA as

shown in Figure 4.10. A dummy capacitance was also added to the other TIA input

to maintain the symmetry of the differential circuit.

The results of this simulation are shown in Figure 4.11. Figure 4.11 a) shows

the transimpedance gain with different values of the AGC voltage. The TIA has

a maximum transimpedance gain of 64 dBΩ and a corresponding transimpedance

bandwidth of 1.8 GHz. This works out to approximately 0.72 times the bit rate of


Figure 4.9: 2.5 Gbps TIA Chip Plot


IPD

TIA

50Ω

50ΩCPD

Cdummy

Vout

Iin

Figure 4.10: Simulation Setup

2.5 Gbps which is near the optimum value discussed in section 2.3.3. The average

input referred noise current spectral density corresponding to the maximum gain is

approximately 9.0 pA/√

Hz.

109

1010

25

30

35

40

45

50

55

60

65

Frequency (Hz)

Tra

nsi

mp

edance

(dB

Ω)

AGC=0.0 VAGC=2.4 VAGC=2.5 VAGC=2.6 VAGC=3.0 V

109

1010

0

10

20

30

40

50

60

70

Frequency (Hz)

Input

Ref

erre

dN

ois

eC

urr

ent

Den

sity

(pA√Hz)

AGC=0.0 VAGC=2.4 VAGC=2.5 VAGC=2.6 VAGC=3.0 V

(a) (b)

Figure 4.11: Simulated Transimpedance Gain and Input Referred Noise Current -CPD = 250 fF a) Transimpedance Gain b) Input Referred Noise Current

The results show that the transimpedance gain can be lowered to 46 dBΩ when an

AGC voltage of 3.0 V is applied. Results are also shown for a number of intermediate

AGC voltages. It can be seen that as the gain is reduced, the bandwidth of the

amplifier is increased. This is because, as the AGC voltage is increased, the total

resistance of the feedback network is reduced. This raises the value of the input pole

created by the feedback resistance and the photodiode capacitance. We can see in


Figure 4.11 b) that as the AGC voltage is increased, the input referred noise current

is increased. This is because the transistor MAGC is now conducting and contributing

noise current that is directly referred to the input, and the bandwidth of the amplifier

is increased which allows more noise into the system. Ideally, the input referred noise

current would be held constant, but this is not a major problem for the system, as in

practice the gain is only lowered in the presence of a high powered input signal. In

this situation the signal power is high enough to achieve a low BER.

We can estimate the sensitivity of the receiver based on these results using the

same procedure shown in section 2.1.1. In order to determine the input referred noise

current we can integrate the output noise voltage spectral density with respect to

frequency, and divide by the peak transimpedance gain as shown below.

|in,in|2 =1

|ZTpk|2

∞∫

0

d|vn,out|2df

df (4.10)

The result of this integral is estimated using a numerical integration from 0 to

50 GHz. Simulation data for the output noise voltage spectral density was created

up to 50 GHz with data points spaced every 10 MHz. The root mean squared input

referred noise current was found to be 0.598 µA rms when the AGC voltage was set to

0.0 V. When the AGC voltage was set to 3.0 V, the root mean squared input referred

noise current was increased to 2.55 µA rms.

Figure 4.12 shows the BER plots with these values for the input referred noise

current. For these calculations, a photodiode responsivity of 0.9 A/W was used, the

pulse shape dependent term I1 was set to 1, and the extinction ratio re was set to

10 dB.

We can see that the sensitivity is approximately 7 dB lower with an AGC of 3.0 V.

However, since the difference in the transimpedance gain is 18 dB, if we assume the


−28 −26 −24 −22 −20 −18 −16 −14−15

−10

−5

0

Pavg(dBm)

log(B

ER

)

AGC = 0.0 VAGC = 3.0 V

Figure 4.12: Estimated BER for the 2.5 Gbps TIA

TIA output voltage is held constant, we would expect the photodiode current to be

at least 18 dB higher when the AGC is equal to 3.0 V.

∣

∣

∣

∣

Vout

Iin

∣

∣

∣

∣

= 64 dBΩ (4.11)

∣

∣

∣

∣

Vout

I ′in

∣

∣

∣

∣

= 46 dBΩ (4.12)

∣

∣

∣

∣

I ′in

Iin

∣

∣

∣

∣

= 18 dB (4.13)

The photodiode current is related to the input optical power by the responsivity

of the photodiode. An 18 dB increase in the photodiode current corresponds to an

18 dB increase in the average input optical power.

Iin = RPavg (4.14)

I ′in = RP ′

avg (4.15)∣

∣

∣

∣

I ′in

Iin

∣

∣

∣

∣

=

∣

∣

∣

∣

P ′avg

Pavg

∣

∣

∣

∣

= 18 dB (4.16)


This shows that the performance will meet the specified GPON sensitivity re-

quirement of -21 dBm shown in Table 1.2.

4.5 Measured Results

4.5.1 Measurement Setup

The complete four port S-parameters for the 2.5 Gbps TIA were measured using on-

wafer probing with an HP8510 two port vector network analyzer (VNA). In order to

obtain the four port S-parameters, six separate measurements needed to be made.

The two port S-parameters were measured between each of the ports on the TIA

while terminating the unconnected ports with 50 Ω terminations. The full set of four

port S-parameters was later combined from these six measurements. Each of the

measurements were taken over a frequency span of 45 MHz to 40 GHz with a total

of 801 points.

In order to characterize the TIA’s transimpedance gain and group delay under

practical situations, some post processing of the measured S-parameters was required.

The four port S-parameters were loaded into Agilent’s ADS as a dataset. Once the S-

parameters were loaded, ideal capacitances representing the photodiode capacitance

and the corresponding dummy capacitance were added in simulation. Figure 4.13

shows this post processing setup. The TIA was terminated at the outputs using ideal

terminations. An AC simulation was then run to calculate the TIA’s transimpedance

gain and group delay using different photodiode capacitances.

4.5.2 Transistor Model Verification

In order to verify the transistor model used in the simulation results against fabri-

cated data, a 30 finger transistor was fabricated and measured in the common source

configuration for a number of different bias conditions. Due to a lack of available


S Parameters

Measured

4 PortCPD

Cdummy

Ideal Ideal

Iin

50Ω

50Ω

Vout

Figure 4.13: Simulation Setup

chip space, de-embedding structures were not fabricated and the effects of the pads

and short transmission lines were de-embedded using EM simulations performed with

Agilent’s Momentum EM software.

Figures 4.14 and 4.15 show the de-embedded measured results of the 30 finger com-

mon source transistor with a gate bias of Vg = 0.8 V and Vg = 1.2 V respectively.

The measured results are compared to the models obtained from TSMC. Results for

the three RF corner cases are shown, Slow/Slow, Typical/Typical, and Fast/Fast.

The RF corner cases are statistically determined to cover the effects of process vari-

ations. The Slow/Slow model represents the worst case performance based on the

process variations and the Fast/Fast model represents the best case performance.

The Slow/Slow model refers to the slow nMOS model and the slow pMOS model.

Since this design only uses nMOS transistors we will now refer to the three corner

cases as simply slow, typical, and fast.

These results show that for frequencies below 5 GHz, the slow model is the most

consistent with the measured results. At higher frequencies, the typical model seems

more accurate when compared to the measured results.

From these results we can expect better agreement between the measured TIA

results and the simulated results if the slow model is used.


S11

Simulated FF ModelSimulated TT ModelSimulated SS ModelMeasured

5 10 15 20 25 30 35 40−50

−45

−40

−35

−30

−25

−20

−15

−10

Frequency (GHz)

|S12|(

dB

)


(a) (b)

5 10 15 20 25 30 35 40−2

0

2

4

6

8

10

12

Frequency (GHz)

|S21|(

dB

)


S22


(c) (d)

Figure 4.14: S-Parameters for a 30 Finger Common Source Transistor Vd = 1.8 V,Vg = 0.8 V


S11


5 10 15 20 25 30 35 40−50

−45

−40

−35

−30

−25

−20

−15

−10

Frequency (GHz)

|S12|(

dB

)


(a) (b)

5 10 15 20 25 30 35 40−2

0

2

4

6

8

10

12

Frequency (GHz)

|S21|(

dB

)


S22


(c) (d)

Figure 4.15: S-Parameters for a 30 Finger Common Source Transistor Vd = 1.8 V,Vg = 1.2 V


4.5.3 Transimpedance Measurements

Figures 4.16 a) and b) show the measured transimpedance gain of the 2.5 Gbps

TIA with an ACG voltage of 0.0 V (Maximum Gain). Figure 4.16 a) shows the

raw measured data without an external input capacitance and Figure 4.16 b) shows

the transimpedance gain with a 250 fF input capacitance connected to the input to

simulate the effects of the photodiode capacitance.

The Figures also show the simulated results using the three corner models. As

expected, based on the results for the 30 finger transistor, the slow model shows the

best agreement with the measured results.

109

1010

25

30

35

40

45

50

55

60

65

Frequency (Hz)

Tra

nsi

mp

edance

(dB

Ω)

Simulated FFSimulated TTSimulated SSMeasured

109

1010

20

30

40

50

60

70

Frequency (Hz)

Tra

nsi

mp

edance

(dB

Ω)

Simulated FFSimulated TTSimulated SSMeasured

(a) (b)

Figure 4.16: Simulated vs. Measured Transimpedance a) CPD = 0 fF b) CPD = 250fF

Figures 4.17 and 4.18 show the transimpedance gain as the AGC voltage is ad-

justed from 0.0 V to 3.0 V. Figure 4.17 shows the transimpedance gain with no input

capacitance, Figure 4.18 shows the transimpedance gain with an external input ca-

pacitance of 250 fF. Both plots show simulated results using the slow corner model

only.


109

1010

25

30

35

40

45

50

55

60

65

Frequency (Hz)

Tra

nsi

mp

edance

(dB

Ω)

Simulated AGC=0.0 VMeasured AGC=0.0 VSimulated AGC=2.4 VMeasured AGC=2.4 VSimulated AGC=2.5 VMeasured AGC=2.5 VSimulated AGC=2.6 VMeasured AGC=2.6 VSimulated AGC=3.0 VMeasured AGC=3.0 V

Figure 4.17: Simulated and Measured Transimpedance Gain with Various AGC Volt-ages - CPD = 0 fF

109

1010

20

30

40

50

60

70

Frequency (Hz)

Tra

nsi

mp

edance

(dB

Ω)

Simulated AGC=0.0 VMeasured AGC=0.0 VSimulated AGC=2.4 VMeasured AGC=2.4 VSimulated AGC=2.5 VMeasured AGC=2.5 VSimulated AGC=2.6 VMeasured AGC=2.6 VSimulated AGC=3.0 VMeasured AGC=3.0 V

Figure 4.18: Simulated and Measured Transimpedance Gain with Various AGC Volt-ages - CPD = 250 fF


4.5.4 Group Delay Measurements

Another important parameter to measure is the group delay of the TIA. It is impor-

tant to have a constant group delay in the signal band. A flat group delay implies

linear phase which means there is no distortion of the signal. The group delay is

defined in equation 4.17 below as the negative of the derivative of the phase of the

TIA with respect to frequency. The measurement of the group delay is challenging

as it is the derivative of the phase, so any sudden change in the phase will result in a

large spike in the group delay. Figures 4.19 a) and 4.20 a) show the measured phase

of the TIA with an AGC of 0.0 V and 3.0 V respectively. Due to measurement noise,

the phase measurement has a number of sharp variations. In order to get a reasonable

plot of the group delay, the phase curve was smoothed using post processing before

the derivative was taken. The smoothed phase is shown in the figures along with the

simulated curves. Figures 4.19 b) and 4.20 b) show the resulting group delay after

the phase was smoothed.

τg = −dφ

dω(4.17)

1 2 3 4 5 6 7 8 9 10−3

−2

−1

0

1

2

3

Frequency (GHz)

Phase

(rad)

SimulatedMeasuredSmoothed

1 2 3 4 5 6 7 8 9 100

50

100

150

200

250

Frequency (GHz)

Gro

up

Del

ay

(ps)

SimulatedMeasured (Smoothed)

(a) (b)

Figure 4.19: Simulated vs. Measured Phase and Group Delay - AGC = 0.0 V a)Phase b) Group Delay


1 2 3 4 5 6 7 8 9 10−3

−2

−1

0

1

2

3

Frequency (GHz)

Phase

(rad)

SimulatedMeasuredSmoothed

1 2 3 4 5 6 7 8 9 100

50

100

150

200

Frequency (GHz)

Gro

up

Del

ay

(ps)

SimulatedMeasured (Smoothed)

(a) (b)

Figure 4.20: Simulated vs. Measured Phase and Group Delay - AGC = 3.0 V a)Phase b) Group Delay

The bit period for a 2.5 Gbps signal is equal to 400 ps. The variation in the group

delay over the band of interest should be significantly less than a bit period to ensure

minimal distortion of the signal. The variation in the group delay for the TIA with

an AGC voltage of 0.0 V is less than 10 ps and the variation is the group delay with

an AGC voltage of 3.0 V is less than 25 ps.

4.5.5 Noise Measurements

Since the input referred noise current is not physical, it cannot be directly measured.

Instead, the noise properties of the TIA can be characterized in terms of the following

noise parameters [26].

Fmin - Minimum Noise Factor

Rn - Equivalent Noise Resistance

Yopt = (Gopt + jBopt) - Optimum Source Admittance

Using these noise parameters, the noise properties of the system can be calculated

with different input impedances. The Yopt term is the input impedance that results in


the minimum noise figure Fmin. Using these parameters we can derive an expression

for the input referred noise current density.

We will start with the noise representation shown in Figure 4.21. The TIA is

represented by a noiseless two-port network with the noise referred to the input. The

photodiode in the system is represented by a noise source and a source impedance

YS.

YSidiode

vn

in

Noiseless

Network

Two-Port

TIAPhotodiode

Figure 4.21: Noisy Two-port Network Representation

We wish to convert this representation to the one shown in Figure 4.22, where iin

is the input referred noise current.

YSidiode iin

Noiseless

Network

Two-Port

TIAPhotodiode

Figure 4.22: Simplified Noisy Two-port Network Representation

From the representation shown in Figure 4.21, we can calculate the total short

circuit current as follows.

isc = idiode + in + vnYS (4.18)


We can now determine the total mean squared short-circuit noise current spectral

density.

d|isc|2df

=d|idiode|2

df+

d|in + vnYS|2df

− 2d(i∗diode(in + vnYS))

df(4.19)

Since the noise from the photodiode and the noise from the TIA are not correlated,

the third term in this expression is equal to zero. We can now write the expression

for the total mean squared short-circuit noise current spectral density.

d|isc|2df

=d|idiode|2

df+

d|in + vnYS|2df

(4.20)

In this equation the second term is the mean squared input referred noise current

spectral density.

d|in,in|2df

=d|in + vnYS|2

df(4.21)

Since the two noise sources in and vn are correlated, we can separate in into the

portion that is correlated inc, and the portion that is uncorrelated inu. The correlated

source is related to the source vn using the correlation admittance inc = Ycorvn [26].

d|in,in|2df

=d|inu + inc + YSvn|2

df(4.22)

d|in,in|2df

=d|inu + (Ycor + YS)vn|2

df(4.23)


Next, we can express the noise voltage in terms of an equivalent noise resistance

Rn and the uncorrelated noise current in terms of an equivalent noise conductance

Gu as follows

d|inu|2df

= 4kT0Gu (4.24)

d|vn|2df

= 4kT0Rn (4.25)

where k is the Boltzmann constant, and T0 is the temperature in Kelvin. By sub-

stituting these expressions into equation 4.23 we can get the following expression for

the input referred noise current density. The units of the input referred noise current

will be A/√

Hz.

√

d|in,in|2df

=√

4kT0Gu + |GS + jBS + Gcor + jBcor|24kT0Rn (4.26)

where the uncorrelated noise conductance Gu and the correlation admittance Ycor

can be written in terms of the noise parameters as shown below.

Gcor =Fmin − 1

2Rn

− Gopt (4.27)

Bcor = −Bopt (4.28)

Gu = (G2opt − G2

cor)Rn (4.29)

The noise parameters of the device were measured using the technique described

in appendix B. The noise figure of the device at a given source impedance is given

as.


F = Fmin +Rn

Gs

|Ys − Yopt|2 (4.30)

The noise parameters can be determined mathematically with noise figure mea-

surements at a minimum of four unique source impedances. An impedance tuner is

used to present the TIA with a number of different input impedances and the noise

figure of the device is measured at each input impedance.

Figure 4.23 shows the measured noise parameters and the calculated input referred

noise current spectral density of the TIA with the AGC voltage set to 0.0 V. The

measured data is compared with data simulated using Agilent’s ADS software. As

with the transimpedance data, the slow transistor model was used. A significant

amount of variation is shown in the results. This is a result of the uncertainty in the

noise figure measurements as well as the uncertainty in the measurement of the input

impedance. The data follows the trends in the simulated data.

Figure 4.24 shows the measured noise parameters and the calculated input referred

noise current spectral density of the TIA at an AGC voltage of 3.5 V (minimum gain).

Again the results show significant variance due to the measurement uncertainty. The

results again follow the trends in the simulation.

4.5.6 Common Mode Rejection Ratio Measurement

The common mode rejection ratio (CMRR) is a measure of the TIA’s ability to reject

common mode signals. This is important for this amplifier because its intended

application is in an integrated system where there will be crosstalk generated by the

other circuits on the same substrate. Cross talk from other circuits coupled into the

TIA should mostly be common mode signals. If the TIA has a large CMRR, it means

it will be able to reject these signals and they won’t be added to the amplified signal.

In order to calculate the CMRR, the equivalent differential and common mode two

port S-parameters need to be calculated from the measured four port S-parameters [23].


1 2 3 4 5 6 7 8 9 100

2

4

6

8

10

Frequency (GHz)

Fmin

SimulatedMeasured

Γ opt

SimulatedMeasured

(a) (b)

1 2 3 4 5 6 7 8 9 10100

200

300

400

500

600

700

800

Frequency (GHz)

Rn

(Ω)

SimulatedMeasured

1 2 3 4 5 6 7 8 9 100

10

20

30

40

50

60

Frequency (GHz)

Equiv

ale

nt

Nois

eC

urr

ent

Den

sity

pA

/√Hz

SimulatedMeasured

(c) (d)

Figure 4.23: TIA Noise measurements AGC = 0.0 V a) Minimum Noise Factor Fmin

b) Optimum Source Reflection Coefficient Γopt c) Equivalent Noise Re-sistance Rn d) Input Referred Noise Current Spectral Density


1 2 3 4 5 6 7 8 9 1010

12

14

16

18

20

22

Frequency (GHz)

Fmin

SimulatedMeasured

Γ opt

SimulatedMeasured

(a) (b)

1 2 3 4 5 6 7 8 9 10200

300

400

500

600

700

800

900

1000

Frequency (GHz)

Rn

(Ω)

SimulatedMeasured

1 2 3 4 5 6 7 8 9 1010

20

30

40

50

60

Frequency (GHz)

Equiv

ale

nt

Nois

eC

urr

ent

Den

sity

pA

/√Hz

SimulatedMeasured

(c) (d)

Figure 4.24: TIA Noise measurements AGC = 3.5 V a) Minimum Noise Factor Fmin

b) Optimum Source Reflection Coefficient Γopt c) Equivalent Noise Re-sistance Rn d) Input Referred Noise Current Spectral Density


Equations 4.31 to 4.38 show these conversions using the port numbering convention

shown in 4.25.

S Parameters

Measured

4 Port

1

43

2

Figure 4.25: Port Numbering Convention

Sd1d1 =1

2(S11 − S31 − S13 + S33) (4.31)

Sd1d2 =1

2(S12 − S32 − S14 + S34) (4.32)

Sd2d1 =1

2(S21 − S41 − S23 + S43) (4.33)

Sd2d2 =1

2(S22 − S42 − S24 + S44) (4.34)

Sc1c1 =1

2(S11 + S31 + S13 + S33) (4.35)

Sc1c2 =1

2(S12 + S32 + S14 + S34) (4.36)

Sc2c1 =1

2(S21 + S41 + S23 + S43) (4.37)

Sc2c2 =1

2(S22 + S42 + S24 + S44) (4.38)

Once the differential and common mode S-parameters have been calculated, the

CMRR is defined as the ratio of the differential gain to the common mode gain.

CMRR =Sd2d1

Sc2c1(4.39)


Figure 4.26 shows a plot of the measured CMRR for the 2.5 Gbps TIA. It can be

seen that the TIA achieves a CMRR of approximately 29 dB throughout the frequency

band of interest from 0 to 2 GHz.

1 2 3 4 5 6 7 8 9 1024

26

28

30

32

34

36

38

Frequency (GHz)

CM

RR

(dB

)

Figure 4.26: Measured Common Mode Rejection Ratio

4.6 Conclusion

A 2.5 Gbps transimpedance amplifier has been presented in this chapter. The TIA

uses a shunt-shunt feedback topology with a cascode gain stage. The cascode topology

is used to reduce the input capacitance of the amplifier and increase the bandwidth.

The amplifier has been designed to be pseudo differential in order to improve the

common mode rejection. This is important because the intended application of the

TIA is an integrated transceiver. The differential structure will help reduce the impact

of noise coupled into the TIA from other system components. The TIA also has a

variable gain to increase the range of acceptable input powers such that the amplifier

isn’t saturated.

Simulation results have been presented that show a maximum transimpedance

gain of 64 dBΩ and a transimpedance bandwidth of 1.8 GHz with a photodiode ca-

pacitance of 250 fF. The average input referred noise current spectral density over


the TIA bandwidth is 9.0 pA/√

Hz. Using the variable gain control the TIA tran-

simpedance gain can be reduced to 46 dBΩ. Measured results have also been presented

for the TIA and show a good match to simulated results. The S-parameters of the

differential circuit were measured to obtain the transimpedance gain, group delay

and common mode rejection ratio. The noise of the TIA was characterized by first

measuring the noise parameters of the TIA. The noise parameters are then used to

determine the input referred noise current spectral density.

The TIA performance is compared to other TIAs operating at similar bit rates be-

low in table 4.2. The transimpedance gain and noise performance compare favourably

with previous work.

Table 4.2: 2.5 Gbps TIA Performance Comparison

Technology ZT BW CP D Noise Supply Voltage Power Dissipation

Performance

[4] 0.6 µm CMOS 58 dBΩ 950 MHz 500 fF 6.3 pA/√

Hz 5 V 85 mW

[6] 0.6 µm CMOS 55.3 dBΩ 2.2 GHz 500 fF -17 dBm 5 V 210 mW

[5] 0.25 µm CMOS 80 dBΩ 670 MHz 1 pF 0.54 µA 2.5 V 27 mW

[15] 0.15 µm CMOS 59 dBΩ 5.9 GHz - 31 µAp-p 2 V -

[16] 0.18 µm CMOS 58.7 dBΩ 2.6 GHz 200 fF 13 pA/√

Hz 1.8 V 47 mW

[18] 0.5 µm CMOS 64.0 dBΩ 1.2 GHz 600 fF 0.6 µA - 115 mW

This work 0.18 µm CMOS 64.0 dBΩ 1.8 GHz 250 fF 9.0 pA/√

Hz 3.5 V 115 mW

Table 4.2 shows a number of different measures of TIA noise performance. The

noise performance for the TIAs in [4] and [16] are given by the average input referred

noise current spectral density, with the units of A/√

Hz. When multiplied by the

square root of the noise bandwidth of the system, this value will give an approximation

of the root mean squared input referred noise current of the device. The root mean

squared input referred noise current has been reported directly for the TIAs in [5]

and [18]. The noise performance of the TIA can also be measured in terms of the

sensitivity. In [15] this has been stated as the minimum required peak to peak signal

current at the input of the TIA to achieve a specific BER. If the TIA is integrated

with a photodiode, the sensitivity can be stated as a minimum received optical power


to achieve a specific BER as is done in [6].

Chapter 5

10 Gbps Transimpedance Amplifier

5.1 Introduction

It was shown in section 2.3.2 that by using a feedback topology, the frequency of

the input pole created by the photodiode capacitance could be raised by a factor

approximately equal to the gain of the voltage amplifier. However, for higher bit rate

TIAs, the bandwidth requirement is increased and the dominant pole of the TIA will

eventually be at the output of the voltage gain stage.

Generally there is a direct trade-off between the gain and the bandwidth of the

voltage amplifier. If the gain is reduced to improve the bandwidth, the magnitude of

the input pole of the TIA is reduced. If the gain is raised, the voltage amplifier may

limit the bandwidth of the TIA. This chapter looks at using bandwidth enhancement

techniques to improve the bandwidth of the voltage amplifier, while maintaining a

reasonable gain.

5.2 Inductive Peaking

Inductive peaking can be used to extend the bandwidth of an amplifier. The basic

principle is to increase the speed of the device by allowing the load capacitance of

73

CHAPTER 5. 10 GBPS TRANSIMPEDANCE AMPLIFIER 74

the device to resonate with an inductor. Inductive peaking can be accomplished in

the CMOS process with the use of monolithic inductors created on the upper metal

layers. Active inductors can also be used, but they generally consume more voltage

headroom and add noise to the circuit. The drawback to using inductive peaking is

the increased area required to create the inductors.

5.2.1 Shunt and Series Inductive Peaking

Figure 5.1 shows several methods of inductive peaking. Each diagram shows the

equivalent circuit of the output node of a transistor amplification stage. Figure 5.1

a) shows the equivalent circuit without inductive peaking. A resistive load is used to

create broadband amplification down to DC. Assuming this is the dominant pole in

the system, the bandwidth of the amplifier is determined by the RC time constant

created between the resistive load and the load capacitance.

An inductor is placed in series with the load capacitance CL in Figure 5.1 b)

creating a series resonant circuit. As the frequency increases and nears the resonance

frequency, the impedance looking into the inductor is reduced, pulling more current.

This results in a speed increase as more of the current Iin is used to charge the load

capacitance CL.

In Figure 5.1 c) the inductor is placed between the load resistor and the voltage

rail. This method of inductive peaking is called shunt inductive peaking because the

inductor is connected in parallel with the load capacitance. As the frequency in-

creases, the shunt inductor increases the impedance looking into the resistor allowing

more of the current Iin to charge the load capacitance and increase the speed.

There is a limit to the increase in bandwidth for both series and shunt peaking.

As the inductance is increased, the bandwidth is increased but there will also exist

an unwanted peak in the frequency response and the group delay. Beyond a certain

inductance, the bandwidth will no longer be increased but the peaking will become


Iin

RD

Vout

CL Iin

L1

RD

Vout

CL

(a) (b)

L1

Iin

RD

Vout

CL

(c)

Figure 5.1: Various Methods of Inductive Peaking a) RC Circuit Without InductivePeaking b) Series Inductive Peaking c) Shunt Inductive Peaking


larger. The values of inductance that produce a maximally flat gain response and a

maximally flat group delay are given by

L1 = mR2DCL (5.1)

where the appropriate values of m are given in Table 5.1. The values of m that

maximize the bandwidth of the frequency response are also given. These values are

taken from [24].

Table 5.1: Values of m for Shunt and Series Inductive Peaking

Response Series Inductive Peaking Shunt Inductive Peaking

Maximum 0.53 0.76Bandwidth

Maximally Flat 0.5 0.4Frequency Response

Maximally Flat 0.333 0.3Group Delay

In order to compare the bandwidth improvement achieved using series and shunt

inductive peaking, the frequency response and group delay are plotted in Figure 5.2

for each type of peaking. The plots show the normalized transimpedance gain for

each circuit and the frequency axis of each plot is normalized to the 3 dB bandwidth

of the unmodified RC circuit. Figure 5.2 a) and b) show the frequency response

and group delay of each of the circuits configured for a maximally flat group delay.

Shunt inductive peaking shows a bandwidth improvement of 1.58 times, while series

inductive peaking shows an improvement of 1.39 times. Figure 5.2 c) and d) show

the frequency response and group delay of the unmodified RC circuit as well as the

shunt and series peaked circuits configured to produce a maximally flat frequency

response. In this case shunt and series inductive peaking show an improvement of

1.73 and 1.42 respectively. Figure 5.2 e) and f) show the frequency response and

group delay of the same circuits configured for the maximum possible bandwidth.


Shunt inductive peaking provides a maximum bandwidth improvement of 1.88 times

the original RC bandwidth. Series inductive peaking shows minimal improvement in

bandwidth beyond the maximally flat frequency response bandwidth.


0 0.5 1 1.5 2 2.5 3−12

−10

−8

−6

−4

−2

0

2

Normalized Frequency

Norm

ali

zed

Tra

nsi

mp

edance

Gain

(dB

Ω)

No PeakingSeries PeakingShunt Peaking

0 0.5 1 1.5 2 2.5 30

10

20

30

40

50


Gro

up

Del

ay

(ps)


(a) (b)

0 0.5 1 1.5 2 2.5 3−14

−12

−10

−8

−6

−4

−2

0

2


Norm

ali

zed

Tra

nsi

mp

edance

Gain

(dB

Ω)


0 0.5 1 1.5 2 2.5 30

10

20

30

40

50

60


Gro

up

Del

ay

(ps)


(c) (d)

0 0.5 1 1.5 2 2.5 3−14

−12

−10

−8

−6

−4

−2

0

2


Norm

ali

zed

Tra

nsi

mp

edance

Gain

(dB

Ω)


0 0.5 1 1.5 2 2.5 30

10

20

30

40

50

60

70


Gro

up

Del

ay

(ps)


(e) (f)

Figure 5.2: Bandwidth Improvement Using Shunt and Series Inductive Peaking a)and b) Maximally Flat Group Delay c) and d) Maximally Flat FrequencyResponse e) and f) Maximum Bandwidth


5.2.2 Shunt-Series Inductive Peaking

This analysis shows that shunt and series peaking are effective at improving the band-

width with the presence of a large capacitive load. These types of inductive peaking

are particularly useful in output buffers. However, a new analysis is needed when us-

ing inductive peaking between cascaded gain stages where the parasitic capacitance

at the output of the first stage is comparable to the load capacitance. Figure 5.3

shows the updated equivalent circuits for shunt and series inductive peaking.

L1

IinC1

RD

Vout

C2 Iin

Vout

C2C1

L1

RD

(a) (b)

Figure 5.3: Modified Shunt and Series Peaking for Interstage Bandwidth Extensiona) Shunt Inductive Peaking b) Series Inductive Peaking

Shunt inductive peaking is no different than before, as the two capacitances C1

and C2 are added in parallel. The size of the inductor will be chosen based on

the combination of the two capacitances. In the case of series inductive peaking,

the inductor separates the two capacitances. This causes two separate resonance

frequencies in the circuit and changes the performance substantially. These resonance

frequencies are shown graphically in Figure 5.4. As the frequency increases, the first

resonance ω1 occurs between the series inductor L1 and the load capacitor C2.

ω1 =1√

L1C2

(5.2)

As before, the resonance creates a short circuit and pulls more current into the


Iin

Vout

C2

L1

RD

ω = ω1

C1 Iin

Vout

C2

L1

RD

C1

I1

I2

ω > ω1

X

(a) (b)

Iin

Vout

C2

L1

RD

ω = ω2

C1

0 1 2 3 4−25

−20

−15

−10

−5

0

5


Norm

ali

zed

Tra

nsi

mp

edance

Gain

(dB

Ω)

ω2

ω1

(c) (d)

Figure 5.4: Resonance Frequencies Using Series Inductive Peaking a) Series Reso-nance Frequency at ω = ω1 b) Current Reversal Between ω1 and ω2 c) πNetwork Resonance Frequency at ω = ω2 d) Transimpedance Gain withResonance Frequencies Marked


load capacitance. At frequencies above ω1 there exists a 180 degree phase shift in

the impedance of the LC circuit, which produces a negative voltage at node X. This

negative voltage reverses the direction of the currents I1 and I2 flowing in the load

resistor RD and the parasitic capacitance C1, directing more current into the load

capacitance. This additional current results in a further increase in the magnitude

of the frequency response beyond the first resonance point and produces a peak in

the frequency response. The response is shown in Figure 5.4 d) with the resonance

frequencies marked. The frequency axis is normalized to the 3 dB bandwidth of the

unmodified RC circuit. In the previous case where the parasitic capacitance was

negligible, the load resistance could be increased to reduce the additional current I1

and reduce this undesired peaking. When the parasitic capacitance is comparable

in size to the load capacitance, adjusting the value of the load resistance has little

effect on the peak in the response since the additional current I2 still exists. Finally,

the second resonance frequency ω2 is reached when the π network consisting of the

components L1, C1,and C2 resonates.

ω2 =1

√

L1C1C2

C1+C2

(5.3)

This produces an infinite impedance at node X and all of the current flows through

the load resistor, returning the magnitude of the frequency response to the DC level.

By separating the capacitances C1 and C2, series inductive peaking significantly im-

proves the bandwidth of the circuit when compared to shunt inductive peaking when

using a similar sized inductor. The cost of this improvement is a peak in the frequency

response and the group delay.

The bandwidth improvement using this method of inductive peaking is limited by

a midband droop as the size of the series inductor is reduced. Figure 5.5 shows the

change in frequency response and group delay as the series inductor is increased. The

value of the inductor is equal to L1 = nR2DC2, and the value of n is swept from 0.5 to


2.0. The frequency axis is normalized to the 3 dB bandwidth of the unmodified RC

circuit.

0 1 2 3 4−30

−25

−20

−15

−10

−5

0

5


Norm

ali

zed

Tra

nsi

mp

edance

Gain

(dB

Ω)

n = 0.5n = 1.0n = 1.5n = 2.0

0 1 2 3 40

50

100

150


Gro

up

Del

ay

(ps)

n = 0.5n = 1.0n = 1.5n = 2.0

(a) (b)

Figure 5.5: Frequency Response and Group Delay as the Series Inductance is Reduced

It is possible to improve this performance by adding a shunt inductor. If cho-

sen properly, the shunt inductor will reduce the mid-band roll-off by increasing the

impedance looking into the load resistor. The shunt inductor will interact with the

other components and create a resonant circuit. It is important that this resonant

frequency be greater than ω2 such that the inductor doesn’t create another unwanted

peak in the frequency response and group delay. It has been found in [21] that the

following component relationships create the optimal performance when C1 is equal

to C2.

L1 = R2DC2 (5.4)

L2 = 0.5L1 (5.5)

Figure 5.6 shows a comparison of shunt inductive peaking, series inductive peak-

ing and shunt-series inductive peaking under the same load conditions. The plots

show the normalized transimpedance gain and group delay for each configuration.

The frequency axis is normalized to the bandwidth of the unmodified RC circuit.


Since both the series inductive peaking and the shunt-series inductive peaking have

an unavoidable peak in their response, the inductor in the shunt inductive peaking

circuit was adjusted to produce the maximum gain. Shunt inductive peaking shows a

bandwidth improvement of 1.74, the series inductive peaking shows an improvement

of 2.34, and the shunt-series inductive peaking shows an improvement of 3.25.

0 1 2 3 4−25

−20

−15

−10

−5

0

5


Norm

ali

zed

Tra

nsi

mp

edance

Gain

(dB

Ω)

No PeakingShunt PeakingSeries PeakingSeries−Shunt Peaking

0 1 2 3 40

50

100

150

200


Gro

up

Del

ay

(ps)

No PeakingShunt PeakingSeries PeakingSeries−Shunt Peaking

(a) (b)

Figure 5.6: Bandwidth Improvement Using Shunt, Series, and Shunt-Series InductivePeaking a) Transimpedance Gain b) Group Delay

Shunt-series inductive peaking shows a significant improvement in bandwidth

when compared to simple series or shunt inductive peaking. However, it is impor-

tant to examine the effects of the peak in the frequency response and group delay on

random data. The peak in the frequency response will create high frequency ringing,

while the peak in the group delay will increase the inter symbol interference (ISI).

Figures 5.7 to 5.10 show the simulated eye diagrams using a 10 Gbps pseudo random

data sequence as the bandwidth of the circuit is reduced from 11 GHz down to 5 GHz.

The pseudo random bit sequence used has a code length of 217-1 bits. However, due

to memory restrictions, the sequence was only run for 2000 bits. As the bandwidth

is reduced from 11 GHz down to 9 GHz we see a small reduction in the eye opening

in the horizontal direction. This is a result of the peak in the group delay. As the

bandwidth is reduced down to 7 GHz we see more horizontal eye closure since the

peak in group delay begins to have more effect. We also see a vertical eye closure due


to the limited bandwidth. As the bandwidth is reduced to 5 GHz we see significant

vertical and horizontal eye closure. Since there is a trade-off between the bandwidth

and the amount of noise, a reasonable trade-off would be to produce a bandwidth

between 7 and 9 GHz.

0 5 10 1520

25

30

35

40

45

Frequency (GHz)

Tra

nsi

mp

edance

(dB

Ω)

0 5 10 150

25

50

75

100

125

Gro

up

Del

ay

(ps)

0 0.05 0.1 0.15 0.2 0.25 0.3−0.5

0

0.5

Time (ns)

Outp

ut

Volt

age

(V)

(a) (b)

Figure 5.7: Transient Response with a Bandwidth of Approximately 11 GHz a) Tran-simpedance Gain and Group Delay b) 10 Gbps Eye Diagram

0 5 10 1510

15

20

25

30

35

40

Frequency (GHz)

Tra

nsi

mp

edance

(dB

Ω)

0 5 10 150

25

50

75

100

125

150

Gro

up

Del

ay

(ps)

0 0.05 0.1 0.15 0.2 0.25 0.3−0.4

−0.3

−0.2

−0.1

0

0.1

0.2

0.3

0.4

Time (ns)

Outp

ut

Volt

age

(V)

(a) (b)



0 5 10 150

5

10

15

20

25

30

35

40

Frequency (GHz)

Tra

nsi

mp

edance

(dB

Ω)

0 5 10 150

25

50

75

100

125

150

175

200

Gro

up

Del

ay

(ps)

0 0.05 0.1 0.15 0.2 0.25 0.3

−0.2

−0.1

0

0.1

0.2

0.3

Time (ns)

Outp

ut

Volt

age

(V)

(a) (b)


0 5 10 15−10

0

10

20

30

40

Frequency (GHz)

Tra

nsi

mp

edance

(dB

Ω)

0 5 10 150

50

100

150

200

250

Gro

up

Del

ay

(ps)

0 0.05 0.1 0.15 0.2 0.25 0.3−0.25

−0.2

−0.15

−0.1

−0.05

0

0.05

0.1

0.15

0.2

Time (ns)

Outp

ut

Volt

age

(V)

(a) (b)



5.3 10 Gbps TIA Design

The topology chosen for the transimpedance stage is a common source configuration

using shunt-shunt feedback and shunt-series inductive peaking at the output. A

pseudo differential structure has been chosen for this design to reduce the effect of

common mode noise on the receiver sensitivity. The design is pseudo differential since

the input signal from the photodiode is not differential and will only be fed into one

of the inputs. There is a sensitivity penalty for making the design differential, but

this penalty will be offset by the common mode noise rejection. This is important if

the TIA will be integrated on the same substrate as other receiver components. A

differential design also offers other benefits such as supply independent biasing.

Another important aspect of this design is that it will be DC coupled. The biasing

components would need to be exceptionally large to meet the low frequency cutoff

specifications discussed in chapter 1. Again, for the purpose of higher integration, the

design will be DC coupled to eliminate the need for large external biasing components.

Unlike the TIA presented in chapter 4, this TIA was designed with a fixed

transimpedance and does not have variable gain. This was done because the tran-

simpedance is lower in this amplifier due to the lower feedback resistance required to

meet the bandwidth specifications.

Figure 5.11 shows the proposed topology for the TIA input stage.


Cdummy

M1

RFB

I1

CL

CL

L2

RD

L1

L1

RFB

M2

L2

RD

Figure 5.11: Differential TIA Input Stage Using Shunt-Series Inductive Peaking


5.3.1 Noise Analysis

Figure 5.12 shows the equivalent half circuit of the differential topology described

above.

IPD

RD

CPD

M1

RFB

I1/2

L1

L2

C = ∞

CL

Vout

Figure 5.12: TIA Input Stage Half Circuit

In this section, a noise analysis will be done on this half circuit, such that the

optimum component values can be determined to maximize the sensitivity of the

TIA while making reasonable trade-offs with design area and power consumption.

It is desirable to determine the optimum device size for the transistor M1 to

produce the lowest possible noise. The size of the common source transistor largely

determines the values of the other circuit components. The input and output parasitic

capacitance of the device determine the values of the shunt and series inductors

required to achieve the desired bandwidth. The load resistor is then chosen to achieve

a flat magnitude response. Finally, the value of the feedback resistance is determined

by the input capacitance since an input pole is formed by the feedback resistor and

the total input capacitance.

In order to model the noise in the TIA, the circuit is broken up into three cascaded

networks as shown in Figure 5.13.


YPD

YL

Network 1 Network 2 Network 3

YFB

Figure 5.13: Cascaded Networks

The first network is a shunt admittance that will represent the photodiode capac-

itance. The second network is the combination of the common source transistor and

the feedback admittance. The third network is another shunt admittance represent-

ing the load resistance RD and shunt inductance L2. For simplicity, the inductors

L1 and L2 are treated as ideal. For this reason, the series inductor L1 and the load

capacitance are not included in the analysis since they don’t contribute to the input

referred noise current. In reality, the inductors will have finite Q and will have an

impact on the noise of the system. This is only the case for the series inductor because

series resistance in the shunt inductor can be compensated for by changing the value

of the load resistance RD.

The three networks above are cascaded, so we can analyze each separately and

combine them using their ABCD parameters. We will then have a noiseless network

with the noise referred to the input. First we need to add the noise sources to the

circuit. Figure 5.14 shows the noise sources for the transistor, as well as the load and

feedback resistors.

We will write the ABCD parameters for each network in the form shown below.

The first term in equation 5.6 is the ABCD parameters for the noiseless network and

the second term represents the noise referred to the input.


I1

1I

1

2I

2

1

V1

1YPD V

1

2,V 2

1

IN

vFB YFB

I2

2I

3

1I

3

2

V2

2,V 3

1YL

vRL

V3

2

Network 1 Network 2 Network 3

VN M1

Figure 5.14: Cascaded Networks with Noise Sources

V1

I1

=

A B

C D

V2

−I2

+

VN

IN

(5.6)

Since Network 1 is simply the photodiode capacitance, we model it as noiseless.

The ABCD parameters are easily derived.

V 11

I11

=

1 0

YPD 1

V 12

−I12

(5.7)

We next derive the ABCD parameters for the common source transistor with

feedback. This analysis is shown in more detail in [25] as well as appendix A. An

equivalent Y parameter network is used to determine the combined Y-parameters

shown below

I21

I22

=

IN − Y11VN − YFBvFB

−Y21VN + YFBvFB

+

(Y11 + YFB) (Y12 − YFB)

(Y21 − YFB) (Y22 + YFB)

V 21

V 22

(5.8)

where Y11, Y12, Y21, and Y22 are the Y-parameters of the common source transistor


and YFB is the admittance of the feedback network. VN and IN are the input referred

noise voltage and noise current of the common source transistor, and vFB is the noise

voltage created by the feedback resistance.

These Y-parameters can then be converted to the following ABCD parameters as

shown in [26].

V 21

I21

=

−(Y22+YFB)(Y21−YFB)

−1(Y21−YFB)

−∆y

(Y21−YFB)−(Y11+YFB)(Y21−YFB)

V 22

−I22

+

Y21

(Y21−YFB)

(

VN − YFB

Y21vFB

)

YFB(Y11+Y21)(Y21−YFB)

(VN − vFB) + IN

(5.9)

where

∆y = (Y22 + YFB)(Y11 + YFB) + (Y12 − YFB)(Y21 − YFB)

Finally, the ABCD parameters for Network 3 can be derived as shown below

V 31

I31

=

1 0

YL 1

V 32

−I32

+

0

−YLvRL

(5.10)

where YL is the admittance of the load and vRL is the noise voltage that represents

the thermal noise created by the resistive component of the load.

Now that we have the ABCD parameters for each network we can use the following

identity to convert the circuit to a single noiseless network with the noise sources

referred to the input.

V1

I1

=

A1 B1

C1 D1

A2 B2

C2 D2

A3 B3

C3 D3

V2

−I2

+

V ′N

I ′N

(5.11)


V ′N

I ′N

=

A1 B1

C1 D1

A2 B2

C2 D2

V 3N

I3N

+

A1 B1

C1 D1

V 2N

I2N

+

V 1N

I1N

(5.12)

Next we can use the procedure shown in [25] as well as appendix A to obtain expres-

sions for the noise parameters Rn, Gu and Ycor with respect to the circuit component

values. The input referred noise current spectral density can be calculated from these

noise parameters using the same method shown in section 4.5.5.

√

d|in,in|2df

=√

4kT0Gu + |GS + jBS + Gcor + jBcor|24kT0Rn (5.13)

5.3.2 Optimum Device Size

In order to use the noise model to determine the optimum transistor device size the

model needs to be constrained. First, the photodiode capacitance is set to 250 pF,

which is a reasonable value. Photodiode capacitances are generally between 100 fF

and 500 fF [2]. Second, the drain current density is held constant as the transistor

size is varied. The drain current density is defined as the drain bias current divided

by the width of the transistor. The transistor is a multi-finger device with 2.5 µm

wide fingers. Models for the transistors are only available for 2.5 µm gate widths so

the finger size is restricted to this value. We will assume that this stage is loaded

with a similar gain stage with the same device size such that the load capacitance is

equal to the gate capacitance of the device used. The inductor L1 is determined by

rearranging equation 5.2 to get equation 5.14 below. The value of ω1 is selected to

achieve the desired bandwidth. L2 is simply half the value of L1 using the assumption

that the load capacitance is approximately equal to the drain capacitance. Finally,

the load resistance is set by rearranging equation 5.4 to get equation 5.15 below.


L1 =1

ω21CL

(5.14)

RD =

√

L2

CL

(5.15)

The next step is to determine the maximum allowable feedback resistance that

will still meet the required bandwidth. The feedback resistance combines with the

photodiode capacitance and the input capacitance of the common source transis-

tor to create a pole at the input. This was shown for a general feedback TIA in

equation 2.31. The frequency of this pole will change with the device size since the

input capacitance will change. To allow for a fair comparison, the feedback resistance

should also be varied along with the device size to maintain a constant bandwidth.

The change in input capacitance is approximately linear, so the feedback resistance

was decreased linearly to maintain a constant bandwidth. Figure 5.15 shows the mag-

nitude response and group delay as the transistor size is changed from 20 fingers to

100 fingers (2.5 µm width fingers). There is very little variation in the bandwidth and

group delay as the device size is varied, which shows that the feedback resistance has

been varied properly. The values of the feedback resistance were determined experi-

mentally. Figure 5.16 shows the change in the feedback resistance used to compensate

for the change in input capacitance.

An input referred noise current spectral density curve can now be calculated for

each device size. In order to compare the noise performance as the device size is

varied, the input referred noise current spectral density is averaged over the TIA’s

noise bandwidth. The noise bandwidth of a circuit is defined as the bandwidth of a

perfect rectangular filter that has the same peak value and area as the actual power

gain versus frequency characteristic of the system. The noise bandwidth of a circuit

is given by the following equation.


0 5 10 1525

30

35

40

45

50

55

Frequency (GHz)

Tra

nsi

mp

edance

(dB

Ω)

Width = 20 FingerWidth = 40 FingerWidth = 60 FingerWidth = 80 FingerWidth = 100 Finger

0 5 10 150

20

40

60

80

100

120

Frequency (GHz)

Gro

up

Del

ay

(ps)

Width = 20 FingerWidth = 40 FingerWidth = 60 FingerWidth = 80 FingerWidth = 100 Finger

(a) (b)

Figure 5.15: Transimpedance Gain and Group Delay as the Transistor Size is In-creased

20 30 40 50 60 70 80 90 100200

250

300

350

400

Transistor Size (Number of 2.5 µm Fingers)

Fee

dback

Res

ista

nce

(Ω)

Figure 5.16: Feedback Resistance versus Device Size


NBW ≡ 1

|Hpk|2

∞∫

0

|H(f)|2df (5.16)

For this circuit, the plot shown in Figure 5.17 shows the average input referred

noise current spectral density as the device size is swept from 10 fingers to 100 fingers

(a finger width of 2.5 µm is used). The drain current density is also varied and is

shown using the variable Iden. The plot shows that the optimum device size for the

input stage of the TIA under the specified conditions is approximately 27 fingers.

10 20 30 40 50 60 70 80 90 10020

25

30

35


Aver

age

Input

Ref

erre

dN

ois

eC

urr

ent

Den

sity

(pA/√Hz)

Iden=100 A/mIden=150 A/mIden=200 A/mIden=250 A/mIden=300 A/m

Figure 5.17: Optimum Device Size for Various Values of the Drain Bias Current Iden

We also notice in Figure 5.17 that the noise performance improves as the current

density is increased. Figure 5.17 shows an enlarged view of the area around the

optimum device size with a broader range of current densities. We can see from this

plot that the optimal current density is approximately 400 A/m. There will be a

direct trade-off between the current density and the power consumption. Since the

load resistor is unchanged, as the current density is increased the supply voltage is

increased as well as the current, leading to a large increase in power consumption. For

a 27 finger transistor with a drain current density of 400 A/m, the bias current will be

approximately 27 mA. The load resistor for this configuration would be 170 Ω which


means there will be a 4.6 V drop across the load resistor which will raise the required

supply voltage. This analysis also only considers half of the differential circuit. The

power consumption of the final amplifier will be twice this value.

20 25 30 35 4021.5

22

22.5

23

23.5

24

24.5

25

25.5


Aver

age

Input

Ref

erre

dN

ois

eC

urr

ent

Den

sity

(pA/√Hz)

Iden=100 A/m

Iden=250 A/m

Iden=400 A/m

Iden=550 A/m

Iden=700 A/m

Figure 5.18: Optimum Current Density

Next, we need to consider the component values used to create the optimum

performance. Figure 5.19 shows that as the device size is lowered, the value of the

series inductance is increased to maintain the specified bandwidth. This results in an

interesting trade-off. As the device size is lowered, a higher bandwidth can be achieved

with the same series inductor. However, in this case increasing the bandwidth beyond

the optimum value found in section 2.3.3 results in higher noise and lower receiver

sensitivity. In order to maintain the optimal bandwidth, the inductor needs to be

increased as the device size is reduced. Since the series inductor will be realized using

a spiral inductor, a higher inductance will result in a larger area, and a lower Q factor.

As mentioned before, the Q factor of the series inductor will have an effect on the

noise performance.

Figure 5.19 shows the value of the series inductor as the device size varied from 10

to 100 fingers. A reasonable value of inductance using the 0.18 µm CMOS technology

is approximately 2 nH. This occurs at a device size of 40 fingers. We can see from


previous plots that a device size of 40 fingers is a reasonable trade-off between noise

performance and design area.

20 30 40 50 60 70 80 90 1000.5

1

1.5

2

2.5

3

3.5

4

4.5


Ser

ies

Induct

ance

(nH

)

Figure 5.19: Series Inductance versus Device Size

Figure 5.20 shows the calculated transimpedance gain with the transistor at the

optimum size of 40 fingers. The transimpedance gain shows significant peaking. This

is due to the fact that the calculations assume that ideal inductors are used. The

inductor parasitics will significantly reduce the peaking.

5.3.3 Final Schematic

A 10 Gbps TIA has been designed using the transimpedance input stage described

above. A second voltage gain stage has been cascaded with the transimpedance stage

to increase the overall transimpedance gain. Finally an output buffer has been added

such that the circuit can be used to drive a 50 Ω load. Figure 5.21 shows a simplified

version of the schematic for the 10 Gbps TIA. Table 5.2 lists the component values

used.

5.3.4 On-Chip Inductors

The shunt and series inductors are implemented using square monolithic spiral induc-

tors. As mentioned previously, the Q factor of the shunt inductor is not important

since it is placed in series with the load resistor. The load resistor can be decreased


0 5 10 1530

35

40

45

50

55

Frequency (GHz)

Tra

nsi

mp

edance

(dB

Ω)

0 5 10 150

20

40

60

80

100

Frequency (GHz)

Gro

up

Del

ay

(ps)

(a) (b)

0 5 10 1510

15

20

25

30

35

40

45

Frequency (GHz)

Input

Ref

erre

dN

ois

eC

urr

ent

(pA/√Hz)

(c)

Figure 5.20: Transimpedance, Group Delay and Input Referred Noise Current usingthe Optimum Device Size

IN-

IN+

RFB RFB

OUT-

OUT+

Lshunt 1 Lshunt 1

RD 1

Lseries 1

Lseries 1

Lshunt 2 Lshunt 2

RD 2

Lseries 2

Lseries 2

Lshunt 3Lshunt 3

RD 3

Lseries 3

Lseries 3

RD 1 RD 2 RD 3

M1 M1 M2 M2 M3 M3

Ibias 1 Ibias 2 Ibias 3

Voltage Gain Stage Output BufferTransimpedance Stage

Figure 5.21: 10 Gbps TIA Schematic


Table 5.2: 10 Gbps TIA Component Values

Transimpedance Stage Component ValuesComponent Lshunt 1 Lseries 1 RD 1 RFB M1 Ibias 1

Value 1.1 nH 2.2 nH 60 Ω 200 Ω 100 µm 24 mA

Voltage Gain Stage Component ValuesComponent Lshunt 2 Lseries 2 RD 2 M2 Ibias 2

Value 0.95 nH 1.9 nH 122 Ω 50 µm 12 mA

Output Buffer Stage Component ValuesComponent Lshunt 3 Lseries 3 RD 3 M3 Ibias 3

Value 0.44 nH 0.88 nH 72 Ω 87.5 µm 20 mA

to compensate for any series resistance in the inductor. Since this is the case, the

inductor should be designed with the smallest possible trace width in order to reduce

the overall size and parasitic capacitance. The minimum allowable trace width is

determined by the current density rules since the shunt inductor will be carrying the

DC bias current.

Square symmetrical spiral inductors are used for the series inductors. As shown

in Figure 5.22 b), symmetrical inductors use multiple cross-over points to create

a symmetrical structure. This means the parasitic capacitance is more balanced

between the two inputs than in a square spiral inductor. This makes more sense in

this situation because it doesn’t add more capacitance to one side of the π resonance

structure, shown in Figure 5.4, than the other.

Each of the inductors was first simulated using the ASITIC simulation software

in order to get a rough approximation of the required dimensions. The optimization

feature was used to find the optimum dimensions for maximum Q in the series induc-

tors. All of the inductors were then simulated using Agilent’s Momentum software

and adjusted accordingly.


Metal 5

Metal 6

a) b)

Figure 5.22: Monolithic Inductors a) Square Spiral Inductor b) Square SymmetricalInductor

5.3.5 Resistors

The load resistors in each stage are implemented in polysilicon over an n+ diffusion to

reduce the parasitic capacitance to the substrate. A blocking layer is used to prevent

the polysilicon from being doped which would reduce it’s resistivity. The undoped

polysilicon has a sheet resistance of approximately 290 Ω/.

The design rules require that each resistor have a minimum of 5 squares and a

minimum width of 2 µm in order to produce an accurate resistance. With a sheet

resistance of 290 Ω/, a 5 square resistor has a resistance of approximately 1.5 kΩ.

Unfortunately in order to make accurate small value resistors like the ones required

for this design, multiple 5 square resistors must be placed in parallel. This has the

undesired effect of increasing the parasitic capacitance of the resistors.


5.4 Simulation Results

The final 10 Gbps TIA was simulated with Agilent’s Advanced Design System (ADS)

using transistor models provided by the Taiwan Semiconductor Manufacturing Com-

pany (TSMC). A chip photo of the device is shown in Figure 5.23, and the final

layout is shown in Figure 5.24. The TIA has a total area of 1000 µm by 875 µm,

including the input and output pads. In order to account for the effects of the trans-

mission lines, pads, and inductors, Agilent’s Momentum simulator was used to do an

electromagnetic (EM) simulation of the top metal layer. Ports were added to each

inductor as well as the pads and at the ends of the co-planer waveguides. The active

components were then connected to the ports and a co-simulation was done.

1000 µm

875 µm

Figure 5.23: 10 Gpbs TIA Die Photo

In order to account for the effects of the photodiode, an ideal capacitance was


Figure 5.24: 10 Gbps TIA Chip Plot


added to the input of the TIA. A dummy capacitance was also added to the other

TIA input to maintain the symmetry of the differential circuit. Simulation results

are shown below in Figure 5.25.

109

1010

0

10

20

30

40

50

Frequency (Hz)

Tra

nsi

mp

edance

(dB

Ω)

CPD = 0 fFCPD = 250 fF

2 4 6 8 10 12 14 16 18 20−50

0

50

100

150

200

Frequency (GHz)

Gro

up

Del

ay

(ps)


(a) (b)

2 4 6 8 10 12 1420

30

40

50

60

70

80

90

100

Frequency (GHz)

Input

Ref

erre

dN

ois

eC

urr

ent

Den

sity

(pA√Hz)


(c)

Figure 5.25: Full Circuit Simulation a)Transimpedance Gain b) Group Delay c)InputReferred Noise Current Spectral Density

The transimpedance gain of the TIA is shown with and without a photodiode

capacitance of 250 fF. The TIA achieves a simulated transimpedance gain of 45 dBΩ.

Without the photodiode capacitance, the TIA achieves a transimpedance bandwidth

of approximately 12 GHz. Adding the photodiode capacitance decreases the band-

width of the TIA to approximately 6 GHz. Based on the analysis shown in sec-

tion 5.2.2, the bandwidth of this amplifier is higher than what is required for a


10 Gbps TIA. By tuning the inductors in the design, the peaking frequency could be

reduced to improve the performance with a higher photodiode capacitance.

Figure 5.25 b) shows the group delay for the TIA with and without the photodiode

capacitance. The group delay is flat except for the peak at approximately 11 GHz

created by the shunt-series inductive peaking. It was shown in section 5.2.2 that this

type of response produces acceptable eye patterns.

The input referred noise spectral density is shown in Figure 5.25 c). With the

photodiode connected the TIA shows an average input referred noise spectral density

of 30 pA/√

Hz over the bandwidth of the TIA.

5.4.1 Front-End Tuning

Adding an ideal capacitance at the input of the TIA to simulate the effects of the

photodiode is not entirely accurate for this circuit. In practice, the TIA is connected

to the photodiode with a wire-bond. At these high frequencies, this wire-bond can

have a significant effect on the performance of the system. In fact, if chosen properly,

the wire-bond can significantly improve the TIA performance. Figure 5.26 shows a

more realistic model of the circuit.

CBP

LBW

CBP

LBW

TIA

50Ω

50ΩCPD

Cdummy

IPD

Photodiode

Figure 5.26: 10 Gbps TIA with Front-End Tuning

The photodiode capacitance is separated from the TIA by a bond wire inductance.

The bond wire inductance provides series inductive peaking, and can extend the

bandwidth of the TIA. The bond wire also creates a filter at the input and reduces


the input referred noise current.

Figure 5.27 shows a simulation of the 10 Gbps TIA with a photodiode capacitance

of 250 fF and a bond wire inductance of 1 nH. The bond wire was given a series

resistance of 10 Ω to give it a more realistic Q value.

109

1010

−10

0

10

20

30

40

50

Frequency (Hz)

Tra

nsi

mp

edance

(dB

Ω)

2 4 6 8 10 12 14 16 18 20−50

0

50

100

150

200

250

300

350

Frequency (GHz)

Gro

up

Del

ay

(ps)

(a) (b)

2 4 6 8 10 12 1420

30

40

50

60

70

80

Frequency (GHz)

Input

Ref

erre

dN

ois

eC

urr

ent

Den

sity

(pA√Hz)

(c)

Figure 5.27: Full Circuit Simulation with Front-End Tuning a)Transimpedance Gainb) Group Delay c)Input Referred Noise Current Spectral Density

The simulation shows that the TIA bandwidth is improved to approximately

12 GHz, and the average input referred noise current density has been reduced to

approximately 22 pA/√

Hz.


5.5 Measured Results

5.5.1 Inductor Measurements

In order to evaluate the accuracy of the circuit modeling, test structures were created

on the chip to measure performance of various inductors used in the TIA. The mea-

sured results are compared to simulated results created using Agilent’s Momentum

EM simulator. Simulations were done on the entire test structure which includes

measurement pads and transmission lines. Figure 5.28 shows a comparison of the

measured and simulated results.

The measured inductance is consistently lower than the simulated value. In order

to remove the effects of the measurement pads, both the measured and simulated

results were de-embedded using measured open and short calibration structures.

This difference in inductance will change the resonance frequencies of the shunt-

series inductive peaking circuits. Equations 5.2 and 5.3 show the resonance fre-

quencies of the peaking circuit. With a decrease in the inductance, both resonance

frequencies will be increased. This will have an undesired effect on the circuit if

the resonance frequencies are raised too high. The input pole formed by the feed-

back resistance and the photodiode capacitance will determine the bandwidth of the

circuit.

5.5.2 Differential Measurements

Differential measurements for this TIA were not possible due to a stability problem

with the amplifier. As shown in Figure 5.29 the TIA oscillates at approximately

14.225 GHz with no input signal.

The stability of the amplifier can be analyzed using the following criteria shown

in [27]. The value of µ in equation 5.17 is the stability factor for the load, and the

value of µ′ is the stability factor for the source.


2 4 6 8 10 12 140.8

1

1.2

1.4

1.6

1.8

2

2.2

Frequency (GHz)

Induct

ance

(nH

)

Simulated − Test StructureMeasured − Test StructureSimulated − De−embeddedMeasured − De−embedded

2 4 6 8 10 12 141

1.5

2

2.5

3

3.5

Frequency (GHz)

Induct

ance

(nH

)


(a) (b)

2 4 6 8 10 12 14

0.8

1

1.2

1.4

1.6

1.8

2

Frequency (GHz)

Induct

ance

(nH

)


2 4 6 8 10 12 140

1

2

3

4

5

6

Frequency (GHz)

Induct

ance

(nH

)


(c) (d)

Figure 5.28: Inductor Test Structure Measurements a) 0.95 nH Square Inductor b)1.1 nH Square Inductor c) 0.88 nH Symmetrical Inductor d) 2.2 nHSymmetrical Inductor


14.2 14.21 14.22 14.23 14.24 14.25−120

−100

−80

−60

−40

−20

0

Frequency (GHz)

Outp

ut

Pow

er(d

Bm

)

Figure 5.29: 10 Gbps TIA Measured Output Spectrum

µ =|1 − S2

11||S22 − S∗

11∆| + |S12S21|(5.17)

µ′ =|1 − S2

22||S11 − S∗

22∆| + |S21S12|(5.18)

where ∆ = S11S22 − S12S21. The criteria for unconditional stability is that both µ

and µ′ be greater than 1.

Figure 5.30 shows the simulated source and load stability factors for the 10 Gbps

TIA. Both of the stability factors are greater than 1 which means the amplifier should

be unconditionally stable. This simulation however, only simulates the effects of

the top metal layer. Due to the large sizes of the inductors, the transistors in the

differential pair structures were separated by a distance that is larger than desired.

The sources of the differential pair transistors are connected on lower metal layers.

The effects of these connections were not considered in the initial simulation. Extra


0 5 10 15 201

2

3

4

5

6

7

8

Frequency (GHz)

Sta

bil

ity

Fact

or

SourceLoad

Figure 5.30: 10 Gbps TIA Load and Source Stability Factor

inductance in the sources of the transistors can cause instability. A second simulation

was done with the effects of these connections included. Figure 5.31 shows the new

source and load stability factors.

Since the stability factors are still above 1, the circuit is still theoretically uncon-

ditionally stable. However, if we compare the results in Figures 5.30 and 5.31, we can

see that modelling the source connections has reduced the stability of the circuit in

the area corresponding to the oscillation frequency.

The cause of the instability is most likely a combination of effects. There could

be coupling between the measurement probes, as well as effects from the rest of

the measurement setup. It was also shown in section 5.5.1 that the modeling of the

inductors was slightly off. This could also have an effect on the stability of the device.

This analysis however, shows that the stability of the device can be improved if the

transistors in the differential pairs are placed closer together.


0 5 10 15 201

2

3

4

5

6

7

8

Frequency (GHz)

Sta

bil

ity

Fact

or

SourceLoad

Figure 5.31: 10 Gbps TIA Load and Source Stability Factor with Source Connections

5.5.3 Single-Ended Measurements

Single-ended measurements were possible for the 10 Gbps TIA, since the TIA was

stable when measured single-ended. The single-ended measurements were taken by

leaving the second input and second output of the TIA open, and not matched with a

50 Ω load. The second side of the differential circuit was still biased and conducting

current. Single-ended measurements don’t show the true performance of the TIA,

but are able to offer some insight into the performance of the device. Figure 5.32

shows the measured transimpedance gain and group delay of the device.

The measured results are compared to results simulated single-ended. It can be

seen that the measured results show the peak resulting from the shunt-series peaking

circuit at a higher frequency. This is expected based on the inductor measurements

presented in section 5.5.1. The measured inductors showed less inductance than the

simulated inductors. This will result in an increase in the resonant frequencies in

the shunt-series inductive peaking circuit. The measured results also show a second

peak in the response at approximately 14.5 GHz. It is believed that this peak is a


2 4 6 8 10 12 14 16 18 20−10

0

10

20

30

40

50

Frequency (GHz)

Tra

nsi

mp

edance

(dB

Ω)

No Source ParasiticsWith Source ParasiticsMeasured

2 4 6 8 10 12 14 16 18 20−100

0

100

200

300

400

Frequency (GHz)

Gro

up

Del

ay

(ps)

No Source ParasiticsWith Source ParasiticsMeasured

(a) (b)

Figure 5.32: 10 Gbps TIA Single-ended Measurements a) Transimpedance Gain b)Group Delay

result of the connections between the transistors in the differential pairs. The plots

show results from the simulation done with and without the effects of these source

connections. A small peak in both the transimpedance and the group delay can be

found when the source connections are included in the simulation.

5.6 Conclusions

Several methods of inductive peaking have been explored in this chapter. Inductive

peaking can be used to extend the bandwidth of an amplifier by allowing an inductor

to resonate with the parasitic load capacitance of an amplifier. Series inductive peak-

ing, shunt inductive peaking, and shunt-series inductive peaking were all discussed

and the optimum component values were determined for optimally flat responses. It

was shown that shunt-series inductive peaking was able to substantially improve the

bandwidth of the TIA when compared to shunt or series peaking alone.

A 10 Gbps transimpedance amplifier has been designed using shunt-series induc-

tive peaking. The TIA uses a common source topology with shunt-shunt feedback

with shunt-series inductive peaking at the output. The amplifier has been designed


to be pseudo differential in order to improve the common mode rejection. This is

important because the intended application of the TIA is an integrated transceiver.

The differential structure will help reduce the impact of noise coupled into the TIA

from other system components.

Simulated results show a transimpedance gain of 45 dBΩ with a transimpedance

of 6 GHz with a 250 fF photodiode capacitance. Simulations also show that these

results could be improved by using the bond wire inductance between the photodiode

and the TIA to improve the performance. Simulation results show that a 12 GHz

bandwidth can be achieved using a 1.0 nH bond wire inductance. The bond wire can

also improve the noise performance. The average input referred noise current spectral

density is 22 pA/√

Hz for this amplifier using inductive front-end tuning.

Differential measured results are not available due to a stability problem in the

amplifier. A stability analysis is shown for the amplifier and it is suspected that the

cause the instability is the long connections between the transistors in the differential

pairs. Simulations show that the parasitics caused by these long connections reduce

the stability of the device. Measurements also show inaccuracies in the modeling of

the spiral inductors used in the TIA. This has caused a shift in the inductive peaking

frequency and may also be contributing to the stability problem.

Single-ended measurements have been presented for the TIA. These results clearly

show the shift in the peaking frequency due to the inaccuracies in the inductor models.

The simulated TIA performance is compared to previous work below in Table 5.3.

The transimpedance gain and transimpedance bandwidth compare well with previous

work. However, the average input referred noise current spectral density is higher than

previous reported results. One reason for the higher noise is the larger bandwidth

than required. The inductive peaking can be tuned to lower the bandwidth to around

7 to 9 GHz. This would allow the feedback resistance to be increased, and the noise

would be reduced. Also, further optimization using inductive front-end tuning should


be able to improve the noise performance.

Table 5.3: 10 Gbps TIA Performance Comparison

Technology ZT BW CP D Noise Supply Voltage Power Dissipation

Performance

[10] 0.25 µm CMOS 42.9 dBΩ 8.4 GHz - 14.6 pA/√

Hz 1.5 V 1.28 mW

[10] 47 GHz SiGe HBT 47.3 dBΩ 9.8 GHz - 12.0 pA/√

Hz 1.8 V 1.75 mW

[12] 0.13 µm CMOS 42 dBΩ 15 GHz 80 fF 225 µA p-p 2.0 V 9 mW

[17] 0.18 µm CMOS 61 dBΩ 7.2 GHz 250 fF 8.2 pA/√

Hz 1.8 V 70 mW

This Work 0.18 µm CMOS 45 dBΩ 12 GHz 250 fF 22 pA/√

Hz 2.8 V 100 mW

Chapter 6

Conclusions and Future Work

6.1 Conclusions

This thesis has examined the design of high speed transimpedance amplifiers in low

cost CMOS technology. Due to aggressive scaling, CMOS has become an attractive

technology for high speed analog circuits. Besides the cost advantage, CMOS offers

the potential for higher levels of integration since the analog circuits can be integrated

with digital electronics on the same substrate. This thesis focuses on the design of

transimpedance amplifiers intended to be used in integrated transceivers for a fiber

to the home application. A highly integrated solution using low-cost CMOS has the

potential to significantly reduce the system cost, which is important in this highly

cost sensitive area.

A 2.5 Gpbs transimpedance amplifier intended to meet the GPON specifications

has been presented. The TIA uses a shunt-shunt feedback topology with a cascode

gain stage. The cascode topology is used to reduce the input capacitance of the

amplifier and increase the bandwidth. The amplifier has been designed to be pseudo

differential in order to improve the common mode rejection. This is important because

the intended application of the TIA is an integrated transceiver. The differential

structure will help reduce the impact of noise coupled into the TIA from other system

114

CHAPTER 6. CONCLUSIONS AND FUTURE WORK 115

components. The TIA also has a variable gain to increase the range of acceptable

input powers such that the amplifier isn’t saturated.

Simulation results have been presented that show a maximum transimpedance

gain of 64 dBΩ and a transimpedance bandwidth of 1.8 GHz with a photodiode ca-

pacitance of 250 fF. The average input referred noise current spectral density over

the TIA bandwidth is 9.0 pA/√

Hz. Using the variable gain control the TIA tran-

simpedance gain can be reduced to 46 dBΩ. Measured results have also been presented

for the TIA and show a good match to simulated results. The S-parameters of the

differential circuit were measured to obtain the transimpedance gain, group delay

and common mode rejection ratio. The noise of the TIA was characterized by first

measuring the noise parameters of the TIA. The noise parameters are then used to

determine the input referred noise current spectral density.

The TIA performance is compared to other TIAs operating at similar bit rates, and

the transimpedance gain, and noise performance compare favourably with previous

work.

Next, a higher bit rate TIA has been explored. In order to increase the bandwidth

of the TIA, bandwidth extension techniques have been employed to counteract the

higher parasitics in CMOS technology. Several methods of inductive peaking have

been explored for this purpose. Inductive peaking can be used to extend the band-

width of an amplifier by allowing an inductor to resonate with the parasitic load

capacitance of an amplifier. Series inductive peaking, shunt inductive peaking, and

shunt-series inductive peaking have each been discussed and the optimum component

values were determined for optimally flat responses. It was shown that shunt-series

inductive peaking was able to substantially improve the bandwidth of the TIA when

compared to shunt or series peaking alone.

A 10 Gbps transimpedance amplifier has been presented using shunt-series induc-

tive peaking. The TIA uses a common source topology with shunt-shunt feedback


with shunt-series inductive peaking at the output. The amplifier has again been de-

signed to be pseudo differential in order to improve the common mode rejection. The

TIA circuit topology is optimized using a novel noise analysis using a high frequency

noise model for the transistor. The optimum transistor size and bias current are

determined to minimize the amplifier noise.

Simulated results show a transimpedance gain of 45 dBΩ with a transimpedance

of 6 GHz with a 250 fF photodiode capacitance. Simulations also show that these

results could be improved by using the bond wire inductance between the photodiode

and the TIA to improve the performance. Simulation results show that a 12 GHz

bandwidth can be achieved using a 1.0 nH bond wire inductance. The bond wire can

also improve the noise performance. The average input referred noise current spectral

density is 22 pA/√

Hz for this amplifier using inductive front-end tuning.

Differential measured results are not available due to a stability problem in the

amplifier. A stability analysis is shown for the amplifier and it is suspected that the

cause the instability is the long connections between the transistors in the differential

pairs. Simulations show that the parasitics caused by these long connections reduce

the stability of the device. Measurements also show inaccuracies in the modeling of

the spiral inductors used in the TIA. This has caused a shift in the inductive peaking

frequency and may also be contributing to the stability problem.

Single-ended measurements have been presented for the TIA. These results clearly

show the shift in the peaking frequency due to the inaccuracies in the inductor models.

6.2 Future Work

The work presented in this thesis offers opportunities for several areas of further study.

For the 2.5 Gbps TIA, future work includes wire-bonding the TIA to a photodiode

and producing eye diagrams for various input power levels. The TIA could also be

connected to a receiver and the system sensitivity could be confirmed by measuring


the BER directly.

For the 10 Gbps TIA, further work needs to be done to improve the modeling of

the spiral inductors. The performance of the TIA depends heavily upon the induc-

tors creating resonant structures with device parasitics to improve the bandwidth of

the system. Small deviations in the inductors have a significant effect on the TIA

performance.

Further work on the noise analysis can also be done that includes a model for

the bond wire. It has been shown that the bond wire has a significant effect on the

TIA bandwidth and noise performance. By optimizing the TIA performance with the

bond wire, better performance should be possible.

Another possible area of study would be to consider more complex types of induc-

tors for the 10 Gbps TIA. Since the Q factor of the shunt inductor is not important,

multilevel layer inductors could reduce the area of the TIA with little change in

performance.

References

[1] T. Koonen, “Fiber to the home/fiber to the premises: What, where, and when?”

vol. 94, no. 5, pp. 911–934, May 2006.

[2] B. Razavi, Design of Integrated Circuits for Optical Communications. McGraw-

Hill, 2003.

[3] R. G. Smith and S. D. Personick, Topics in Applied Physics - Receiver Design for

Optical Fiber Communication Systems, H. Kressel, Ed. Springer, 1982, vol. 39.

[4] S. M. Park and H.-J. Yoo, “1.25-Gb/s regulated cascode CMOS transimpedance

amplifier for gigabit ethernet applications,” IEEE J. Solid-State Circuits, vol. 39,

no. 1, pp. 112–121, January 2004.

[5] S. M. Park, J. Lee, and H.-J. Yoo, “1-Gb/s 80-dB fully differential CMOS tran-

simpedance amplifier in multichip on oxide technology for optical interconnects,”

IEEE J. Solid-State Circuits, vol. 39, no. 6, pp. 971–974, June 2004.

[6] S. M. Park and H.-J. Yoo, “2.5 Gbit/s CMOS transimpedance amplifier for

optical communication applications,” Electronics Letters, vol. 39, no. 2, pp. 211–

212, January 2003.

[7] W.-Z. Chen, Y.-L. Cheng, and D.-S. Lin, “A 1.8-V 10-Gb/s fully integrated

CMOS optical receiver analog front-end,” IEEE J. Solid-State Circuits, vol. 40,

no. 6, pp. 1388–1396, June 2005.

118

REFERENCES 119

[8] W.-Z. Chen and C.-H. Lu, “A 2.5 Gbps CMOS optical receiver analog front-

end,” in Proceedings of the IEEE 2002 Custom Integrated Circuits Conference,

May 2002, pp. 359–362.

[9] H.-Y. Hwang, J.-C. Chien, T.-Y. Chen, and L.-H. Lu, “A CMOS tunable tran-

simpedance amplifier,” IEEE Microwave Wireless Compon. Lett., vol. 16, no. 12,

pp. 693–695, December 2006.

[10] D. Guckenberger and K. Kornegay, “Novel low-voltage, low-power Gb/s tran-

simpedance amplifier architecture,” in Proceedings of SPIE, vol. 5117, 2003, pp.

274–285.

[11] D. Guckenberger, J. D. Schaub, and K. T. Kornegay, “A DC-coupled low-power

transimpedance amplifier architecture for Gb/s communication system applica-

tions,” in IEEE Radio Frequency Integrated Circuits Symposium, June 2004, pp.

515–518.

[12] C. Schow, L. Schares, R. John, L. Fischer, and D. Guckenberger, “25 Gbit/s

transimpedance amplifier in 0.13 µm CMOS,” Electronics Letters, vol. 42, no. 21,

pp. 1240– 1241, October 2006.

[13] L. Schares, C. L. Schow, S. J. Koester, G. Dehlinger, R. John, and F. E. Doany,

“A 17-Gb/s low-power optical receiver using a Ge-on-SOI photodiode with a

0.13-µm CMOS IC,” in Optical Fiber Communication Conference, 2006, March

2006, pp. 1–3.

[14] K. Schrdinger, J. Stimma, and M. Mauthe, “A fully integrated CMOS receiver

front-end for optic gigabit ethernet,” IEEE J. Solid-State Circuits, vol. 37, no. 7,

pp. 874–880, July 2002.

REFERENCES 120

[15] A. Tanabe, M. Soda, Y. Nakahara, T. Tamura, K. Yoshida, and A. Furukawa,

“A single-chip 2.4-Gb/s CMOS optical receiver IC with low substrate cross-

talk preamplifier,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 2148–2153,

December 1998.

[16] F. Beaudoin and M. N. El-Gamal, “A 5-Gbit/s CMOS optical receiver frontend,”

in The 2002 45th Midwest Symposium on Circuits and Systems, vol. 3, August

2002, pp. III–168 – III–171.

[17] C.-H. Wu, C.-H. Lee, W.-S. Chen, and S.-I. Liu, “CMOS wideband amplifiers

using multiple inductive-series peaking technique,” IEEE J. Solid-State Circuits,

vol. 40, no. 2, pp. 548–552, February 2005.

[18] S. S. Mohan, M. del Mar Hershenson, S. P. Boyd, and T. H. Lee, “Bandwidth

extension in CMOS with optimized on-chip inductors,” IEEE J. Solid-State Cir-

cuits, vol. 35, no. 3, pp. 346–355, March 2000.

[19] D. Guckenberger, J. D. Schaub, D. Kucharski, and K. T. Komegay, “1 V, 10 mW,

l0 Gb/s CMOS optical receiver front-end,” in IEEE Radio Frequency Integrated

Circuits Symposium, June 2005, pp. 309–312.

[20] M. Kossel, C. Menolfi, T. Mod, M. Schmatz, and T. Toifl, “Wideband CMOS

transimpedance amplifier,” Electronics Letters, vol. 39, no. 7, April 2003.

[21] S. Galal and B. Razavi, “40-Gb/s amplifier and ESD protection circuit in 0.18-µm

CMOS technology,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2389–2396,

December 2004.

[22] A. S. Sedra and K. C. Smith, Microelectronic Circuits, fourth edition ed. Oxford

University Press, 1998.

[23] Anritsu, “Application note: Three and four port S-parameter measurements,”

Anritsu, Tech. Rep., May 2002.

REFERENCES 121

[24] T. H. Lee, The Design of CMOS Radio-Frequency Integrated Circuits, second

edition ed. Cambridge University Press, 2004.

[25] K. B. Niclas, “Noise in broad-band GaAs MESFET amplifiers with parallel feed-

back,” IEEE Trans. Microwave Theory Tech., vol. 30, no. 1, pp. 63–70, January

1982.

[26] G. Gonzalez, Microwave Transistor Amplifiers Analysis and Design, second edi-

tion ed. Prentice Hall, 1997.

[27] M. L. Edwards and J. H. Sinsky, “A new criterion for linear 2-port stability

using geometrically derived parametes,” IEEE Trans. Microwave Theory Tech.,

vol. 40, no. 12, pp. 2303–2311, December 1992.

[28] M. Hossain, “A fully integrated K-Band receiver front-end in CMOS,” Master’s

thesis, Queen’s University, December 2004.

[29] R. LANE, “The determination of device noise parameters,” Proceedings of the

IEEE, vol. 57, no. 8, pp. 1461 – 1462, August 1969.

[30] E. W. Strid, “Measurement of losses in noise-matching networks,” IEEE Trans.

Microwave Theory Tech., vol. 29, no. 3, pp. 247–252, March 1981.

Appendix A

Noise Model Calculations

A.1 High Frequency Noise Model

The following high frequency noise model was developed in [28] for a common source

transistor. Figure A.1 shows the small circuit diagram used for the noise model.

This model is used in chapter 5 to optimize the transistor size to minimize the

noise of the 10 Gbps transimpedance amplifier.

CGS

CGD

idCDS

ri

gds

S

D

ig

Vgs

G RG

gmVgs

Figure A.1: High Frequency Noise Model

Using this model, the common source transistor can be modeled as a noisy two-

port network. In order to add the shunt-shunt feedback resistance to this model,

which we will show in the next section, we would like to represent the noise as shown

in Figure A.2. The common source transistor is modeled as a noiseless two port

network with the noise referred to the input.

122

APPENDIX A. NOISE MODEL CALCULATIONS 123

VN

IN

Noiseless

Network

Two-Port

Figure A.2: Noise Measurement Setup

Expressions for the noise sources are given below where k is the Boltzmann con-

stant, T0 is the temperature in degrees Kelvin, and ∆f is the noise bandwidth of the

device. Rn and Gn are defined as the equivalent noise resistance and conductance

respectively.

|VN |2 = 4kT0Rn∆f (A.1)

|IN |2 = 4kT0Gn∆f (A.2)

Expressions for Rn and Gn are given for the common source transistor in[28].

These expressions are given below. Further information on the derivation of these

parameters can be found in[28].

Rn = RG +RGδω2C2

G

5gdo

+γ

αgm

+ (RG + ri)2 ω2C2

Gγgdo

gm

+ 2RG|c|ω2C2

G

gm

√

δγ

5(A.3)

Gn =ω2C2

G

gm

(

δα

5+

γ

α+ 2

√

δγ

5

)

(A.4)

The correlation admittance Ycor is also given below in equation A.5. Ycor de-

scribes the correlation between the two noise sources VN and IN and is also needed

to determine the input referred noise current density of the TIA.


Ycor = Gcor + jBcor (A.5)

Gcor = RGω2C2G (A.6)

Bcor = ωCG

(

1 + α|c|√

δ

5γ

)

(A.7)

The next section will show how this model can be used to determine the noise

characteristics of a common source transistor with shunt-shunt feedback.

A.2 Common Source Transistor Model with Re-

sistive Feedback

The following analysis for determining the ABCD representation of a common source

transistor with shunt-shunt feedback is shown in [25]. In order to determine the

ABCD parameters for a common source transistor with shunt-shunt feedback, we will

first start with the equivalent circuit shown in Figure A.3. The equivalent circuit uses

the Y-parameter representation of the common source transistor [22] with the noise

sources referred to the input. The feedback network includes the feedback admittance

as well as a noise source.

Y12V2Y11 Y22 V2V1

YFB

I1 I2VN

IN

vFB

Y21(V1 − VN)

Figure A.3: Common Source Transistor with Feedback

We can solve for the currents I1 and I2 as follows:


I1 = (V1 − VN)Y11 + V2Y12 + (V1 − vFB − V2)YFB + IN (A.8)

I2 = V2Y22 + (V1 − VN)Y21 + (V2 + vFB − V1)YFB (A.9)

From these equations we can easily write the Y-parameter representation for the

entire circuit.

I1

I2

=

(Y11 + YFB) (Y12 − YFB)

(Y21 − YFB) (Y22 + YFB)

V1

V2

+

IN1

IN2

(A.10)

where,

IN1

IN2

=

IN − Y11VN − YFBvFB

−Y21VN + YFBvFB

We can now convert this Y-parameter representation into and ABCD parameter

representation so it can be used in cascaded circuits. In order to convert the noise to

an ABCD representation we can use the following expression.

VN

IN

=

0 B

1 D

IN1

IN2

(A.11)

The ABCD representation of the common source transistor with shunt-shunt feed-

back is given as follows.


V1

I1

= − 1

(Y21 − YFB)

(Y22 + YFB) 1

∆y (Y11 + YFB)

V2

−I2

+

V ′N

I ′N

(A.12)

where,

∆y = (Y22 + YFB)(Y11 + YFB) + (Y12 − YFB)(Y21 − YFB)

and,

V ′N

I ′N

=

Y21

(Y21−YFB)

(

VN − YFB

Y21vFB

)

YFB(Y11+Y21)(Y21−YFB)

(VN − vFB) + IN

In the 10 Gbps TIA described in chapter 5, the common source transistor with

shunt-shunt feedback is cascaded with a load resistor and a shunt peaking inductor.

Using this ABCD representation of the noise of the common source transistor with

shunt-shunt feedback, the total circuit performance can be determined.

A.3 Calculating Noise Parameters from ABCD Rep-

resentation

A model for the 10 Gbps TIA in chapter 5 is found using the ABCD representation of

a noisy two-port device. In order to calculate the input referred noise current density

of the device, as shown in equation 5.13, the following noise parameters need to be

determined from the ABCD representation.

Gu - Equivalent Noise Conductance of the Uncorrelated Noise Current



Ycor - Correlation Admittance

Figure A.4 shows the ABCD representation of a circuit with the noise sources

referred to the input. The following analysis will determine the noise parameters of

the circuit. This analysis has been shown in [25].

(Noiseless)

ABCDV2V1

I1 I2VN

IN

Figure A.4: ABCD Representation with Noise

The general form of the ABCD representation with noise is given below in equa-

tion A.13.

V1

I1

=

A B

C D

V2

−I2

+

VN

IN

(A.13)

We can first calculate the correlation impedance Ycor as follows. The noise source

IN can be split into the portion of the noise source that is correlated with the noise

source VN and the portion that is uncorrelated with the noise source VN .

IN = INu + INc (A.14)

The correlated portion of the noise current INc is related to the noise voltage VN

using the correlation admittance Ycor.


IN = INu + YcorVN (A.15)

If we multiply this expression in equation A.15 by V∗N we get the following ob-

serving that INuV ∗N = 0.

INV ∗N = Ycor|VN |2 (A.16)

Using this expression we can rearrange and find the following expression for the

correlation admittance in terms of the two noise sources.

Ycor =INV ∗

N

|VN |2(A.17)

Next we can find the equivalent noise conductance for the uncorrelated noise cur-

rent Gu. We first need to find an expression for |INu|2 the mean squared uncorrelated

noise current. In order to do this we can use the following identity.

|INu|2|VN |2 = |IN |2|VN |2 − |INV ∗N |2 (A.18)

We can now write the following

|INu|2 =|IN |2|VN |2 − |INV ∗

N |2|VN |2

(A.19)

We can now determine Gu using the following expression.

Gu =|INu|2

4kT0∆f(A.20)

The equivalent noise resistance Rn can be determined directly from the noise

voltage VN .


Rn =|VN |2

4kT0∆f(A.21)

Appendix B

Noise Measurements

B.1 Determining Device Noise Parameters

A linear noisy two-port network can be represented as a noiseless two-port with

external noise sources as long as the noise sources create the same noise voltages

at the terminals as the the internal noise sources. Figure B.1 below shows one such

representation with the noise sources referred to the input of the device. The two port

network is also shown connected to a source impedance YS. The noise contributed

by the source is shown as is.

YS

vn

in

Noiseless

Network

Two-Portis

Figure B.1: Noisy Two Port Network

Using this representation of the noise in a two-port network it can be shown that

the noise behaviour of a linear noisy two-port network can be characterized using the

four noise parameters given below:

130

APPENDIX B. NOISE MEASUREMENTS 131

Fmin - Minimum Noise Factor


Yopt =(Gopt + jBopt) - Optimum Source Admittance

Using these noise parameters the noise factor (F) can be determined for any source

impedance using the following equation [26].

F = Fmin +Rn

Gs

|Ys − Yopt|2 (B.1)

Traditionally, the noise parameters have been determined by altering the source

impedance until the minimum noise figure is found. A second measurement point

would be required to determine the equivalent noise resistance Rn. This process can

be tedious and inaccurate. More recent methods use a least squares fit to determine

the noise parameters. A minimum of four unique measurements are needed to solve

for the four real numbers (Fmin, Rn, Gopt, Bopt) in the noise parameters. Practically,

many more measurements can be made to produce an overdetermined system.

B.1.1 R. Q. Lane Method

The least squares fit method was first proposed by [29]. The form of equation B.1 is

changed such that it is linear with respect to four new parameters A, B, C, and D.

F = A + BGs +C + BB2

s + DBs

Gs

(B.2)

The four noise parameters can be determined in terms of the new parameters.


Fmin = A +√

4BC − D2 (B.3)

Rn = B (B.4)

Gopt =

√4BC − D2

2B(B.5)

Bopt =−D

2B(B.6)

Determining Fmin and Gopt requires the assumption that both values are positive

such that the appropriate roots can be selected.

We can rewrite equation B.2 as shown below

A + B

Gs +

B2s

Gs

+

C

Gs

+DBs

Gs

− F = 0 (B.7)

Using this expression we can write the following expression for the least squares

error for n measurements.

ε =1

2

n∑

i=1

Wi

[

A + B

Gi +

B2i

Gi

+

C

Gi

+DBi

Gi

− Fi

]2

(B.8)

where Gi and Bi are the measured source impedance, and Fi is the measured noise

factor at the corresponding source impedance.

A weighting factor Wi can be used if it is known that some measurements are

more or less accurate than others.

We now minimize the error term by setting the partial derivative with respect

to each parameter to zero. These four equations are then solved simultaneously to

determine the noise parameters of the system.


∂ε

∂A=

n∑

i=1

WiP = 0 (B.9)

∂ε

∂B=

n∑

i=1

Wi

(

Gi +B2

i

Gi

)

P = 0 (B.10)

∂ε

∂C=

n∑

i=1

Wi

P

Gi

= 0 (B.11)

∂ε

∂D=

n∑

i=1

Wi

Bi

Gi

P = 0 (B.12)

where,

P =

A + B

(

Gi +B2

i

Gi

)

+C

Gi

+DBi

Gi

− Fi

(B.13)

B.2 Noise Parameter Measurement Procedure

B.2.1 Measurement Setup

Figure B.2 shows the setup used to measure the noise parameters of the transimpedance

amplifiers in this thesis. The noise measurements were done on bare chips so wafer

probing was required. A waveguide slide screw tuner is used to present different

source impedances to the device under test (DUT). A bias network is required on

the output to block the DC component from entering the noise figure analyzer. A

low noise pre-amplifier has been added before the noise figure analyzer to drive down

the noise figure and decrease the measured noise figure uncertainty. The noise figure

analyzer is calibrated at the input of the pre-amplifier by connecting the noise source

directly to the input of the pre-amplifier before starting measurements.

B.2.2 Source Impedance Measurement

In order to determine the noise parameters using the procedure described in the

previous section, the source impedance presented to the DUT must be accurately


DUTNoise Figure

AnalyzerNoiseSource

Slide Screw

Tuner

Pre-AmpLow Noise

Bias Network

ΓS

Figure B.2: Noise Measurement Setup

measured. This poses a slight challenge when performing on wafer measurements.

The source impedance must be measured at the tip of the input probe to the DUT.

To perform this measurement, a second measurement probe was used. The VNA was

calibrated to the tip of this second probe, and the two probes were placed on a set

of reference pads such that they were connected together. This measurement setup

is shown below in figure B.3.

Probe 1

VectorNetworkAnalyzer

Slide Screw

TunerSourceNoise

CalibrationReference Plane

ΓS

Probe 2

Figure B.3: Source Impedance Measurement Setup

For improved accuracy, a wide variety of source impedances should be chosen such

that all areas of the smith chart are well covered. The tuning position of the slide

screw tuner is recorded for each source impedance such that it can be returned to

the same position during the noise figure measurement. The slide screw tuner uses

micrometer control to allow the tuner to be set accurately.

B.2.3 Noise Figure Measurement

In order to measure the noise figure, the measurement setup is returned to the setup

shown in figure B.2. The noise figure is recorded over the bandwidth of interest for


each of the pre-determined tuner positions. Averaging can be used to improve the

accuracy of the results.

B.2.4 Loss Compensation

Before the noise parameters can be calculated, the measured noise figure must be

adjusted to remove the effects of the measurement setup. The measurement setup in

figure B.2 can be simplified in terms of losses to the following block diagram shown in

figure B.4. The before DUT losses include the loss of the tuner, the wafer probe, and

any other cables and adapters between the noise source and the DUT. The after DUT

losses include the wafer probe, the output bias network and any cables and adapters.

Before DUTLoss Loss

After DUTDUTNoise Source Pre-Amplifier

ΓS 1 ΓOUT 1, ΓS 2 ΓOUT 2, ΓS 3 ΓOUT 3, ΓS 4

F1, Ga 1 F2, Ga 2 F3, Ga 3

Ftotal, Gtotal

Figure B.4: Loss Compensation

The total noise factor for cascaded stages is given by the following equation where

Fi is the noise factor of each stage, and Gi is the available power gain of each stage.

F = F1 +F2 − 1

G1+

F3 − 1

G1G2+ · · · (B.14)

In a perfectly matched system, the available power gain of each stage is equal to

|S21|2. However, since we are introducing significant mismatch by using the impedance

tuner we need to accurately calculate the available power gain for each stage [30]. The

available power gain is given by the following equation.

Ga =|S21|2(1 − |ΓS|2)

(1 − |ΓOUT |2)|1 − S11ΓS|2(B.15)


where,

ΓOUT = S22 +S21S12ΓS

1 − S11ΓS

(B.16)

In order to accurately calculate the available power gain for each of the networks,

the S-parameters for each device need to be measured. Preferably, components can

be measured together to reduce the measurement error. The measurement probes

however, cannot be measured individually so an approximation is required. The

input and output probes are measured back to back and they are assumed to have

the same response. The S-parameters for a single probe are calculated by solving for

the T-parameters of the probe. It is possible to solve for the T-parameters assuming

that the probes are the same and are reciprocal.

In order to determine the noise factor of the loss networks we can use the fact that

the noise factor of a passive two port is the factor by which the available power is

attenuated (i.e. Fi = 1/Ga i). Using this identity we can re-write the cascaded noise

factor equation for this network as follows.

F =1

Ga 1+

F2 − 1

Ga 1+

(1/Ga 3) − 1

Ga 1Ga 2(B.17)

We can rearrange this equation to solve for F2 which is the noise factor of the

DUT.

F2 = FGa 1 −(1 − Ga 3)

Ga 2Ga 3

(B.18)

transimpedance amplifier design using 0.18 µm cmos technology

Documents