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International Journal of Industrial Electronics and Electrical Engineering, ISSN: 2347-6982 Volume-2, Issue-9, Sept.-2014 Design of Low Power 4-Bit BCD Adder Using Reversible Gates 14 DESIGN OF LOW POWER 4-BIT BCD ADDER USING REVERSIBLE GATES 1 C.MOUNESH KUMAR, 2 M.SRINIVASULU, 3 S.AHMED BASHA, 4 K.SUVARNA, 5 H.DEVANNA 1 M.tech VLSISD student, SJCET, 2 Associate Professor ECE Dept, SJCET, 3 Assistant Professor ECE Dept SJCET, 4 Associate Professor ECE Dept, SJCET, 5 Associate Professor ECE Dept, SJCET E-mail: [email protected], [email protected], [email protected], [email protected], [email protected] Abstract- Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. The proposed BCD adder is efficient in terms of power dissipation. Various technologies are going to be used and respective power dissipation will be compared. Logic Gates such as AND, OR, NAND (Except NOT) gates are not reversible that is inputs cannot be recovered from the output. On the other hand, in Reversible Logic Gates inputs can be recovered completely from the output that is there is one to one mapping between inputs and outputs. Reversible logic gates use less power compared to classical gates and under ideal condition. Keywords- HNG, NG, RPS gate, BCD Adder. I. INTRODUCTION Reversible gates perform a logic computation without a loss of information. A revesible conventional BCD adder was implemented using HNG gates. In this project we implemented BCD Adder using RPS gates. This effects an improved reversible decimal adder with reduced logical complexity and number of garbage outputs. In this project the design of 4-bit BCD adder using reversible gates is done II. IMPLEMENTATION The implementation of BCD adder using RPS. In this totally 9 RPS gates with garbage outputs. The circuit generates a correction bit ‘L’ or Decimal C OUT L=C OUT +S 3 (S 1 +S 2 ) And total sum delay T sum-digit T dsum(conventional) =NT dcout +T sum-digit For 4 digit BCD adder the delay is 36 and N-digit BCD adder the delay is 9N. Proposed BCD adder Timing Diagram: Layout: Analog Simulation for CMOS 0.12µm Analog Simulation for CMOS 65nm

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Page 1: DESIGN OF LOW POWER 4-BIT BCD ADDER USING ...pep.ijieee.org.in/journal_pdf/11-79-140963286314-16.pdfconventional BCD adder using 70nm technology is International Journal of Industrial

International Journal of Industrial Electronics and Electrical Engineering, ISSN: 2347-6982 Volume-2, Issue-9, Sept.-2014

Design of Low Power 4-Bit BCD Adder Using Reversible Gates

DESIGN OF LOW POWER 4-BIT BCD ADDER USING REVERSIBLE GATES

1C.MOUNESH KUMAR, 2M.SRINIVASULU, 3S.AHMED BASHA, 4K.SUVARNA, 5H.DEVANNA

1M.tech VLSISD student, SJCET, 2Associate Professor ECE Dept, SJCET, 3Assistant Professor ECE Dept SJCET,

4Associate Professor ECE Dept, SJCET, 5Associate Professor ECE Dept, SJCET E-mail: [email protected], [email protected], [email protected], [email protected],

[email protected]

Abstract- Reversible logic is emerging as an important research area having its application in diverse fields such as low power CMOS design, digital signal processing, cryptography, quantum computing and optical information processing. The proposed BCD adder is efficient in terms of power dissipation. Various technologies are going to be used and respective power dissipation will be compared. Logic Gates such as AND, OR, NAND (Except NOT) gates are not reversible that is inputs cannot be recovered from the output. On the other hand, in Reversible Logic Gates inputs can be recovered completely from the output that is there is one to one mapping between inputs and outputs. Reversible logic gates use less power compared to classical gates and under ideal condition. Keywords- HNG, NG, RPS gate, BCD Adder. I. INTRODUCTION Reversible gates perform a logic computation without a loss of information. A revesible conventional BCD adder was implemented using HNG gates. In this project we implemented BCD Adder using RPS gates. This effects an improved reversible decimal adder with reduced logical complexity and number of garbage outputs. In this project the design of 4-bit BCD adder using reversible gates is done II. IMPLEMENTATION The implementation of BCD adder using RPS. In this totally 9 RPS gates with garbage outputs. The circuit generates a correction bit ‘L’ or Decimal COUT L=COUT+S3(S1+S2) And total sum delay Tsum-digit Tdsum(conventional)=NTdcout+Tsum-digit For 4 digit BCD adder the delay is 36 and N-digit BCD adder the delay is 9N. Proposed BCD adder

Timing Diagram:

Layout:

Analog Simulation for CMOS 0.12µm

Analog Simulation for CMOS 65nm

Page 2: DESIGN OF LOW POWER 4-BIT BCD ADDER USING ...pep.ijieee.org.in/journal_pdf/11-79-140963286314-16.pdfconventional BCD adder using 70nm technology is International Journal of Industrial

International Journal of Industrial Electronics and Electrical Engineering, ISSN: 2347-6982 Volume-2, Issue-9, Sept.-2014

Design of Low Power 4-Bit BCD Adder Using Reversible Gates

Analog Simulation for CMOS 70nm

BCD adder using RPS:

Timing Diagram:

Layout:

Analog Simulation for CMOS 0.12µm

Analog Simulation for CMOS 65nm

Analog Simulation for CMOS 70nm

RESULT TABLE

Sl.No

Technology

Voltage Vdd (V)

No. of metals

Power Dissipation BCD Adder

BCD adder using RPS

1 0.12µm

1.2 6 11.281µw

1.722mw

2 65nm 0.7 6 0.160mw

0.517mw

3 70nm 0.7 6 0.242mw

0.35mw

CONCLUSION From above result table, a conclusion is made that the conventional BCD adder using 70nm technology is

Page 3: DESIGN OF LOW POWER 4-BIT BCD ADDER USING ...pep.ijieee.org.in/journal_pdf/11-79-140963286314-16.pdfconventional BCD adder using 70nm technology is International Journal of Industrial

International Journal of Industrial Electronics and Electrical Engineering, ISSN: 2347-6982 Volume-2, Issue-9, Sept.-2014

Design of Low Power 4-Bit BCD Adder Using Reversible Gates

having low power dissipation when compared with other technologies. The BCD adder using RPS gates using 70nm technology is also having low power dissipation when compared with other technologies. Thus n this project low power conventional BCD adder and Low Power BCD adder are designed and implemented. FUTURE SCOPE High end technologies can be used for design and implementation of BCD Adder.

REFERENCES [1] Design of Compact Reversible Decimal Adder using RPS

Gates-Rekha K.James,K.Poulose Jacob [2] R.Landauer, “Irreversibility and Heat Generation in the

Computational Process”,IBM Journal of Research Development,pp.183-191,5,1961

[3] Md.Hafiz Hasan Babu and A.R. Chowdary,”Design of a

Reversible BCD addrer by using reversible 4-bit Parallel Adder”,VLSIDesign2005,pp.255-260,jan2005

[4] H.Thapliyal,S.Kotiyal and M.B.Srinivas,”Novel BCD Adders

and their reversible logic implementation for IEEE 754r format ”,19th VLSI Design2006,pp.387-392,jan2006

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New Majority Gate Based Parallel BCD Adder Designs for ... › files › base-papers › 2019 › vlsi › vlsi-3.pdf · BCD adder. As a result, we have reduced delay in the multi-digit

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Dhanalakshmi College of Engineering2. Design and implementation of 4 bit binary Adder/ Subtractor and BCD adder using IC 7483 3. Design and implementation of Multiplexer and De-multiplexer