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CPE 404: MODERN PROCESSOR ARCHITECTURE CATALOG DATA Instruction-, data-, and thread-level parallelism. Scalar and superscalar pipelines. Instruction and data flow techniques. Memory hierarchy. Input/Output subsystem. Advanced architectures. COREQUISITES AND PREREQUISITES Prerequisite: CpE 300 with a grade of C or better. Advanced Standing required. RELEVANT TEXTBOOKS John L. Hennessy, David A. Patterson. Computer Architecture: A Quantitative Approach, 4th ed. J. Shen, M. Lipasti, Modern Processor Design: Fundamentals of Superscalar Processors, McGraw-Hill, 2 nd ed. Coordinator Emma Regentova Instructors: Drs. Sarah Harris, Emma Regentova, Mei Yang Course Topics I. Instruction set architecture and processor performance. Parallelism of different granularity size (1 week) a. Instruction Set Architecture: CISC, RISC and VLIW architectures. b. Evaluation of processor performance and optimization pathways. c. Parallel processing and parallel architectures: classification and representatives. d. Instruction level parallelism (ILP), limitations of ILP. II. Pipelined processors. (6 weeks) a. Overview: instruction fetch, decoding, dispatching, execution, completion and retirement. b. Pipeline idealism; balancing pipeline stages; unifying instruction types. c. Program flow and control dependencies; scheduling; pipeline hazards, penalty cycles and data forwarding. d. Complier techniques; why RISC. e. Parallel, diversified and dynamic pipelines. f. Instruction Flow Techniques; branch prediction; speculation. g. Register Data Flow Techniques: register renaming, reservation station and reorder buffer, dynamic instruction scheduler. h. Memory Data Flow Techniques: ordering of memory accesses, load bypassing and load forwarding, speculative loads. i. Survey of Superscalar Processors and its limitations. III. Multiprocessors and Multithreading (4 weeks). a. Coarse-grain/fine-grain/simultaneous multithreading. b. Latency hiding

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Page 1: Department of Electrical and Computer Engineering ...ece.unlv.edu/docs/courses/CPE404.docx · Web view2. An ability to apply engineering design to produce solutions that meet specified

CPE 404: MODERN PROCESSOR ARCHITECTURE

CATALOG DATAInstruction-, data-, and thread-level parallelism. Scalar and superscalar pipelines. Instruction and data flow techniques. Memory hierarchy. Input/Output subsystem. Advanced architectures. COREQUISITES AND PREREQUISITESPrerequisite: CpE 300 with a grade of C or better. Advanced Standing required.

RELEVANT TEXTBOOKS John L. Hennessy, David A. Patterson. Computer Architecture: A Quantitative

Approach, 4th ed. J. Shen, M. Lipasti, Modern Processor Design: Fundamentals of Superscalar

Processors, McGraw-Hill, 2nd ed.

CoordinatorEmma RegentovaInstructors: Drs. Sarah Harris, Emma Regentova, Mei YangCourse TopicsI. Instruction set architecture and processor performance. Parallelism of different granularity size (1 week)a. Instruction Set Architecture: CISC, RISC and VLIW architectures.b. Evaluation of processor performance and optimization pathways.c. Parallel processing and parallel architectures: classification and representatives.d. Instruction level parallelism (ILP), limitations of ILP.II. Pipelined processors. (6 weeks)a. Overview: instruction fetch, decoding, dispatching, execution, completion and retirement.b. Pipeline idealism; balancing pipeline stages; unifying instruction types. c. Program flow and control dependencies; scheduling; pipeline hazards, penalty cycles and data forwarding. d. Complier techniques; why RISC.e. Parallel, diversified and dynamic pipelines.f. Instruction Flow Techniques; branch prediction; speculation.g. Register Data Flow Techniques: register renaming, reservation station and reorder buffer, dynamic instruction scheduler.h. Memory Data Flow Techniques: ordering of memory accesses, load bypassing and load forwarding, speculative loads.i. Survey of Superscalar Processors and its limitations.III. Multiprocessors and Multithreading (4 weeks).a. Coarse-grain/fine-grain/simultaneous multithreading. b. Latency hiding

Page 2: Department of Electrical and Computer Engineering ...ece.unlv.edu/docs/courses/CPE404.docx · Web view2. An ability to apply engineering design to produce solutions that meet specified

c. Synchronizing shared-memory threads: atomic operations and hardware techniques.d. Memory consistency and cache coherence; snooping and directory based cache coherence protocols.IV. Input/Output subsystem (2 weeks)

Course OutcomesUpon completion of this course, students should be able to:1. Design a pipelined architecture. Perform simulation and evaluate the performance.

Identify critical paths and optimize the design (1,6) [1,2]2. Design branch prediction unit (1,2). [1,2]3. Understand compiler tasks and optimization techniques, static/dynamic interface

(1,2,6) [1,2]4. Design, analyze and optimize caches of specified types (1,2,6). [1,2]5. Design and analyze memory subsystem and I/O (1,2,6) [1,2]6. Analyze multiprocessor systems (1,6). [1,2]7. Understand and analyze advanced architectures (1,6,4) [1,2]8. Present results of analysis and simulation (6,4) [1,2,3]ABET OUTCOMES1. An ability to identify, formulate, and solve complex engineering problems by applying principles of engineering, science, and mathematics2. An ability to apply engineering design to produce solutions that meet specified needs with consideration of public health, safety, and welfare, as well as global, cultural, social, environmental, and economic factors3. An ability to communicate effectively with a range of audiences4. An ability to recognize ethical and professional responsibilities in engineering situations and make informed judgments, which must consider the impact of engineering solutions in global, economic, environmental, and societal contexts5. An ability to function effectively on a team whose members together provide leadership, create a collaborative and inclusive environment, establish goals, plan tasks, and meet objectives6. An ability to develop and conduct appropriate experimentation, analyze and interpret data, and use engineering judgment to draw conclusions7. An ability to acquire and apply new knowledge as needed, using appropriate learning strategies.Computer UsageStudents use DLS, Simple Scalar and other simulators to analyze the system or a component performance. Students use HDL and CAD tools and platforms to design a component or a system.

Page 3: Department of Electrical and Computer Engineering ...ece.unlv.edu/docs/courses/CPE404.docx · Web view2. An ability to apply engineering design to produce solutions that meet specified

UULO Course Outcomes1. Intellectual Breadth and Lifelong Learning2. Inquiry and Critical Thinking3. Communication4. Global/Multicultural Knowledge and Awareness5. Citizenship and EthicsGradinCumulative: Based on homework, projects and exams.Course Syllabus Preparer and Date:Dr. Mei Yang, 10/26/2019