dehon-workshop fpt 2009 1 architecture of fpgas as future computing platforms (with workshop...

DeHon-Workshop FPT 2009

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Architecture of FPGAs as Future Computing Platforms

(with workshop discussion annotations)

André DeHon

[email protected]


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State of FPGAs


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Lattice quoting: iSuppli, “Competitive Landscaping Tool - Q1 2009,” March 6, 2009

State of FPGAs• Modest Market Share


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State of FPGAs

• Modest Market Share

• Growing starts– “Gartner reported that FPGAs now have a

30-to-1 edge over ASICs in design starts.” • EDN, March 2009


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State of FPGAs

• Modest Market Share

• Growing starts– Growing starts– But low total volume– Generally low-volume products

• Slow overall market growth


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State of FPGAs

• Modest Market Share• Growing starts

– Growing starts– But low total volume– Generally low-volume products

• Slow overall market growth• “Cool” kids are programming

– GPGPUs, Multicore


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Hand-me-Down

• Technology process– Designed for needs of processors, RAMs

• Programming– Verilog, VHDL design for fixed-function devices– C designed for ISA processors– CUDA design for GPUs

• Benchmarks– Toronto 20 (logic syntehsis)– Spec (processors)– LINPAK (supercomputers)


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This Session Considers

• What does the future look like?

• Does it have to be like the past?

• How impacted by silicon scaling?

• What will it take for FPGAs to take over?


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Session Outline

• FPGA– Weaknesses– Negative stereotypes

• Strength of Alternatives

• FPGA Strengths• Big challenges for

late silicon era

• How can alternatives lose?

• How can FPGAs win?

• Questions worth thinking about?– (research directions)

Interactive, opinions, consensus, tight time budget….


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Why do Today’s FPGAs Suck?

• Weaknesses [real and perceived]– Self-criticism

• Stereotypes– Catharsis

[Budget 3min]


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Why do Today’s FPGAs Suck?(from audience discussion)

• High power• Hard to program• High per part cost• Too slow• Low Utility (compared to

ASIC?)• Inefficient use of area• Tools suck

• Low Floating-Point performance

• Unpronounceable Acronym

• Unpredictable timing• Not reprogrammable• Poor man’s ASIC

replacement• Insecure


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Why do Today’s FPGAs Suck? (weaknesses [real and perceived])

• High learning curve (entry)• Hard to extract performance

– (master and repeat)

• Long tool times• No standards• Limited reuse, portability• No scalable design capture

– (must redesign)


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Negative Stereotypes

• Slow/expensive/power-hungry ASICs• Slow compared to processors• Only for prototyping

– "Real" designs on ASICs• Only for low-volume products

– Successful, high-volume designs use ASICs• Only for control and interfacing

– tech-support geek only; can't have starring role• HARDware emphasis on hard• Non-scalable solutions


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Strengths of Processors

[Budget 2min]


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Strengths of Processors (from audience discussion)

• Flexible• Scalable

– Backward compatible

• Ease of Reuse• Have ISA• Compiler Targetable• Fast Compile

• Good compilers• Good debug support

and visibility• Good abstractions

– E.g. unbounded memory

• Lots of programmers


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Strengths of Processors (single core)

• Preserve investment – Ride tech curve; old code runs faster

• Millions of programmers• Easy to program

– Invest in teaching everyone to program• Ubiquitous• Cheap• Volume shipped, easy to get hands on• Rich development tools, standards• Fast compilation• Fast enough to handle most real-time tasks today• General-purpose, can be programmed to do

“anything”


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Strengths of Multicore Processors

• Lower power per op than monolithic, insane-way superscalar

• Becoming ubiquitous– The anointed “wave” of the future

• Can reuse single-processor know-how


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Strengths of GPGPU

[Budget 2min]


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Strengths of GPGPU (from audience discussion)

• Higher compute density than processors• More power efficient than processors• Ubiquitous• Higher throughput than processors• Have standards, scalability• Efficient use of Instruction Memory• Good single-precision floating-point performance• High throughput I/O• Fast Tools• Good Visualization


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Strengths of GPGPU

• Greater computational throughput than processors– At least for single-precision floating-point

• Programmable• Easy to program data-parallel tasks• Shipping in 100s of millions• Easy add-ons, build out• Investment preserving


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Strengths of ASICs

[Budget 1min]


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Strengths of ASICs (from audience discussion)

• Low Cost (in volume)

• Low Power

• High Performance (on task)

• Fun

• Well-developed tool flow

• Compact


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Strengths of ASICs

• Get just what you need– Remove all that general-purpose overhead

• On task– Lower power– Higher computational density


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Strength of FPGAs

[Budget 2min]


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Strength of FPGAs (from audience discussion)

• Field Programmable = flexible and general-purpose – Future protecting

• Low NRE• High profit margins?• Customizable memory and I/O• Can tune to task• Allow reuse of hardware• Easier to debug than ASICs


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Strength of FPGAs

• Programmable

• Adapt to needs of computation

• High computational density

• High memory bandwidth

• ? Power


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Fundamental FPGA Characteristics

• Fine-grained building blocks– Compute– Memory– Interconnect

• Spatially distributed• Spatially configured

i.e. Array of 32-bit seq. processors is not an FPGA.

2-bit datapath array with random config read/write is.


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FPGA Strengths/WeaknessesFundamental to Architecture?

+ Programmable

+ Adapt to needs of computation

+ High compute density

+ High memory bandwidth

- High learning curve

- Hard to extract performance

- Long tool times

- Power hungry

- No standards; limit reuse, portable

- Non-scalable design capture[Budget 3min]


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FPGA Strengths/WeaknessesAccurate/Fundamental?

Property Accurate Fundamental

- High Power Compared to asic, yes

- Hard to Program Yes No

- High per part cost ?

- Too slow No*

- Low utilization Yes Yes

- Inefficient use of area ?

- Tools suck Yes No

- Low Floating-Point Performance No

- Not Reprogrammable No


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FPGA Strengths/WeaknessesAccurate/Fundamental?

Property Accurate Fundamental

- Unpredictable Timing Yes No

- Poor Man’s ASIC Yes No

- Insecure Yes No

+ Flexible, GP, future-preserving Yes Yes

+ Low NRE Yes Yes

+ Customizable memory and I/O Yes Yes

+ Can tune to task Yes Yes

+ Allow reuse of hardware Yes Yes

+ Easier to debug than ASICs Yes Yes


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FPGA Strengths/WeaknessesFundamental to Architecture?

+ Programmable yes

+ Adapt to needs of computation yes

+ High compute density yes

+ High memory bandwidth yes

- High learning curve no

- Hard to extract performance no

- Long tool times no

- Power hungry some

- No standards; limit reuse, portable no

- Non-scalable design capture no


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Big Challengesfor Late Silicon Era


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Big Challenges next 10 Years

[Budget 3min]


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Big Challenges next 10 Years (from audience discussion)

• Power Density

• Leakage

• Variability

• Good Tools – deal with device capacity

• Smaller packages ?

• Reliability


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Big Challenges

• Power– Can put more transistors on a chip than we

can operate

• Reliability– Cannot expect them all to work any more

• NRE– Can only afford very high volume parts

• Design Productivity– Bottleneck is human time to put all those

transistors to use


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Challenge: Power


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Origin of Power Challenge

• Limited capacity to remove heat– ~100W/cm2 force air– 1-10W/cm2 ambient

• Transistors per chip grow at Moore’s Law rate = (1/F)2

• Energy/transistor must decrease at this rate to keep constant

• E/tr CV2f– V scaling more slowly than F


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ITRS Vdd Scaling:V Scaling more slowly than F


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CV2 scaling from ITRS:More slowly than (1/F)2


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Origin of Power Challenge

• Transistors per chip grow at Moore’s Law rate = (1/F)2

• Energy/tr must decrease at this rate to keep constant

• E/tr CV2f


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Historical Power Scaling

[Horowitz et al. / IEDM 2005]


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Challenge: Reliability


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RelXLayer: August 200948

Reliability• Fewer dopants, atoms increasing Variation

– Must margin over wider range of devices

• Increasing Transistors / chip– More things to go wrong, sample extreme devices

• Decreasing critical charge– Increasing upset rates

• Decreasing opportunities for burnin– More devices fail in field

• Increasing wear-out effects– Shorter lifetime and/or larger margins


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• Margins growing due to increasing variation

• Fixed-function designs stuck with manufacturing delays

• System performance is the worst-case path– Leakage is worst-case devices

• More devicesMore pathsMore chances of bad paths

• Further limiting Vdd scaling

Variations

Pro

babi

lity

Dis

trib

utio

n

Delay

New

Old


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End of Energy Scaling?

[Bol et al., IEEE TR VLSI Sys 17(10):1508—1519]

Black nominalGrey with variation


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Power and Reliability

• Intersection is the challenge

• Push Vdd in opposite directions

• Both reach inflection points– From doesn’t matter – To major concern


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Challenge: NRE


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NRE Costs


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Economics

• Economics force fewer, more customizable chips– Mask costs approaching millions of dollars– Custom IC design NRE tens of millions of dollars

• Need market of hundreds of millions of dollars to recoup investment

• With fixed or slowly growing total IC industry revenues Number of unique chips must decrease

Forcing fewer,more customizablechips


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Challenge: Designer Productivity


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DOMAIN SPECIFIC

RTL

GATE

TRANSISTOR

BEHAVIORAL

Design Productivity by Approach

a

b

s

q0

1

d

clk

GATES/WEEK(Dataquest)

100 - 200

1K - 2K

2K - 10K

8K - 12K

10 - 20

Source: Keutzer (UCB EE 244)


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Productivity

• At 10K gates / week• 1M “gate” FPGA design

– 100 man weeks 2 man years!

• Yes, we can program the FPGA fast– …but still slow (expensive) to develop the

design

• Also holding back ASICs– Why FPGAs capacities are good enough


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Implications


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How can Processors Lose?

[Budget 2min]


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How can Processors Lose? (from audience discussion)

• Hard to program in multicore era• Genericpower problems• Single thread performance no longer scales• Yield (every transistor must work)• Hard to extract performance• Variabilityslow• Memory NRE ???• More reliant on OS?


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How can Processors Lose?

• Too much power– Little of their power goes into the actual

computation

• Reliability: too coarse-grained– Variability and power end beneficial scaling– No access to most advanced fabs

• Programmability (multicore)


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Pentium Pro Energy Breakdown

[Bose, Martinosi, Brooks / Sigmetrics 2001]


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Embedded Processor

[Dally et al. / Computer 2008]


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Energy

[Abnous et al, The Application of Programmable DSPs in Mobile Communications, Wiley, 2002, pp. 327-360 ]


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How can GPGPUs lose?

[Budget 2min]


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How can GPGPUs lose? (from audience discussion)

• SIMD too limiting

• Don’t run legacy ISA software

• Insufficient local memory

• Memory bandwidth bottleneck

• Yield (granularity)

• Insufficient Programmability


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How can GPGPUs lose?

• Too much power– Paying huge power for non-local memory

bandwidth

• Reliability: too coarse-grained– Variability and power end beneficial scaling– No access to most advanced fabs

• Limited programmability – Not solve enough problems well


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How can ASICs lose?

[Budget 1min]


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How can ASICs lose? (from audience discussion)

• Too expensive– NRE– Design Productivity

• Too long Time-To-Market

• Lack of programmability/flexibility Low Yield and product lifetime

• Tools expensive and hard to use


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How can ASICs lose?

• NRE too high– Mask costs– Working out manufacturing/reliability issues

• Design productivity– Cannot afford to design something large enough

to demand extra capacity

• Reliability: no opportunity for scaling– Variability and power end beneficial scaling– No access to most advanced fabs


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How can FPGAs win?

[Budget 3min]


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How can FPGAs win? (from audience discussion)

• Redundancy

• Better programming languages

• Late bindingmap around process variation

• Vendor neutrality

• Ready for a good model

• Share NRE


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How can FPGAs win? (1)

• Reliability: post-fab, fine-grained configurability gives access to better technology– Power win from smaller feature size– Power win from lower voltage operation– Discard little when units bad


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Fine-Grained Reconfiguration

• Selecting devicesrole mapping after fabrication is powerful.– Mitigation fabrication

statistics• Defects• variation

– Mitigate lifetimechanges

• FPGA-like architectures have a potential head-start over alternatives.


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• Programmable to be efficient in domains not supported by GPGPUs and Processors– Local, spatial interconnect– Low latency communications– Specialized functional units

• Examples:– Graph problems, network processing, cryptography– Vision?


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• Adaptable in system– Reliability: aging– Environment: temperature, upset rate– Application data set– Application computing needs


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• Power: fine-grained programmability minimizes what switches


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• Big enough

• Fast enough

• Think: Innovator’s Dilemma


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• Must address:– Designer productivity– Scaling– Reuse– Standards– Easy access to exploit strengths

High-Level Models and Architectures


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Patterns for Parallelism

SPMD(CUDA)Streaming

(SCORE)

Actor-Oriented(GraphStep)

CellularAutomata

Transactional

WorkFarm

Sequential Control(BSP)

SpecializedInterpreter

FPGAs can potentially support all…and can mix-and-match…


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Prognosis

• Architecturally -- alternatives will have to become more like FPGAs to survive.

• Software/model wise – FPGAs still have a lot to learn from alternatives.


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Questions to Think About

• In light of coming challenges, what are the big questions we should be thinking about in FPGA Architecture and Systems?– What should research be trying to answer?

[Budget 4min]


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Questions to Think About (from audience discussion)

• Design at higher abstraction levels• Design portability and scalability to future

chips• Solve parallel programming problem• Reduce CAD runtime

– Time to first run

• Lower designer expectations?– help understand TTM vs. performance tradeoffs– find favorable points on curve

• Exploit post-fab configuration


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Questions to Think About

• Granularity – Balance reliability and overhead– Avoid tradeoff?

• Compute models– Exploit strengths, ease design, scalability

• Simplify performance programming– Including low energy

• Flexibility metrics (value of fine-grained prog.)• Efficiency over range of environments • Adaptability


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Conclusions

• Coming challenges promise a shake-up– Power, reliability, NRE, design productivity

• Many effects point in the direction of FPGA architecture– Also suggest directions for FPGA evolution

• We are not doing a good job of making FPGA strengths accessible

• Must take an aggressive lead– Address weaknesses– Demonstrate FPGA readiness to address

challenges

dehon-workshop fpt 2009 1 architecture of fpgas as future computing platforms (with workshop...

Documents

dehonworkshop fpt

multicore slide

architecture of fpgas

todays fpgas suck

low total volume

lowvolume products successful

strengths of processors

slow low utility