dac architecture
DESCRIPTION
DAC Architecture. DAC Architecture. Nyquist DAC architectures Binary-weighted DAC Unit-element (thermometer-coded) DAC Segmented DAC Resistor-string, current-steering, charge-redistribution DACs Oversampling DAC Oversampling performed in digital domain (zero stuffing) - PowerPoint PPT PresentationTRANSCRIPT
– 1 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
DAC Architecture
DAC Architecture
– 2 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
• Nyquist DAC architectures– Binary-weighted DAC– Unit-element (thermometer-coded) DAC– Segmented DAC– Resistor-string, current-steering, charge-redistribution DACs
• Oversampling DAC– Oversampling performed in digital domain (zero stuffing)– Digital noise shaping (ΣΔ modulator)– 1-bit DAC can be used– Analog reconstruction/smoothing filter
– 3 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
Binary-Weighted DAC
Binary-Weighted CR DAC
– 4 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
• Binary-weighted capacitor array → most efficient architecture
• Bottom plate @ VR with bj = 1 and @ GND with bj = 0
Cu = unit capacitance
VX
2Cu Cu Cu8Cu 4Cu
VR
Vo
b3 b2 b1 b0
CP
Binary-Weighted CR DAC
– 5 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
• Cp → gain error (nonlinearity if Cp is nonlinear)
• INL and DNL limited by capacitor array mismatch
Ru
Np
N
1ju
jNjN
RN
1ju
jNup
N
1ju
jNjN
o
VC2C
C2b
VC2CC
C2b
V
N
1jj
j-NR
uN
p
uN
o 2
bV
C2C
C2V
VX
2Cu Cu Cu8Cu 4Cu
VR
Vo
b3 b2 b1 b0
CP
Stray-Insensitive CR DAC
– 6 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
VX
2Cu Cu
16Cu
8Cu 4Cu
VR
Vo
b3 b2 b1 b0
CP
A
N
1jj
j-NR
uu1N
pu
N
uN
o 2
bV
A
CC2CC2
C2V
Large A needed to attenuate summing-node charge sharing
MSB Transition
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Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
Largest DNL error occurs at the midpoint where MSB transitions, determined by the mismatch between the MSB capacitor and the rest of the array.
4
o R4
p 0 jj=1
CV 1000 V
C +C + C
1 2 3
o R4
p 0 jj=1
C C CV 0111 V
C +C + C
δC,CCCCC :Assume u3214
uu
oo
CδCC
CC
δC
1LSB1LSB0111V1000VDNL
Code 0111 Code 1000
Midpoint DNL
– 8 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
• δC > 0 results in positive DNL
• δC < 0 results in negative DNL or even nonmonotonicity
δC > 0 δC < 0
Di
Ao
00111 1000
+DNL
Di
Ao
00111 1000
-DNL
Output Glitches
– 9 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
• Glitches cause waveform distortion, spurs and elevated noise floors
• High-speed DAC output is often followed by a de-glitching SHA
• Cause: Signal and clock skew in circuits
• Especially severe at MSB transition where all bits are switching –
0111…111 →
1000…000Time
Vo
De-Glitching SHA
– 10 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
Time
Vo
DAC...
b1
bN
VoSHA
SHA output must be smooth (exponential settling can be viewed as pulse shaping → SHA BW does not have to be excessively large).
SHA samples the output of the DAC after it settles and then hold it for T, removing the glitching energy.
Frequency Response
– 11 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
f
|H(f)|
0 fs 2fs 3fs
SHA
ZOH
2ωT
2ωTsin
ejωH 2
ωTj
ZOH
3dB
SHA
ωωj1
1jωH
Binary-Weighted Current DAC
– 12 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
• Current switching is simple and fast
• Vo depends on Rout of current sources without op-amp
• INL and DNL depend on matching, not inherently monotonic
• Large component spread (2N-1:1)
VX
Vob3 b2 b1 b0 A
I/2 I/4 I/8 I/16
R
N
1jj
j-No 2
bIRV
R-2R DAC
– 13 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
• A binary-weighted current DAC
• Component spread greatly reduced (2:1)
N
1jj
j-No 2
bIRV
VX
Vob3 b2 b1 b0 A
R
R R R
2R 2R 2R 2R
I
2RI/2 I/4 I/8 I/16
– 14 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
Unit-Element DAC
Resistor-String DAC
– 15 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
• Simple, inherently monotonic → good DNL performance
• Complexity ↑ speed ↓ for large N, typically N ≤ 8 bits
VR
Vo
Vo
Di
0
b0 b0 b1 b1
1
2
3
Code-Dependent Ro
– 16 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
• Ro of ladder varies with signal (code)
• On-resistance of switches depend on tap voltage
t
Vo
VR
Vo
Ro
Di
b0 b0 b1 b1
Co
Signal-dependentRoCo causes HD
DNL
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Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
RN
1k
1j
1k
RN
1k
1j
1k
j VΔRNR
ΔRR1jV
R
RV
R+ΔRNR+ΔRN-1R+ΔR1 R+ΔR2
VR...
V1 V2 VN VN+1
RN
1k
2j
1k
1j- VΔRNR
ΔRR2jV
j 1 j 1R
j j-1 R RN
k1
j 1 RR Rj j j-1 DNL
R ΔR ΔRVV V V V
N NRNR ΔR
ΔR σV VDNL V V DNL 0, σ
N N R R
Rσ0,ΔR
INL
– 18 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
R2
N
jk
1j
1k
RRN
1k
1j
1k
RN
1k
1j
1k
j VRN
ΔR1jΔR1j-N
VN
1jV
ΔRNR
ΔRR1jV
R
RV
RR
j j R INL
σNVj -1INL V V INL 0, σ max
N N 2 R
j
j
22 2R
j R V R3 2
22 2R
V R2
j 1 N- j 1 σj 1V V , σ V
N N Rσ1 N N
σ max V , when j 14N R 2 2
INL and DNL of BW DAC
– 19 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
RINL
RDNL
σNINL 0, σ max
2 R
σDNL 0, σ max 2 INL N
R
A BW DAC is typically constructed using unit elements, the same way as that of a UE DAC, for good component matching accuracy.
Current-Steering DAC
– 20 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
• Fast, inherently monotonic → good DNL performance
• Complexity increases for large N, requires B2T decoder
Io
…… …
…
Binary-to-Thermometer Decoder
...b1 bN
I I I
Unit Current Cell
– 21 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
• 2N current cells typically decomposed into a (2N/2×2N/2) matrix
• Current source cascoded to improve accuracy (Ro effect)
• Coupled inverters improve synchronization of current switches
Io
ROW/COL Decoder
...
b1
bN
I
Φ
Φ
...
Sj Sj
– 22 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
Segmented DAC
BW vs. UE DACs
– 23 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
Binary-weighted DAC
• Pros– Min. # of switched elements– Simple and fast– Compact and efficient
• Cons– Large DNL and glitches– Monotonicity not guaranteed
• INL/DNL– INL(max) ≈ (√N/2)σ– DNL(max) ≈ 2*INL
Unit-element DAC
• Pros– Good DNL, small glitches– Linear glitch energy– Guaranteed monotonic
• Cons– Needs B2T decoder– complex for N ≥ 8
• INL/DNL– INL(max) ≈ (√N/2)σ– DNL(max) ≈ σ
Combine BW and UE architectures → Segmentation
Segmented DAC
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Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
0
VFS
…
Di
Vo
2N-10
LSB’s
MSB’s
• MSB DAC: M-bit UE DAC
• LSB DAC: L-bit BW DAC
• Resolution: N = M + L
• 2M+L switching elements
• Good DNL• Small glitches• Same INL as
BW or UE
Comparison
– 25 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
Example: N = 12, M = 8, L= 4, σ = 1%
Architecture σINL σDNL # of s.e.
Unit-element 0.32 LSB’s 0.01 LSB’s 2N = 4096
Binary-weighted 0.32 LSB’s 0.64 LSB’s N = 12
Segmented 0.32 LSB’s 0.06 LSB’s 2M+L = 260
Max. DNL error occurs at the transitions of MSB segments
Example: “8+2” Segmented Current DAC
– 26 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
Ref: C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6mm2,” IEEE Journal of Solid-State Circuits, vol. 33, pp. 1948-1958, issue 12, 1998.
MSB-DAC Biasing Scheme
– 27 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
Common-centroid global biasing + divided 4 quadrants of current cells
MSB-DAC Biasing Scheme
– 28 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
Randomization and Dummies
– 29 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
References
– 30 –
Data Converters DACProfessor Y. Chiu
EECT 7327Fall 2014
1. M. J. M. Pelgrom, JSSC, pp. 1347-1352, issue 6, 1990.
2. D. K. Su and B. A. Wooley, JSSC, pp. 1224-1233, issue 12, 1993.
3. C.-H. Lin and K. Bult, JSSC, pp. 1948-1958, issue 12, 1998.
4. K. Khanoyan, F. Behbahani, A. A. Abidi, VLSI, 1999, pp. 73-76.
5. K. Falakshahi, C.-K. Yang, B. A. Wooley, JSSC, pp. 607-615, issue 5, 1999.
6. G. A. M. Van Der Plas et al., JSSC, pp. 1708-1718, issue 12, 1999.
7. A. R. Bugeja and B.-S. Song, JSSC, pp. 1719-1732, issue 12, 1999.
8. A. R. Bugeja and B.-S. Song, JSSC, pp. 1841-1852, issue 12, 2000.
9. A. van den Bosch et al., JSSC, pp. 315-324, issue 3, 2001.