Spidergon STNoC : The technology that adds value to your System

Marcello Coppola

Hot Chips 22

Agenda

Setting the stage Overview on Spidergon STNoC Spidergon STNoC backbone User experience Communication Primitives & Services Spidergon STNoC today Conclusions

2

Hot Chips 22

3

Moore’s law in real life

1 algorithm

On-chip communication network

Heterogeneous multiprocessing

SW

HW

CPU

MEM BUS

Few applicationsPseudo static behavior

CPUCPU

MEMMEM

CPU

IP

MEM

CROSBAR

Middleware

Operating system

SW & HW multi -tasking

Memory hierarchy

ASIC

Single micprocessorSoC

CrossBar -based multiprocessorSoC

SW Configurable SoC platform

Infrastructure

1 application

Many applicationsDynamic behavior

Hot Chips 22

Multicore SoC architecture: 2004 vision

IOIOEmbeddedMem

EmbeddedMem

ExtMemCtrl

DSPDSPVLIW HW IPDSPHOSTCPU

Masters

HOSTCPU

DMA

SoC interconnectExtMemCtrl

VLIW DSP DSPProgrammableParallel Engine

HW IP

EmbeddedMem IO IO secondary

targetRegisters

interconnect

EmbeddedMem

EmbeddedMem

In packagememory

Slaves

towards….

Open Configurable Heterogeneous Mul t icore Platforms

Hot Chips 22

Agenda

Setting the stage Overview on Spidergon STNoC Spidergon STNoC backbone User experience Communication Primitives & Services Spidergon STNoC today Conclusions

5

Hot Chips 22

6

Spidergon STNoC at a glance

Best in class for multi-protocol support (AMBA, STBUS, custom)

Solving wire congestion and time closure problems without any area penalty

Reduce SoC NRE Several Innovative Services Configurable end extensible

technology Fully integrated with state-of-

the-art verification environment Allow post silicon re-

configurability by software

Hot Chips 22

7

Spidergon STNoC technology

Spidergon STNoC is set of CommunicationPrimitives and Services implemented on top of adistributed on-chip network (NoC backbone) thatconnects several components.

Communication Primitives

Spidergon STNoC Backbone

Read/Write

CacheCoherence

Platform Services

QoS

Security

Multi -paths

Power IOMMU

Virtual Channels

FaultTolerance

AXI4AXI3 STBus

SocketInteroperability

Hot Chips 22

Agenda

Setting the stage Overview on Spidergon STNoC Spidergon STNoC backbone User experience Communication Primitives & Services Spidergon STNoC today Conclusions

8

Hot Chips 22

Spidergon STNoC backbone

The on-chip network is based on 3 well-defined configurable components called:

• Network Interface• Router • Physical link

Hot Chips 22

Communication Primitives

• Natively support (without bridges) different socket protocols (AXI, STBUS, OCP, custom, etc.)

• Efficient upsize and downsize conversion

parallelwires

flits Router

parallelwires

Routerflits

AXI

NI

NIOCP

AXI

OCP

64 6432

128

64

128

Hot Chips 22

ni_i_top

shl_rsp

shl_req krn_req

krn_rsp

sl_us_itf

sl_ds_itf

emu_top

error_management_on

request path

response path

IP

protocolShell

Handshake IP protocol

Encodes IP protocol

Programming

Security access

ShellHandshake IP

protocol

Encodes IP protocol

Programming

Security access

KernelSSTNoCpacket

assembling

Frequency Conversion

Error/Power Management

KernelSSTNoCpacket

assembling

Frequency Conversion

Error/Power Management S

ST

NoC

Inte

rfac

eS

ST

NoC

Inte

rfac

e SSTNoC

packets

Err

or M

an.

Uni

tE

rror

Man

. U

nitIP

protocolShell

Handshake IP protocol

Encodes IP protocol

Programming

Security access

ShellHandshake IP

protocol

Encodes IP protocol

Programming

Security access

KernelSSTNoCpacket

assembling

Frequency Conversion

Error/Power Management

KernelSSTNoCpacket

assembling

Frequency Conversion

Error/Power Management S

ST

NoC

Inte

rfac

eS

ST

NoC

Inte

rfac

e SSTNoC

packets

Err

or M

an.

Uni

tE

rror

Man

. U

nit

Network Interface

Hot Chips 22

Network Interface Features

Data bus / flit Size Conversion Upsize Downsize No conversion

Frequency Conversion Gray counters (any even number

of FIFO locations) 2 to 4 Synch. Flip Flops

0 to 3 cycles configurable crossing latency

Store & Forward IP Prot to S-STNoC (packet,

chunk, msg) S-STNoC to IP prot (S-STNoC

packet)

Error Management Security Management Transaction ordering support Single/Multiple Target QoS

support Programming Unit

Routing (Dir1, Dir2, DestID fields) QoS FBA fields Security STBus T1 or APB interface

Hot Chips 22

Spidergon Router

The Router implements the network and the data link layers of the NoCprotocol, offering best effort and possible quality of service (QoS) in terms of both latency and throughput

It is responsible for the transmission of the flits

The router supports 2 Virtual Channels

13R

ight

72

3

2

2

flit

flit_id

val

credit

flit_dataflit_be

us_flit

0636471

Example 72-bit flit

2 flit_id_err

ROUTERLe

ft

Hierarchy

Across Networ

k Inte

rface

flit_id_atomic2 four_be

flit_id_3

Hot Chips 22

14

Spidergon STNoC request/response networks

Spidergon STNoC technology a llow s you to design

separated request / response netw orks

request & response switch Less wires per router

Initiators

Requestresponsenetwork

Targets Initiators

requestnetwork

Targets

responsenetwork

Initiators

Router Router Router

Hot Chips 22

Router Features

Each Link (L, R, A, NI, H), Port (DS, US), VN (VN1, VN2) is individually instantiable and configurable

Back routing support

Configurable flit size: flit payload size16/18, 32/36, 64/72, 128/144 bits, plus flit extra bits

Optional registers on credits

IB with/without bypass capability and Optional retiming stage: configurable crossing latency (1 cycle or 2 cycles)

Configurable Output Queue size: 0 –64 flits When zero, OQ is not instantiated

Configurable number of Output Queues to NI

QoS Support Configurable basic arbitration

scheme within a faction: LRU, RR, pk_priority

Configurable virtual channel arbitration scheme: LRU/RR, VN_priority (w/ & w/o lock packet)

Routing Unit support for hierarchical networks: H link is a gateway between 2 S-STNoC sub-networks

Routing Unit support for SpidergonRouting or Source Routing mechanisms

Hot Chips 22

16

Com posed by a set of wires, an upst ream logic and a

downst ream logic

Enable efficient physical im plem entat ion

Synchronous version, Adapt ive version

Opt im ized flow cont rol with vir tual channel support

Physical Link

Spidergoncomponent US DS

flit

flitID

validcredit

Spidergon

component

Fixed upstream

interface

Fixed downstream

interface

Hot Chips 22

17

GALS: some previous works

1. Pausible Clocking Yun (ICCAD-96); Villiger et al./ETH (ASYNC-03)

2. Latency-Insensitive Systems Carloni, Sangiovanni-Vincentelli et al. (ICCAD-99);

3. Static Scheduling Casu, Macchiarulo (DAC-04)

3. Fine-Grain Synchronous Handshaking Jacobsen et al./IBM (ASYNC-02)

Hot Chips 22

18

Shells (“speaking” the latency insensitive protocol)

Latency Insensitive Design (LTI) [ICCAD99]

Channels (short wires)

Channels (long wires)

P1

P2

P3

P4

P5

P6

P7

Pearls (synchronous IP cores)

Source: L. Carloni

Hot Chips 22

19

Shells (“speaking” the latency insensitive protocol)

Channels (short wires)Channels (long wires)

P1

P2

P3

P4

P5

P6

P7

Pearls (synchronous IP cores)

Latency Insensitive Design (LTI) [ICCAD99]

RS

RS

RS

RS

RS

RSRS

RS

Relay Stations

RS

Source: L. Carloni

Hot Chips 22

Adaptive Link

20

Different link configurations for different purposes

RelayStation: configuration used to break long link (backend oriented)

Alink with freq. conv: used to cross frequency domain

Alink with size conv: used to adapt flit size

Alink with volt. conv: used to support multiple voltage domain

dsusds

us dsds usfreq. conv

us dsds ussize conv

us dsds usVolt.conv

us

Hot Chips 22

Features and configurability Each VN (VN1, VN2) is individually

instantiable and configurable (both DS and US are activated on the selected VN)

Configurable flit size: flit payload size 16/18, 32/36, 64/72, 128/144 bits, plus flit extra bits

Optional registers on credits

IB with/without bypass capability and optional retiming stage: configurable crossing latency

Configurable virtual channel arbitration scheme: LRU/RR, VN_priority (w/ & w/o lock packet)

DS/US flit size conversion support (instantiates FIFOs)

Frequency conversion support (instantiates bisynchronous FIFOs)

When FIFOs on, can support Store&Forward: Per NoC packet Per NoC packet per flit threshold

Separate FIFOs for header and payloads: Optimized Header FIFO width Flexibility for advanced S&F control

Depending on traffic type, removes unnecessary Payload FIFO

NOTE: DS/US flit sizes cannot both be lower than header width

NOTE2: DS and US flit extra bits sizes cannot be random. Either they are zero (at least one of them) or they stay in the same ratio as DS and US flit payload sizes

NOTE3: four_be conversion/management not supported for flit payload size 16/18

Hot Chips 22

Agenda

Setting the stage Overview on Spidergon STNoC Spidergon STNoC backbone User experience Communication Primitives & Services Spidergon STNoC today Conclusions

22

Hot Chips 22

The User Experience

How a product behaves and is used by people in the real world

“every product that is used by someone has a user experience: newspapers, ketchup bottles, reclining armchairs, cardigan sweaters.” (Garrett, 2003)

User Experience the way people feel about it their pleasure and satisfaction when using it, looking at it, holding it, opening or closing it

Hot Chips 22

The best experience out of the box.

Multicore

On-demand accelerators

ConnectivityMemory CTRL

System Functions

On-Chip Network

Periperals

Video AudioImagingGraphics

Multicore

L2

Multicore

L2

Multicore

L2

Core

L1

PCIe

PHY

USB

PHY

MIPI

PHY

FeedbackAction

Hot Chips 22

Agenda

Setting the stage Overview on Spidergon STNoC Spidergon STNoC backbone User experience Communication Primitives & Services Spidergon STNoC today Conclusions

25

Hot Chips 22

26

Spidergon STNoC: the Software

A software Library (libstnoc) and set of device drivers to programme interconnection behaviour of SoC architecture and to take advantage of built-in NoC services (Power, QoS, Security, MMU, Diagnostic, etc.)

Hot Chips 22

Spidergon STNoC driver

The driver exposes in files the NoC configuration information (base address, routing type etc)

Routing, QoS, and security information Through writable files, writing to the files updates the

configuration registers Last Register status Possible destinations Alternative paths for source routing

Hot Chips 22

Spidergon STNoC Library: Libstnoc

Libstnoc provides a high level C API, abstracted from the details of register format

A simple interface to allow applications to optimize the NoC at any time for their requirements.

High level get and set functions for routing, QoS. Error handling/valid data checks before applying to the

registers. Higher level functionality: profile switching / requirements

based reprogramming of the NoC.

Libstnoc

Hot Chips 22

NoC aware applications on Android

The Conent Provider, provides access to STNoC functionality to the whole Java based Android Application Framework.

Possible Applications. GUI on-device debug interface for the NoC. Parameters adjustment when receiving a phone call,

in flight mode, in standby etc. Adjustments for performance or low power.

Hot Chips 22

Platform Services: An example

Communication Primitives

Spidergon STNoC Backbone

Read/Write

CacheCoherence

Platform Services

QoS

Security

Multi -paths

Power IOMMU

Virtual Channels

FaultTolerance

AXI4AXI3 STBus

SocketInteroperability

QoS

Hot Chips 22

Dynamic resource usages: the web browser

31

The Software Stack: An overview

STNoCDriver

Libstnoc

Hot Chips 22

Dynamic resource usages: face time

32

Hot Chips 22

Service: Programmable QoS

DMA

Video Core

Audio

S-STNoCGraphics

Peripherals

PCI

ethernet

43%

11%

16%

24%6%

Initiators

CPU DMAGraphics Video CoreAudio

Average DDR BWis 1GB/s

long devXxxRead (struct aiRecord *pai) {

if (pai->pact) [

return S_devXxx_OK; /* zero */

}

pai->pact = TRUE

devXxxBeginAsyncIO(pai->dpvt);

return S_devXxx_OK;

}

Hot Chips 22

Towards IPU

IPU = Interconnect Processing Unit IPU Services are implemented in hardware and/or

software Communication Primitives Low level Platform

Services

34

Source: Design of cost efficient Interconnect processing unit:Spidergon STNoC, ISBN: 9781420044713

Hot Chips 22

Agenda

Setting the stage Overview on Spidergon STNoC Spidergon STNoC backbone User experience Communication Primitives & Services Spidergon STNoC today Conclusions

35

Hot Chips 22

Where is Spidergon STNoC today?

Spidergon STNoC is not only a standard NoCtechnology but it is an innovative technology able to provide real product differentiation through a set of smart hardware/software software services

ST on-chip communication network strategy in following years in consumer, multimedia, mobile etc.

External company licensing (eg. STE)

36

Hot Chips 22

Spidergon in real SoC: The hybrid NoC

37

Hot Chips 22

38

For more info

Book published by CRC press Spidergon STNOC book ISBN: 9781420044713 Publication Date: September 2008

Web based info from European/Catrene funded projects 3DIM3 COMCAS MODERN SHAPES …..

Hot Chips 22

39