compact modeling of ldmos transistors for extreme ... · extreme environment analog circuit design...

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 6, JUNE 2010 1431

Compact Modeling of LDMOS Transistors forExtreme Environment Analog Circuit Design

Avinash S. Kashyap, Student Member, IEEE, H. Alan Mantooth, Fellow, IEEE,Tuan A. Vo, and Mohammad Mojarradi

Abstract—The cryogenic characterization (93 K/−180 ◦C to300 K/27 ◦C) and compact modeling of a high-voltage (HV)laterally diffused MOS (LDMOS) transistor that exhibits car-rier freeze-out are presented in this paper. Unlike low-voltageMOS devices, it was observed that HVMOS structures experiencefreeze-out effects at much higher temperatures, resulting in anoutput current roll-off beyond a transition temperature. Stan-dard compact models generally do not guarantee performancebelow 218 K (−55 ◦C), and freeze-out effects are certainly notincorporated in them. This causes the models to fail to track atlower temperatures, and designers relying on these models wouldbe misled. In this paper, the temperature-scaling equations ofthe MOS Model 20 LDMOS model are modified to reflect thedevice operation down to 93 K, which is sufficient for designingsensor interface circuitry for lunar applications. The model is thenvalidated against an LDMOS device designed by engineers at theJet Propulsion Laboratory, using the IBM SiGe 5AM process. Amodified parameter extraction procedure has also been developed.This generalized approach is compact model friendly and canalso be implemented for other standard models. Analog circuitsdesigned with this new model are currently being tested at theInternational Space Station.

Index Terms—Cryogenic, extreme environment, high-voltage(HV) MOSFET, impurity freeze-out, laterally diffused MOS(LDMOS), MOS Model 20 (MM20).

I. INTRODUCTION

ACCURATE temperature-scalable device models are thefirst steps toward designing extreme environment cir-

cuitry. Currently, designers utilize the standard models that areused to implement circuits in the range from 393 to 218 K(+120 ◦C to −55 ◦C). Such models are not sufficient forthis research effort, which aims to build high-voltage (HV)biasing circuits for sensor interface electronics that are to bedeployed in future lunar missions. These electronics are partof a remote health monitoring system-on-a-chip that monitorsthe conditions of surrounding key systems on a spacecraft [1].

Manuscript received October 15, 2009; revised March 1, 2010; acceptedMarch 5, 2010. Date of publication April 15, 2010; date of current versionMay 19, 2010. This work was supported by the National Aeronautics andSpace Administration under Grant NNL05AA37C. The review of this paperwas arranged by Editor M. A. Shibib.

A. S. Kashyap was with the University of Arkansas, Fayetteville, AR 72701USA. He is now with the General Electric Global Research Center, Niskayuna,NY, 12309 USA (e-mail: [email protected]).

H. A. Mantooth is with the University of Arkansas, Fayetteville, AR 72701USA (e-mail: [email protected]).

T. A. Vo and M. Mojarradi are with the Jet Propulsion Laboratory,Pasadena, CA 91109 USA (e-mail: [email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2010.2046073

This chip processes a wide variety of possible sensor inputsthrough an analog front end (Wheatstone bridge, variable-gain amplifier, filtering, and data conversion). The electronicsshould be capable of operating down to 93 K (−180 ◦C) sincethey will not be shielded by “warm electronic boxes,” whichis the current practice. This will greatly reduce the weight,volume, and power consumption, while improving the overallperformance and system reliability.

It would be erroneous to extrapolate the temperature scalingin standard models to such low cryogenic temperatures simplybecause the behavior at 93 K significantly deviates from whatwas observed at 218 K. One approach to address this problemis to use a standard model as an isothermal model by turn-ing off the temperature-dependent parameters and extractinga parameter set to fit at one single temperature. This can berepeated at various temperatures within the range. This binningmethod has many disadvantages: 1) effects such as self-heatingwill not be accounted for; 2) it may not be very accurate ifmany temperature points are not considered; 3) it cannot beused to design circuits that require a continuous replication ofthe device performance over the temperature range; 4) it wouldrequire greater time and effort for realizing the design; and5) the possibility of human errors increases as designers needto repeatedly switch between the various isothermal modelsused in their circuits depending on the temperature. It wouldtherefore be desirable to have one model (and, thereby, oneparameter set) that can accurately replicate the behavior of thedevice over the entire temperature range.

Section II describes the laterally diffused MOS (LDMOS)device used in the research effort and the results of the cryo-genic characterization, while in Section III, the physics behindthe various observations in the measured data are explained.Section IV describes the native MOS Model 20 (MM20)model from NXP Semiconductors and the shortcomings of itstemperature-scaling equations—which can be gauged from theresults of the isothermal parameter extraction. The newly de-veloped equations for the modified temperature-scaling modelalong with the model performance are presented in Section V,and Section VI 6 explains some of the salient points in themodified parameter extraction sequence.

II. LDMOS DEVICE AND CHARACTERIZATION

A. Structure

Traditionally, high-voltage (HV) operation has been real-ized in low-voltage (LV) processes using circuit techniques.

0018-9383/$26.00 © 2010 IEEE

1432 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 6, JUNE 2010

Fig. 1. Cross section of the LDMOS device designed by JPL using the IBM5AM BiCMOS technology (not to scale).

However, these techniques increase both the complexity of thecircuit and the power requirements. HV LDMOS devices makeit possible to integrate LV circuits with HV parts instead ofusing discrete devices. The cross section of the LDMOS deviceused in this research effort is shown in Fig. 1. The p-well bulk isdiffused from the source side under the gate forming a graded-channel region. The device has a gate length of 2 μm and awidth of 40.45 μm. To withstand the HVs between the sourceand drain, the lightly doped drift region is long (4.35 μm), andit comprises two different sections: 1) the thin-gate-oxide driftregion and 2) the thick-field-oxide drift region. The LDMOSdevice was implemented in IBM’s 5AM SiGe BiCMOS tech-nology [2] using custom layout techniques. Since the 5AMprocess is essentially for LV devices, the gate voltage of theLDMOS device is capped at a maximum of 3.3 V, while thedrain voltage could be 20 V or higher, depending on the lengthand doping of the drift region. As this is a nonstandard device,IBM does not provide models for it in the process design kit.

B. Operation

When the gate bias exceeds the threshold voltage of the de-vice, an inversion channel is created, and the carriers (electronsin this case) flow toward the lightly doped drift region. The gateextends over the drift region, as seen in Fig. 1. When a positivebias is applied on the gate, electrons in the n-type drift regionunder the thin gate oxide get attracted to the surface and forman accumulation layer there. This provides a continuity for theflow of electrons that originate in the inversion channel. Beyonda certain point in the thin-gate-oxide drift region, depletionoccurs and the accumulation layer vanishes. As a result, theelectrons are gradually spread into the bulk region of the driftarea. The electrons are spread over the entire drift region nearthe drain. The gate bias does not have much effect in controllingthese electrons flowing in the bulk as the field oxide is verythick compared to the thin-oxide region [3], [4]. One of the mostdistinguishing features of LDMOS devices is the presence ofthe quasi-saturation effect in the output characteristics. Quasi-saturation is manifested as the invariance of the drain currentwith increasing gate voltages, as seen in Fig. 2. This is attributedto velocity saturation [5], [6] happening in the lightly dopeddrift layer of the device. The input characteristics of the deviceacross the entire temperature range are shown in Fig. 3.

C. Cryogenic Characterization

The packaged device was placed in an environment chamberthat was fed with liquid nitrogen at 230 psi. This enabled the

Fig. 2. Output characteristics of the JPL LDMOS device at 300 K (Vgs

ranging from 0.7 to 3.1 V in steps of 0.2 V) clearly exhibiting the quasi-saturation effect for higher gate voltages.

Fig. 3. Input characteristics of the JPL LDMOS device from 300 to 93 K(at Vds = 0.1 V for all temperatures). The threshold voltage keeps increasingas the temperature decreases.

authors to characterize the device from 300 K down to 93 K.For measuring the dc and CV characteristics, a Keithley 4200[7] Semiconductor Characterization System was utilized. Thisguarantees high-resolution data that can be used for devicestudies and modeling. The device pins were connected to theexternal measurement system using BNC connectors.

All the necessary measurements such as input characteristicsat high and low drain voltages, output characteristics, andcapacitance measurements were performed from 300 to 93 Kin 20-K intervals [8]. The capacitance values (measured at1 MHz) were seen to negligibly vary with temperature. Theparasitic capacitances due to the package were characterizedusing calibration test structures included in the chip. Theywere then deembedded from the C–V measurements of thedevice.

KASHYAP et al.: LDMOS TRANSISTOR MODEL FOR EXTREME ENVIRONMENT CIRCUIT DESIGN 1433

Fig. 4. Output current in the saturation region (at Vds = 20 V) and the linearregion (at Vds = 1.5 V) for Vgs = 3.1 V.

III. LDMOS DEVICE PHYSICS DISCUSSION

The input characteristics of the device were along expectedlines—i.e., the threshold voltage kept increasing as the tem-perature decreased. Furthermore, as the temperature decreased,the drain current (in the output characteristics) increased, asis expected in a MOS device. However, when the temperaturewas reduced below 133 K, the output current started decreasing,as shown in Fig. 4. Such nonmonotonic behavior is extremelyrare in MOSFETs and even more so at the relatively highertemperatures shown here at which the current starts falling. Thedevice was packaged in the well-characterized 40-pin ceramicdual inline package from Kyocera [18]. The resistance asso-ciated with the package (wires, leads, etc.) was deembeddedfrom the measurements. The parasitic package resistance (withknown coefficients of temperature) linearly varies within thetemperature range of interest and does not contribute to thecurrent roll-off.

A. Self-Heating

One plausible explanation for the above observations, partic-ularly for an HV device is self-heating. However, self-heatingwas conclusively ruled out as a cause due to the followingreasons.

1) Self-heating is manifested only in the saturation regionof the output characteristics [9] when the higher currentcauses the device to heat up (due to local hot spots, devicedesign, etc). In this case, we see that the decrease incurrent is seen both in the linear and saturation regions(Fig. 4).

2) Devices that self-heat have the characteristic droopingcurves [9] in the saturation region, as seen in an unrelateddevice in Fig. 5 (topmost blue curve). However, in theLDMOS device at the Jet Propulsion Laboratory (JPL),

Fig. 5. Example of self-heating in an unrelated device (measured at roomtemperature). The topmost blue curve exhibits the typical droop indicating thepresence of self-heating. The brown curve is the same measurement performedin pulsed mode.

it is clear that the output characteristics do not droop(Fig. 2).

3) The device was initially measured using normal dcsweeps. The same measurements were then repeatedusing pulses (pulsewidth = 0.1 μs, and interval betweenpulses = 40 μs) instead of dc sources, which wouldeliminate any self-heating, if present. The current valuesmeasured through both techniques were the same, indi-cating the absence of self-heating. In Fig. 5, the browncurve shows the data when the measurement was pulsed,thereby isolating the self-heating phenomenon. No suchissue was encountered in the JPL LDMOS.

B. Carrier Freeze-Out

It is postulated that impurity carrier freeze-out is the phenom-enon that is causing the current to decrease at cryogenic temper-atures [8]. Ionization energy is an important parameter in theoperation of semiconductor devices. Dopants usually requiresome energy (usually thermal) to ionize and produce carriersin the semiconductor. If the temperature is too low, dopantswill not be sufficiently ionized, and there will be insufficientcarriers, leading to freeze-out. Si MOSFETs can operate to thelowest temperatures because the carriers needed for conductionin the channel can be ionized by an electric field from thegate, known as field-assisted impurity ionization [10], [11]. SiMOSFETs and CMOS circuits are often used at deep cryogenictemperatures, below the freeze-out of Si (< 40 K) [12].

However, in LDMOS devices, the gate’s electric field isshielded from the drift region, which is doped low (to increasebreakdown voltage) to begin with. This creates lower ionizationof carriers in the drift region as the temperature is decreased,and we can therefore see the current considerably decreasingafter a transition temperature. In Fig. 6, it is shown that lightlydoped regions experience freeze-out even at relatively highertemperatures compared to highly or moderately doped regions.


Fig. 6. Ionized carrier concentration versus temperature in semiconductors.The green portion is roughly considered the usable temperature range.

Therefore, the freeze-out begins in the drift layer of the device,and consequently, the output current keeps falling. There is arisk of these devices completely freezing-out in temperaturesthat normal MOSFETs continue to work. This fact has to beborne by circuit designers who use both LV and HV devices intheir design. While the LV devices would continue to functionas expected in low cryo temperatures, the HV devices wouldstart to freeze out, and this has to be reflected in the modelsfor an accurate reliable design. The transition temperature canpossibly be lowered by appropriate device design changes. Thefreeze-out effects are also manifested in the input characteris-tics as the apparent decrease in the current in strong inversionwhen the temperature decreases to low values (Fig. 3).

IV. TEMPERATURE SCALING IN MM20

MM20 [13] is a surface-potential-based model for asym-metric lateral MOS devices that can replicate the effects dueto the drift region without the necessity for a series externalresistor in a subcircuit configuration. MM20 was chosen forthis research project because it has been shown to successfullymodel HV LDMOS devices to a great level of accuracy [3].The equations and the source code were fairly mature, and themodel was available (in Verilog-A) for modifications at the timethis project began. Moreover, the temperature-scaling equationsare neatly decoupled from the core dc and CV model—whichmakes understanding and modifying the model easier.

To gauge the capability of the temperature scaling in theMM20 model, isothermal parameter extractions were per-formed for the LDMOS device from 300 to 93 K in steps of20 K. Self-heating was turned off in the model during thisprocess. Some representative fits obtained from the isothermalextractions can be seen in Fig. 7. The red dots are the measureddata, and the blue lines are the model. The gate voltage rangesfrom 0.7 to 3.1 V in steps of 0.4 V.

The parameter extraction was performed on the input(Id–Vgs) and output characteristics (Id–Vds) along with theoutput conductance (gds) for each temperature data point. Thecapacitance parameters were extracted before the dc extrac-tion was performed. The simulation results have an excellent

Fig. 7. Output characteristics of the device at 300 and 93 K after isothermalparameter extraction.

agreement with the data, including in the quasi-saturationregion—which is a very challenging area to model in LDMOSdevices.

One important point to be noted here is that the MM20measurement procedure (and, hence, the parameter extractionguide) provided by NXP Semiconductors is not directly ap-plicable to this device because of its unique specifications.For example, as per the MM20 manual [13], the IDVD mea-surement entails stepping the gate voltage from VT + 0.1 Vto VT + 3.1 V. For this device, it would not be feasible tostep the gate voltage up to ∼4 V when the maximum allowedgate voltage is only 3.3 V. Moreover, certain model parameterssuch as MEXP, MEXPD, CGSO, and CGDO were not includedin the extraction procedure. Therefore, changes are needed tobe made to the parameter extraction guide to accommodatethese requirements. At the end of the isothermal extractions, allthe extracted temperature-dependent parameters were plotted.Some of them include BET (gain factor of the channel regionat the reference temperature Tref ), BETACC (gain factor for theaccumulation layer in the drift region), RD (ON-resistance ofthe drift region), THE3 (mobility reduction coefficient in thechannel region due to the horizontal electric field caused byvelocity saturation), and PHIB (surface potential at the onsetof strong inversion in the channel region). These plots werethen superimposed with the same parameters calculated bythe temperature-scaling equations (Fig. 8). For instance, in thenative MM20 model, the temperature scaling of the parameterBET is given as a simple exponential [13], i.e.,

βT = βi · Trηβ (1)


Fig. 8. Comparison of isothermally extracted BET with BET calculated fromthe native MM20 model (self-heating turned off).

Fig. 9. Performance of the native MM20 model (using built-in temperature-scaling equations) at 93 K.

where βi is the BET extracted at Tref , ηβ (ETABET) is thetemperature scaling exponent (a parameter), and Tr is thenormalized temperature. It can clearly be seen in Fig. 8 thatthe native model would grossly overestimate the value of BETin lower cryogenic temperatures as it does not account for car-rier freeze-out. Similarly, overestimation (or underestimation)of the values are also observed with the other temperature-dependent parameters. In low cryo temperatures, since most ofthe processed parameter values are incorrect, the output currentis also erroneous, as seen in Fig. 9.

The above shortcomings clearly demonstrate the need forimproved temperature-scaling equations that would render themodel useful for circuit design in deep cryogenic temperatures.

V. MODEL ENHANCEMENT

“Physical” models (even though they have some arbitraryfitting coefficients) for impurity freeze-out are finite-elementbased and require at least a 1-D device simulator to predict theresults [15], [16]. This is not a practical solution for compactmodeling where speed and convergence are extremely impor-tant factors. Moreover, such numerical models require intimateknowledge of the process and materials used in the constructionof the device—information that is difficult to obtain from

the manufacturers. Therefore, temperature scaling in compactmodels is generally semiempirical.

In the MM20 model, the temperature-dependence equationsare decoupled from the core model. In other words, temperatureparameters and equations process those parameters that areused in the dc and ac model. For example, the simplifiedexpression for the channel region current is [13]

Ich =βT · Vint1

Fmob · (1 + θ3 · VDi)+ Gmin · k2

o · VDi (2)

Fmob =1 + θ1 · Vint2 + θ2 ·Vint3

ko. (3)

In the aforementioned equations, Gmin is a constant, pa-rameter ko (KO) is the body factor of the channel region,parameters θ1 (THE1) and θ2 (THE2) are mobility reductioncoefficients due to the vertical electrical field, and θ3 (THE3)is the mobility reduction coefficient due to the horizontal field.Vint1, Vint2, and Vint3 are internally calculated voltages. It canbe seen that temperature dependence is not directly imple-mented in the above equations. Only the parameters that areused in the core equations are made to track with temperature.Therefore, the model can suitably be enhanced for extremeenvironment operation by modifying the temperature-scalingequations of the parameters that track with temperature.

The native MM20 model has either linear or simple expo-nential functions to describe the trend of the variation of thetemperature-dependent parameters; which works down to about170 K for this device but fails below that. Freeze-out in compactmodeling terms can be visualized as the decrease in mobility(at inversion in channel and accumulation in the drift region)and the consequent increase in the drift resistance beyond thetransition temperature. Various mathematical functions wereevaluated to describe this nonmonotonic behavior. A modifiedform of the equation that defines the probability density func-tion (pdf) of the Gumbel distribution [14] was finally chosen asit can accurately replicate the behavior without any requirementfor piecewise relations or weighting functions. This will sim-plify both parameter extraction and model convergence. Sincea parameter’s value can be greater than one, the normalizationof the pdf is replaced by a user-defined parameter, as shown inthe following [(4) is for BET]:

βT =e−βtmp · e−e−βtmp

βmult(4)

βtmp =TA − TT

βi · βEXP. (5)

In the above equations, TA is the ambient temperature,and TT is the freeze-out transition temperature. The ETABETparameter in the native model has been replaced by twonew parameters—BETEXP (βEXP) and BETMULT (βMULT).BETEXP is defined as the scaling coefficient for BET, andBETMULT is the temperature exponent of BET. With thenew equation, BET varies with temperature, as shown inFig. 10. The incorporation of parameters such as the transi-tion temperature and the consequent nonmonotonic behaviorof the parameter provides a more physical meaning to thetemperature-scaling equations than what was present in the


Fig. 10. Comparison of some of the isothermally extracted parameters (blue) with the values calculated from the new T-scaling equations (red). Parameter valuescalculated from the native T-scaling equations in the MM20 model are shown in green.

native model. Equation (1) in the native model was then re-placed with the newly developed equations (4) and (5) and theirassociated parameters.

In a similar way, the temperature scaling of the drift regionresistance is also illustrated below. In the native model, the driftregion resistance is scaled as follows:

RDT= RD · TrηRD . (6)

This equation was then modified as:

RDT=

e−RDtmp · e−e−RDtmp

RDmult

+ RDmult (7)

RDtmp =TA − TT

RD · RDEXP

. (8)

The ETARD (ηRD) parameter in the native model is re-placed by RDEXP (the first-order scaling coefficient of RD)and RDMULT (the temperature exponent of RD). The results ofRD scaling and of some other representative parameters are alsoshown in Fig. 10. Note that the newly developed equations areable to replicate the temperature scaling of the parameters veryaccurately. The performance of the native temperature-scalingequations is also overlaid on the figures for comparison.

Other parameters such as PHIB had a linear variation overthe temperature range, and the built-in equations were thereforesufficient for lower cryo operation. The temperature-scalingequations of the native MM20 Verilog-A model were then re-placed with the newly developed equations using the ModLyngtool [17]. The new model has 12 new parameters for tem-perature dependence. This modified model was then compiledfor Spectre and simulated, the results of which can be seenin Fig. 11.

The model with the newly developed equations is extremelyaccurate (error <1%–2%) over the entire temperature range.As shown in Fig. 12, it also performs exceptionally well inthe subthreshold region (including back bias) and in the C–Vregimes (Figs. 13 and 14). There were no changes in the modelsimulation times or convergence properties. This model can beused to extend the temperature-scaling behavior until the devicefails (in both high- and low-temperature conditions).

VI. PARAMETER EXTRACTION

As previously mentioned in Section IV, the parameter ex-traction guide of the MM20 model is not directly applicable tothis device due to its unique specifications. For this particulardevice, since Vgs,max is only 3.3 V, there is significant overlapbetween the IDVD and IDVDH measurements. Therefore, only


Fig. 11. (Above) Output and (below) input characteristics of the LDMOS device from 300 to 93 K. The simulation is performed at different temperatures witha single set of parameters. For the output characteristics, Vgs ranges from 0.7 to 3.1 V in steps of 0.4 V, and the input characteristics were measured at a constantdrain voltage of 15 V.

Fig. 12. Subthreshold characteristics measured (red) and simulated (blue)with back bias ranging from 0 to −1 V and Vds = 0.1 V at 300 K.

one of these measurements was performed (with several Vgs

steps from the threshold voltage, VT to Vgs,max) from whichall the parameters related to the output characteristics wereextracted. The smoothing factor MEXP should also be extractedalong with the channel length modulation parameters (ALP andVP). A new step was then added to extract the gain parameter inaccumulation (BETACC) along with the drift region resistance(RD) and the smoothing factor for the linear to quasi-saturationregime (MEXPD) from the same measurement. The transitiontemperature when the output current starts rolling off has nowbeen added as a parameter for modeling LDMOS devices thatexperience freeze-out, and it has to accurately be measuredfrom the output characteristics.

Fig. 13. Cgs characteristics (red) measured and (blue) simulated at 93 K.

Once a complete set of parameters is extracted at roomtemperature, the relevant temperature-scaling parameters cannow be introduced in the same extraction procedures at differenttemperatures. Since the LDMOS temperature behavior is non-monotonic, greater accuracy can be achieved by using four ormore temperature points (i.e., at room temperature, at the upperbound temperature, at the transition temperature, and finally,one more data point below the transition temperature where thecurrent rolls off). For example, RDEXP and RDMULT shouldbe extracted from the step in which RD was extracted, bysimultaneously keeping RD constant at different temperatures.In other words, only by optimizing the temperature scalingfactors can the device be modeled at other temperatures too.Greater weight may be provided to the extraction at lowertemperatures for enhanced accuracy if the circuits designedwith the model are to be primarily used in deep cryogenic


Fig. 14. Cgd characteristics measured (red) and simulated (blue) at 93 K.

conditions. A global fine-tune may also be performed towardthe end of the extraction to the temperature-scaling parametersfor better optimization.

An alternate method would be to extract the dc and ac param-eters isothermally (as previously described) at four differenttemperatures—room temperature, upper bound, lower bound,and transition temperature. The base parameters are then fittedto the new scaling equation using an external program such asMATLAB to extract the temperature-scaling parameters. Thismethod is less automated, but it entails lower optimization timeand can therefore be used for quick turnarounds.

VII. SUMMARY

Cryogenic characterization has been performed on LDMOSdevices designed at JPL. The devices have exhibited an onset ofcarrier freeze-out and output current roll-off at relatively highertemperatures at which conventional MOSFETs normally work.This has been attributed to incomplete ionization at the driftregion due to low doping levels and shielding of the gate biasdue to the thick field oxide. The native temperature scalingequations of MM20 were not sufficient to replicate this effect.New temperature scaling equations have been developed so thatone set of parameters can encompass the operation for the entireoperational range, obviating the need for binned models. Thisis the first compact LDMOS model capable of operating atdeep cryogenic temperatures and replicating impurity freeze-out behavior. It was successfully used in designing and sim-ulating analog circuits that are currently being tested at theInternational Space Station for flight qualification and, in thefuture, would be used in lunar missions.

ACKNOWLEDGMENT

The authors would like to thank C. Moore, A. Keyes,M. Watson, M. Beatty, L. Nadeau of the National Aeronauticsand Space Administration, E. Kolawa of the Jet PropulsionLaboratory, and the IBM SiGe development group for theirsupport and the SiGe ETDP team for the many contributions,including B. Blalock, W. Johnson, R. Garbos, R. Berger,

F. Dai, G. Niu, L. Peltz, P. McCluskey, M. Alles, R. Reed,A. Joseph, C. Eckert, J. Holmes, and J. D. Cressler. The authorswould also like to thank NXP Semiconductors for providing theVerilog-A code of the MM20 model and Lynguent for providingModLyng.

REFERENCES

[1] R. Berger, R. Garbos, J. Cressler, M. Mojarradi, L. Peltz, B. Blalock,W. Johnson, G. Niu, F. Dai, H. A. Mantooth, J. Holmes, M. Alles, andP. McClusky, “Miniaturized data acquisition system for extreme tem-perature environments,” in Proc. IEEE Aerosp. Conf., Mar. 1–8, 2008,pp. 1–12.

[2] SiGe5AM Model Reference Guide, Sep. 2002.[3] A. C. T. Aarts and W. J. Kloosterman, “Compact modeling of high-voltage

LDMOS devices including quasi-saturation,” IEEE Trans. ElectronDevices, vol. 53, no. 4, pp. 897–902, Apr. 2006.

[4] C. Anghel, “High Voltage Device for Standard MOS Technologies—Characterisation and Modelling,” Ph.D. dissertation, EPFL Lausanne,Lausanne, Switzerland, 2004.

[5] M. N. Darwish, “Study of the Quasi-saturation effect in VDMOS transis-tors,” IEEE Trans. Electron Devices, vol. ED-33, no. 11, pp. 1710–1716,Nov. 1986.

[6] J. Evans and G. Amaratunga, “The behavior of very high current den-sity power MOSFETs,” IEEE Trans. Electron Devices, vol. 44, no. 7,pp. 1148–1153, Jul. 1997.

[7] Keithley 4200 Semiconductor Characterization System User Manual.[8] A. S. Kashyap, M. Mudholkar, H. A. Mantooth, T. Vo, and M. Mojarradi,

“Cryogenic characterization of lateral DMOS transistors for lunar appli-cations,” in Proc. IEEE Aerosp. Conf., Big Sky, MT, Mar. 2009, pp. 1–8.

[9] J. Jomaah, G. Ghibaudo, and F. Balestra, “Analysis and modeling of self-heating effects in thin-film SOI MOSFETs as a function of temperature,”Solid State Electron., vol. 38, no. 3, pp. 615–618, Mar. 1995.

[10] I. M. Hafez, G. Ghibaudo, F. Balestra, and M. Haond, “Impact of LDDstructures on the operation of silicon MOSFETs at low temperature,”Solid State Electron., vol. 38, no. 2, pp. 419–424, Feb. 1995.

[11] D. Foty, “Impurity ionization in MOSFETs at very low temperatures,”Cryogenics, vol. 30, no. 12, pp. 1056–1063, Dec. 1990.

[12] F. Balestra and G. Ghibaudo, Device and Circuit Cryogenic Operation forLow Temperature Electronics. Norwell, MA: Kluwer, 2001.

[13] A. C. T. Aarts, A. Tajic, and S. J. Sque, “MOS Model 20, Level 2002.2,”NXP Semiconductors, Eindhoven, The Netherlands, Unclassified Techni-cal Note, PR-TN-2005/00406, May 2009.

[14] M. Evans, N. Hastings, and B. Peacock, Statistical Distributions., 3rd ed.New York: Wiley-Interscience, 2000.

[15] A. Akturk, J. Allnutt, Z. Dilli, N. Goldsman, and M. Peckerar, “Devicemodeling at cryogenic temperatures: Effects of incomplete ionization,”IEEE Trans. Electron Devices, vol. 54, no. 11, pp. 2984–2990, Nov. 2007.

[16] A. Schenk, P. P. Altermatt, and B. Schmithusen, “Physical model ofincomplete ionization for silicon device simulation,” in Proc. SISPAD,2006, pp. 51–54.

[17] ModLyng is a registered trademark of Lynguent Inc., Portland, OR.[18] Kyocera Standard Specification for Multilayer Layer Dual In Line

Packages (AS-1001, Rev. C).

Avinash S. Kashyap (S’03) received the B. Tech.degree in electrical and electronics engineering fromthe University of Calicut, Thenjipalam, India, in2001 and the M.S. and Ph.D. degrees in electri-cal engineering from the University of Arkansas,Fayetteville, in 2005 and 2009, respectively.

He has interned with the Wide Bandgap ResearchGroup, Oak Ridge National Laboratory, Knoxville,TN, and the SPICE Modeling Group, National Semi-conductor, Santa Clara, CA. He is currently withthe Semiconductor Technology Laboratory, General

Electric Global Research Center, Niskayuna, NY. His research is primarilyfocused on modeling (compact and TCAD), characterization, and study ofvarious semiconductor devices in extreme environments.

Dr. Kashyap is a recipient of the Sam Walton Doctoral Academy Fellowshipand the William E. Clark Endowed Doctoral Fellowship.


H. Alan Mantooth (S’83–M’90–SM’97–F’09)received the B.S. and M.S. degrees in electricalengineering from the University of Arkansas,Fayetteville, in 1985 and 1987, respectively, andthe Ph.D. degree from the Georgia Institute ofTechnology, Atlanta, in 1990.

He joined Analogy in 1990, where he focusedon semiconductor device modeling and the researchand development of HDL-based modeling tools andtechniques. In addition to modeling, his interestsinclude analog and mixed-signal design, analysis,

and simulation. In 1998, he joined the faculty of the Department of ElectricalEngineering, University of Arkansas, where he is currently a Full Professor.

Dr. Mantooth is a Member of Tau Beta Pi, Eta Kappa Nu, and numerousother academic honor societies. He currently holds the 21st Century Chair inMixed-signal IC Design and CAD. He is the Executive Director for both theNational Center for Reliable Electric Power Transmission and the NationalScience Foundation Center for Grid-connected Advanced Power ElectronicSystems.

Tuan A. Vo received the B.S.E.E. degree fromCalifornia State University, Long Beach, in 1986.

He is a Senior Engineer with the Power andSensor Systems Section, Jet Propulsion Laboratory,Pasadena, CA. His work has been focused on theintegrated circuit and subsystem design for sensorand power management applications. Prior to joiningthe Jet Propulsion Laboratory, he had more than 20years of experience in CMOS process and devicedevelopment, product engineering development, andmixed-signal and mixed-voltage integrated circuit

design in the areas of sensor and printing at Xerox Microelectronics Center,El Segundo, CA, and Lockheed Martin Focalplane, Santa Barbara, CA. He isthe holder of 26 U.S. patents in areas of IC and subsystem designs.

Mohammad Mojarradi received the Ph.D. degreein electrical engineering from the University ofCalifornia, Los Angeles, in 1986.

He was an Associate Professor with WashingtonState University, Pullman, and the Manager of themixed-voltage/specialty integrated circuit group withthe Xerox Microelectronics Center, El Segundo, CA.He is currently the Supervisor for Advanced Instru-ment Electronic Group, Jet Propulsion Laboratory,Pasadena, CA. He is a specialist in integrated mixed-signal/mixed-voltage electronic sensors, microma-

chined interface circuits, and mixed-mode integrated circuit design. He hasmore than 25 years of combined industrial and academic experience in his field.His current work focuses on developing highly efficient integrated mixed-signalelectronics for sensors, actuators, and power management and distributionsystems for instruments for deep-space systems.

compact modeling of ldmos transistors for extreme ... · extreme environment analog circuit design...

Documents