clbs intro

7/23/2019 CLBs Intro

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CSET 4650CSET 4650Field Programmable Logic DevicesField Programmable Logic Devices

Dan SolarekDan Solarek

FPGA Logic CellsFPGA Logic Cells


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Field-Programmable Gate rra!sField-Programmable Gate rra!s

Xilinx FPGAs are based on Configurable Logic Blocks (CLBs)Xilinx FPGAs are based on Configurable Logic Blocks (CLBs)

More generally called logic cellsMore generally called logic cells

ProgrammableProgrammable

CLB CLB CLB CLBCLB CLB CLB







CLB

"#$ blocksnot s%o&n


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Programmable Logic CellsProgrammable Logic Cells

All FPGAs con!ain a basic "rogrammable logic cellAll FPGAs con!ain a basic "rogrammable logic cellre"lica!ed in a regular array across !#e c#i"re"lica!ed in a regular array across !#e c#i"

configurable logic block$ logic elemen!$ logic module$configurable logic block$ logic elemen!$ logic module$logic uni!$ logic array block$ %logic uni!$ logic array block$ %

many o!#er namesmany o!#er names

ere are !#ree differen! !y"es of basic logic cells'ere are !#ree differen! !y"es of basic logic cells'

mul!i"lexer basedmul!i"lexer based

looku" !able basedlooku" !able based

"rogrammable array logic (PALlike)"rogrammable array logic (PALlike)

e *ill focus on !#e firs! !*o !y"ese *ill focus on !#e firs! !*o !y"es


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Logic Cell ConsiderationsLogic Cell Considerations

,o* are func!ions im"lemen!ed-,o* are func!ions im"lemen!ed-

fixed func!ions (mani"ula!e in"u!s only)fixed func!ions (mani"ula!e in"u!s only)

"rogrammable func!ionali!y (in!erconnec! com"onen!s)"rogrammable func!ionali!y (in!erconnec! com"onen!s)

Coarsegrained logic cells'Coarsegrained logic cells'su""or! com"lex func!ions$ need fe*er blocks$ bu! !#eysu""or! com"lex func!ions$ need fe*er blocks$ bu! !#ey

are bigger so less of !#em on c#i"are bigger so less of !#em on c#i"

Finegrained logic cells'Finegrained logic cells'

su""or! sim"le func!ions$ need more blocks$ bu! !#ey aresu""or! sim"le func!ions$ need more blocks$ bu! !#ey are

smaller so more of !#em on c#i"smaller so more of !#em on c#i"


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Fine-Grained vers's Coarse-GrainedFine-Grained vers's Coarse-Grained

Finegrained FPGAs are o"!imi/ed !o im"lemen!Finegrained FPGAs are o"!imi/ed !o im"lemen!

glue logic and irregular s!ruc!ures suc# as s!a!eglue logic and irregular s!ruc!ures suc# as s!a!e

mac#inesmac#ines

0a!a "a!#s are usually a single bi!0a!a "a!#s are usually a single bi!can be considered bi!le1el FPGAscan be considered bi!le1el FPGAs

Finegrained arc#i!ec!ures are no! sui!able for *iderFinegrained arc#i!ec!ures are no! sui!able for *ider

da!a "a!#sda!a "a!#s

!#ey reuire lo!s of o1er#ead!#ey reuire lo!s of o1er#ead


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Fine-Grained vers's Coarse-GrainedFine-Grained vers's Coarse-Grained

4econfigurable com"u!ing s!resses coarsegrained4econfigurable com"u!ing s!resses coarsegrained

de1ices *i!# da!a "a!# *id!#s muc# #ig#er !#an onede1ices *i!# da!a "a!# *id!#s muc# #ig#er !#an one

bi!bi!

essen!ially *ordle1el FPGAsessen!ially *ordle1el FPGAsCoarsegrained reconfigurable FPGAs are es"eciallyCoarsegrained reconfigurable FPGAs are es"ecially

designed for reconfigurable com"u!ingdesigned for reconfigurable com"u!ing

5uc# arc#i!ec!ures "ro1ide o"era!or le1el func!ion5uc# arc#i!ec!ures "ro1ide o"era!or le1el func!ion

uni!s (CLBs) and *ordle1el da!a"a!#suni!s (CLBs) and *ordle1el da!a"a!#s

&y"ically$ a! leas! fourbi!s *ide&y"ically$ a! leas! fourbi!s *ide


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Logic Cell ConsiderationsLogic Cell Considerations

,o* many in"u!s-,o* many in"u!s-

,o* many func!ions-,o* many func!ions-

all func!ions ofall func!ions of nnin"u!s or elimina!e some combina!ions-in"u!s or elimina!e some combina!ions-

*#a! in"u!s go !o *#a! "ar!s of !#e logic cell-*#a! in"u!s go !o *#a! "ar!s of !#e logic cell-

Any s"eciali/ed logic-Any s"eciali/ed logic-

adder$ e!c7adder$ e!c7

#a! regis!er fea!ures-#a! regis!er fea!ures-

#en designing (or selec!ing) !#e !y"e of logic cell#en designing (or selec!ing) !#e !y"e of logic cell

for an FPGA$ some basic ues!ions are im"or!an!'for an FPGA$ some basic ues!ions are im"or!an!'


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Programmable Logic Cells( )e!sProgrammable Logic Cells( )e!s

#a! is "rogrammable-#a! is "rogrammable-

in"u! connec!ionsin"u! connec!ions

in!ernal func!ioning of cellin!ernal func!ioning of cell

bo!#bo!#

Coarsergrained !#an logic ga!esCoarsergrained !#an logic ga!es

!y"ically a! leas! + in"u!s!y"ically a! leas! + in"u!s

Generally includes a regis!er !o la!c# ou!"u!Generally includes a regis!er !o la!c# ou!"u!

for seuen!ial logic usefor seuen!ial logic useMay "ro1ide s"eciali/ed logicMay "ro1ide s"eciali/ed logic

e7g7$ an adder carry c#aine7g7$ an adder carry c#ain


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Logic Cells as *niversal LogicLogic Cells as *niversal Logic

Logic cells mus! be flexible$ able !o im"lemen! aLogic cells mus! be flexible$ able !o im"lemen! a

1arie!y of logic func!ions1arie!y of logic func!ions

is reuiremen! leads us !o consider a 1arie!y ofis reuiremen! leads us !o consider a 1arie!y of

:uni1ersal logic com"onen!s; as basic building:uni1ersal logic com"onen!s; as basic buildingblocksblocks

Mul!i"lexers (M


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=>

*niversal Logic Gate( +'lti,leer*niversal Logic Gate( +'lti,leer

NOT OR AND

+!o= Mul!i"lexer

? @ A5>5= B5>5= C5>5= 05>5=? @ A5>5= B5>5= C5>5= 05>5=


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==


An exam"le logic func!ion using !#e

Ac!el Logic Module (LM)

Connec! logic signals !o some or all of

!#e LM in"u!s$ !#e remaining in"u!s !o

00 (:=;) or GD0 (:>;)

is exam"le s#o*s !#e im"lemen!a!ion

of !#e fourin"u! combina!ional logic

func!ion'

F . /12 3 /1C2 3 DF . 1/ 3 D2 3 1/C 3 D2F . 1. 1FF3 13 1FF

F1

F2


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For !#ose of you a bi! rus!y *r! Boolean algebra'For !#ose of you a bi! rus!y *r! Boolean algebra'

F . /12 3 /1C2 3 D

F . /12 3 /1C2 3 DF . /12 3 /1C2 3 D/1 3 12

F . /12 3 /1C2 3 D1 3 D1

F . 1 3 1C 3 1D 3 1D

F . 1/ 3 D2 3 1/C 3 D2F . 1. 1FF3 13 1FF

Eam,le 'se o7 S%annon8sEam,le 'se o7 S%annon8s

e,ansion t%eoreme,ansion t%eorem


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2!o= Mul!i"lexer


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=+

-to- +*9 :;EEL-to- +*9 :;EEL

A 2'= M


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nti-7'se FPG Eam,lesnti-7'se FPG Eam,les

Families of FPGAs differ in'Families of FPGAs differ in'

"#ysical means of im"lemen!ing"#ysical means of im"lemen!ing

user "rogrammabili!y$user "rogrammabili!y$

arrangemen! of in!erconnec!ionarrangemen! of in!erconnec!ion

*ires$ and*ires$ and!#e basic func!ionali!y of !#e logic!#e basic func!ionali!y of !#e logic

blocksblocks

Mos! significan! difference is inMos! significan! difference is in

!#e me!#od for "ro1iding!#e me!#od for "ro1iding

flexible blocks and connec!ionflexible blocks and connec!ion


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ctel CT FPGsctel CT FPGs


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CT Sim,le Logic +od'leCT Sim,le Logic +od'le

e AC& = Logic Modulee AC& = Logic Module

(LM$ !#e Ac!el basic logic(LM$ !#e Ac!el basic logic

cell)cell)

!#ree 2!o= M


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An exam"le Ac!el LMAn exam"le Ac!el LM

im"lemen!a!ion using "assim"lemen!a!ion using "ass

!ransis!ors (*i!#ou! any!ransis!ors (*i!#ou! any

buffering)buffering)


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e AC& = Logic Module is

!*o func!ion *#eels$ an 4

ga!e$ and a 2'= MK5A

A=K5A

Eac# of !#e in"u!s (A>$ A=$ and

5A) may be A$ B$ >$ or =


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2>


Mul!i"lexerbased logic

module7

Logic func!ions im"lemen!ed

by in!erconnec!ing signals

from !#e rou!ing !racks !o !#eda!a in"u!s and selec! lines of

!#e mul!i"lexers7

n"u!s can also be !ied !o a

logical = or >$ since !#esesignals are al*ays a1ailable

in !#e rou!ing c#annel7


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2=


8 n"u! combina!ional

func!ion

6>2 "ossible combina!ional

func!ions

2!o= Mul!i"lexer

? @ A 5 B 5? @ A 5 B 5

A

B?

5


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m"lemen!a!ion of a !#reem"lemen!a!ion of a !#ree

in"u! AD0 ga!ein"u! AD0 ga!e


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m"lemen!a!ion of 54

La!c#

0

0

Logic +od'le( S-+od

5euen!ial Logic Module5euen!ial Logic Module


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CT and CT > Logic +od'les

e eui1alen! circui!e eui1alen! circui!

(*i!#ou! buffering) of(*i!#ou! buffering) of

!#e 5E (seuen!ial!#e 5E (seuen!ial

elemen!)elemen!)


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CT and CT > Logic +od'les

e 5E configured as ae 5E configured as a

"osi!i1eedge!riggered"osi!i1eedge!riggered

0 fli"flo"0 fli"flo"


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ctel Logic +od'le nal!sisctel Logic +od'le nal!sis

Ac!el uses a finegrain arc#i!ec!ure *#ic# allo*s you !o useAc!el uses a finegrain arc#i!ec!ure *#ic# allo*s you !o usealmos! all of !#e FPGAalmos! all of !#e FPGA

5yn!#esis can ma" logic efficien!ly !o a finegrain5yn!#esis can ma" logic efficien!ly !o a finegrainarc#i!ec!urearc#i!ec!ure

P#ysical symme!ry sim"lifies "laceandrou!e (s*a""ingP#ysical symme!ry sim"lifies "laceandrou!e (s*a""ingeui1alen! "ins on o""osi!e sides of !#e LM !o ease rou!ing)eui1alen! "ins on o""osi!e sides of !#e LM !o ease rou!ing)

Ma!c#ed !o small an!ifuse "rogramming !ec#nologyMa!c#ed !o small an!ifuse "rogramming !ec#nology

LMs balance efficiency of im"lemen!a!ion and efficiency ofLMs balance efficiency of im"lemen!a!ion and efficiency ofu!ili/a!ionu!ili/a!ion

A sim"le LM reduces "erformance$ bu! allo*s fas! and robus!A sim"le LM reduces "erformance$ bu! allo*s fas! and robus!"laceandrou!e"laceandrou!e


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ltera FLE9 0)ltera FLE9 0)

Al!era FLEX => BlockAl!era FLEX => Block

0iagram0iagram

e EAB is a block of

4AM *i!# regis!ers on !#e

in"u! and ou!"u! "or!s$ andis used !o im"lemen!

common ga!e array

func!ions7

e EAB is sui!able formul!i"liers$ 1ec!or scalars$

and error correc!ion

circui!s7

dedicated memor!


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2

Embedded rra! 1lock /E12Embedded rra! 1lock /E12

Memory block$ can be configured'Memory block$ can be configured'

2.3 x 8$ .=2 x +$ =>2+ x 2$ 2>+8 x =2.3 x 8$ .=2 x +$ =>2+ x 2$ 2>+8 x =


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Embedded ArrayEmbedded Array

BlockBlock

Logic func!ions areLogic func!ions are

im"lemen!ed byim"lemen!ed by"rogramming !#e"rogramming !#e

EAB *i!# a read onlyEAB *i!# a read only

"a!!ern during"a!!ern during

configura!ion$configura!ion$crea!ing a large L


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Logic Array Block

Eac# LAB consis!s of

eig#! LEs$ !#eir associa!ed

carry and cascade c#ains$LAB con!rol signals$ and

!#e LAB local

in!erconnec!7

e LAB "ro1ides !#ecoarsegrained s!ruc!ure !o

!#e Al!era arc#i!ec!ure


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Logic Elemen! (LE)

e LE is !#e smalles! uni! of

logic in !#e FLEX =>

arc#i!ec!ure

con!ains a fourin"u! L


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ltera FLE9 0) Famil!ltera FLE9 0) Famil!

FLEX => 0e1icesFLEX => 0e1ices


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ltera FLE9 0) Famil!ltera FLE9 0) Famil!

FLEX => 0e1ices (con!inued)FLEX => 0e1ices (con!inued)


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ltera FPG Famil! S'mmar!ltera FPG Famil! S'mmar!

Al!era Flex=>N=>EAl!era Flex=>N=>ELEs (Logic elemen!s) #a1e +in"u! L


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9ilin LC

Xilinx LCA (a !rademark$ deno!ing logic cell array)Xilinx LCA (a !rademark$ deno!ing logic cell array)

basic logic cells$ configurable logic blocks or CLBs $basic logic cells$ configurable logic blocks or CLBs $

are bigger and more com"lex !#an !#e Ac!el orare bigger and more com"lex !#an !#e Ac!el or

OuickLogic cells7OuickLogic cells7

e Xilinx CLBs con!ain bo!# combina!ional logice Xilinx CLBs con!ain bo!# combina!ional logic

and fli"flo"s7and fli"flo"s7

Coarsegrain arc#i!ec!ureCoarsegrain arc#i!ec!ure

Xilinx Ma!ure Produc!s' XC>>>$ XC+>>>$ XC.2>>Xilinx Ma!ure Produc!s' XC>>>$ XC+>>>$ XC.2>>


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S=+ 1ased Programmabilit!S=+ 1ased Programmabilit!

La!c#es are used !o'La!c#es are used !o'

make or break cross"oin!make or break cross"oin!

connec!ions in !#e in!erconnec!connec!ions in !#e in!erconnec!

define !#e func!ion of !#e logicdefine !#e func!ion of !#e logic

blocksblocks

se! user o"!ions'se! user o"!ions'*i!#in !#e logic blocks*i!#in !#e logic blocks

in !#e in"u!Nou!"u! blocksin !#e in"u!Nou!"u! blocks

global rese!Nclockglobal rese!Nclock

::Configura!ion bi! s!ream; can beConfigura!ion bi! s!ream; can be

loaded under user con!rolloaded under user con!rolAll la!c#es are s!rung !oge!#er in aAll la!c#es are s!rung !oge!#er in a

s#if! c#ains#if! c#ain


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Logic Look', TableLogic Look', Table

L


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(a) Circuit for a two-input LUT

x1

x2

f

0/1

0/1

0/1

0/1

0

0

1

1

0

1

0

1

1

0

0

1

x1 x2

(b) f1 x1x2 x1x2+=

f1

(c) Storage cell contents in the LUT

x1

x2

1

0

0

1

f1

T&o-"n,'t Look', Table

L


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f

0/1

0/1

0/1

0/1

0/1

0/1

0/1

0/1

x2

x3

x1

T%ree-"n,'t L*T

A sim"leA sim"leex!ension of !#eex!ension of !#e!*oin"u! L


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Out

D Q

Clock

Select

Flip-fopI1

I2

I3

L!"

"ncl'sion o7 a Fli,-Flo, &it% a L*T

A Fli"Flo" can be selec!ed for inclusion or no!A Fli"Flo" can be selec!ed for inclusion or no!

La!c#es !#e L


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+.

9ilin 9C>000 CL1

e block diagram fore block diagram foran XC>>> family CLBan XC>>> family CLBillus!ra!es all of !#eseillus!ra!es all of !#esefea!uresfea!ures

&o sim"lify !#e&o sim"lify !#ediagram$ "rogrammablediagram$ "rogrammableM


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+3

9ilin 9C>000 CL1

A 2bi! looku" !able ( L>> CLB'. CLB in"u!s (AE)$ and

2 fli"flo" ou!"u!s (OX and O?)

2 ou!"u!s from !#e L


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9ilin 9C>000 CL1


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9ilin 9C4000 Famil! CL1

e blocke block

diagram for !#ediagram for !#e

XC+>>> familyXC+>>> family

CLB is similarCLB is similar

!o !#a! of !#e!o !#a! of !#e

CLB of !#eCLB of !#e

XC>>>XC>>>

Carry logicCarry logic

connec!ionsconnec!ionss#o*ns#o*n


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9C4000 Logic 1lock9C4000 Logic 1lock

&*o fourin"u! L


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T&o 4-"n,'t F'nctionsT&o 4-"n,'t F'nctions


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.=

5-"n,'t F'nction5-"n,'t F'nction


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.2

CL1 *sed as =+CL1 *sed as =+


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9ilin 9C500 Famil!

Xilinx XC.2>> family Logic Cell (LC) and configurablelogic block (CLB)7


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9ilin 9C500 Famil!

Basic Cell is called aBasic Cell is called aLogic CellLogic Cell(LC) and is similar !o$ bu! sim"ler !#an$(LC) and is similar !o$ bu! sim"ler !#an$CLBs in o!#er Xilinx familiesCLBs in o!#er Xilinx families

&erm CLB is used #ere !o mean a grou" of + LCs (LC>LC)&erm CLB is used #ere !o mean a grou" of + LCs (LC>LC)


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..

9ilin S,artan Famil!9ilin S,artan Famil!

Memory 4esourcesMemory 4esources

N Connec!i1i!yN Connec!i1i!y

5ys!em Clock5ys!em Clock

Managemen!Managemen!0igi!al 0elay Lock0igi!al 0elay Lock

Loo"s (0LLs)Loo"s (0LLs)

Logic R 4ou!ingLogic R 4ou!ing

CLB


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.3

9ilin S,artan CL19ilin S,artan CL1

5"ar!anE CLB 5lice

!*o iden!ical slices in eac#

CLB

Eac# slice #as 2 L


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.6

9ilin S,artan CL19ilin S,artan CL1

Eac# slice con!ains !*o se!s of !#efollo*ing'

Fourin"u! L


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.8

9ilin ?irte-E CL19ilin ?irte-E CL1

&*o CLB :logic slices;


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9ilin L*Ts( Pros and Cons9ilin L*Ts( Pros and Cons


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clbs intro

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