chapter 30 manufacturing

7/24/2019 Chapter 30 manufacturing

1/85

2013 John Wiley & Sons, Inc. M P Groover, Principles of Modern Manfac!rin" #$e

P%'(SSI)G *

I)+(G%+(- 'I%'I+S

1. vervie/ of I' Processin"

2. Silicon Processin"

3. i!ho"raphy

. ayer Processes se in I' *arica!ion

#. In!e"ra!in" !he *arica!ion S!eps

. I' Pac4a"in"

5. 6ields in I' Processin"


2/85


In!e"ra!ed 'irci! 7I'8

collec!ion of elec!ronic devices sch as !ransis!ors,

diodes, and resis!ors !ha! have een farica!ed and

elec!rically in!raconnec!ed on!o a s9all fla! chip ofse9icondc!or 9a!erial

Silicon 7Si8 : 9os! /idely sed se9icondc!or

9a!erial for I's

ess co99on; "er9ani9 7Ge8 and "alli9arsenide 7Gas8


3/85


evels of In!e"ra!ion in

Microelec!ronics

In!e"ra!ion level )9er devices pproery lar"e scale in!e"ra!ion 7>SI8 10 10 1=?0s

l!ra lar"e scale in!e"ra!ion 7SI810 10 ? 1==0s

Gi"a scale in!e"ra!ion 7GSI8 10=: 1010 2000s


4/85


@IS+%6 *

I)+(G%+(- 'I%'I+S

-evelop9en! of radar i99edia!ely efore WWII 71=3=

A 1=#8

+ransis!or develop9en! Inven!ion of !he In!e"ra!ed 'irci! 7I'8 'o99ercial develop9en! if I's


5/85


vervie/ of I' +echnolo"y

n in!e"ra!ed circi! chip consis!s of hndreds,

!hosand, 9illions or illions of 9icroscopic elec!ronic

devices chipis a sBare or rec!an"lar fla! pla!e !ha! is

ao! 0.# 99 70.020 in8 !hic4 and !ypically # !o 2#

99 70.2 !o 1.0 in8 on a side

(ach elec!ronic device on !he chip srface consis!s ofsepara!e layers and re"ions /i!h differen! elec!rical

proper!ies co9ined !o perfor9 a par!iclar fnc!ion


6/85


'ross sec!ion of a !ransis!or in an in!e"ra!ed circi! :

fea!re siCes can e less !han 0 n9

I' +ransis!or


7/85


In!e"ra!ed

'irci!

@i"hly 9a"nified

i9a"e of an in!e"ra!ed

circi! 7pho!o cor!esyof In!el 'orpora!ion8


8/85


Pac4a"in" of I's

+o connec! !he I' !o !he o!side /orld, and !o pro!ec!

i! fro9 da9a"e, !he chip is a!!ached !o a lead fra9e

and encapsla!ed inside a si!ale pac4a"e +he pac4a"e is an enclosre, 9ade of plas!ic or

cera9ic, !ha! provides 9echanical and

environ9en!al pro!ec!ion for !he chip

+he pac4a"e incldes leads y /hich !he I' cane elec!rically connec!ed !o e


9/85


10/85


Processin" SeBence for

Silicon I's

1. Silicon processin" : sand is redced !o very pre

silicon and !hen shaped in!o /afers

2. I' farica!ion : processin" s!eps !ha! add, al!er,and re9ove !hin layers in selec!ed re"ions !o for9

elec!ronic devices 7planar process8

i!ho"raphy is sed !o define !he re"ions !o e

processed on /afer srface3. I' pac4a"in" : /afer is !es!ed, c! in!o individal

chips, and !he chips are pac4a"ed


11/85


718 Pre silicon is for9ed fro9 9ol!en s!a!e in!o in"o! and

!hen sliced in!o /afersD 728 farica!ion of in!e"ra!ed circi!s

on /aferD and 738 /afer is c! in!o chips and pac4a"ed

SeBence in I' Processin"


12/85


'lean %oo9s

Mch of !he processin" of I's 9s! e carried o! in

a clean roo9

9iance of a clean roo9 is 9ore li4e a hospi!alopera!in" roo9 !han a prodc!ion fac!ory

'leanliness is dic!a!ed y !he 9icroscopic fea!re

siCes in an I', !he scale of /hich con!ines !o

decrease each year


13/85


lso sho/n is !hesiCe of co99onairorne par!icles!ha! cancon!a9ina!e !heI' processin"environ9en!

+rends in I' *ea!re SiCe


14/85


Pro"ress of

9inia!risa!ion, and

co9parison of siCes

of se9icondc!or

9anfac!rin"process nodes /i!h

so9e 9icroscopic

oEec!s and visile

li"h! /avelen"!hs

7see

h!!ps;$$en./i4ipedia.or"$/i4i$Se9icondc!o

rFdeviceFfarica!ion8

Red light (700 nm wavelength

Violet light (400 nm wavelength

Staphylococcusaureus bacterium

Spermatozoonhead

Red blood cellcross-section

uman immuno-de!ciency virus ("V)

10 m (1971) e.g. Intel 8008

3 m (1975) e.g. Intel 8088

1.5 m (1982) e.g. Intel 80286

1 m (1985) e.g. Intel 80386800 nm (1989) e.g. P5 Pentium 60 MHz

600 nm (1994) e.g. Motorola PoerP! 601

350 nm (1995) e.g. Pentium II "lamat#

250 nm (1998) e.g. $M% "6&2

180 nm (1999) e.g. !o''ermine

130 nm (2000) e.g. PoerP! 7447

90 nm (2002) e.g. I$ !7

65 nm (2006) e.g. !ore %uo

45 nm (2008) e.g. !ore 2 (*ol+,

32 nm (2010) e.g. !ore i3 (!l

22 nm (2011) e.g. eon 3&

16 nm (.2013)

11 nm (.2015)

0.5 m


15/85


Silicon Processin"

Microelec!ronic chips are farica!ed on a ss!ra!e of

se9icondc!or 9a!erial

Silicon accon!s for 9ore !han =# of allse9icondc!or devices prodced in !he /orld !oday

Prepara!ion of silicon ss!ra!e 7/afers8 can e

divided in!o !hree s!eps;

1. Prodc!ion of elec!ronic "rade silicon2. 'rys!al "ro/in"

3. Shapin" of Si in!o /afers


16/85


(lec!ronic Grade Silicon

Silicon is one of !he 9os! andan! 9a!erials in !he

ear!hHs crs!, occrrin" na!rally as silica 7e."., sand8

and silica!es 7e."., clay8 Principal ra/ 9a!erial for silicon is quartzite, /hich is

very pre Si2

(lec!ronic "rade silicon 7(GS8 is polycrys!alline

silicon of l!ra hi"h pri!y I9pri!ies are 9easred in par!s per illion


17/85


'rys!al Gro/in"

+he silicon ss!ra!e for 9icroelec!ronic chips 9s!

e 9ade of a sin"le crys!al /hose ni! cell is orien!ed

in a cer!ain direc!ion Ss!ra!e /afers 9s! e c! in a direc!ion !ha!

achieves !he desired planar orien!a!ion

Mos! /idely sed crys!al "ro/in" 9e!hod is !he

Czochralski process Asin"le crys!al bouleis plled fro9 a pool of

9ol!en silicon


18/85


7a8 Ini!ial se!pand 78 drin"crys!al pllin"!o for9 ole

'Cochrals4i Process


19/85


Shapin" of Silicon in!o Wafers

Processin" s!eps !o redce !he ole in!o !hin,

disc shaped /afers

1. In"o! 7ole8 prepara!ion2. Wafer slicin"

3. Wafer prepara!ion


20/85


Prepara!ion of !he ole

+he ends of !he ole are c! off

'ylindrical "rindin" is sed !o shape !he ole in!o a

9ore perfec! cylinder ne or 9ore fla!s are "rond alon" len"!h of ole

*nc!ions, af!er ole is c! in!o /afers, are;

Iden!ifica!ion

rien!a!ion of I's rela!ive !o crys!al s!rc!re

Mechanical loca!ion drin" processin"


21/85


7a8 'ylindrical "rindin" provides dia9e!er and rondnesscon!rol and 78 a fla! "rond on !he cylinder

Grindin" pera!ions on ole


22/85


Wafer Slicin"

'!!in" ed"e is a very !hin rin":shaped sa/ lade

/i!h dia9ond "ri! on in!ernal dia9e!er

I- sed for slicin" ra!her !han !he - for e!!ercon!rol over fla!ness, !hic4ness, parallelis9, and

srface charac!eris!ics of !he /afer

Wafers are c! 0.# 0.5 99 70.020 0.02? in.8 !hic4,

"rea!er !hic4nesses for lar"er /afer dia9e!ers +o 9ini9iCe 4erf loss, lades are very !hin;

!hic4ness 0.30 99 70.013 in8


23/85


Wafer slicin" sin" a dia9ond arasive c! off sa/

Wafer Slicin"


24/85


Wafer Prepara!ion

Wafer ri9s are ronded y con!or "rindin" /heel !o

redce chippin" drin" handlin"

Wafers are che9ically e!ched !o re9ove srfaceda9a"e de !o slicin"

fla! polishin" opera!ion is perfor9ed !o provide

srfaces of hi"h s9oo!hness for pho!oli!ho"raphy

processes !o follo/ *inally, /afer is che9ically cleaned !o re9ove

resides and or"anic fil9s


25/85


i!ho"raphy

n I' consis!s of 9any 9icroscopic re"ions on !he

/afer srface !ha! 9a4e p !he devices and

in!raconnec!ions as specified in !he circi! desi"n In !he planar process, re"ions are farica!ed y s!eps

!ha! add, al!er, or re9ove layers in selec!ed areas of !he

/afer srface

(ach layer is de!er9ined y a "eo9e!ric pa!!ernrepresen!in" circi! desi"n infor9a!ion !ha! is

!ransferred !o !he /afer srface y li!ho"raphy


26/85


i!ho"raphic +echnolo"ies

Several li!ho"raphic !echnolo"ies are sed in

se9icondc!or processin";

p!ical li!ho"raphy 4no/n as Pho!oli!ho"raphy (lec!ron:ea9 li!ho"raphy

K ray li!ho"raphy

Ion ea9 li!ho"raphy

+he differences are in !ype of radia!ion sed !o!ransfer !he 9as4 pa!!ern !o !he /afer srface y

e


27/85


Pho!oli!ho"raphy

ses li"h! radia!ion !o e


28/85


Pho!oli!ho"raphy Mas4

*la! pla!e of !ransparen! "lass on!o /hich a !hin fil9 of

an opaBe ss!ance has een deposi!ed in cer!ain

areas !o for9 !he desired pa!!ern +hic4ness of "lass pla!e is arond 2 99 70.0?0 in8,

/hile deposi!ed fil9 !hic4ness is only 1 9

+he 9as4 i!self is farica!ed y li!ho"raphy

+he pa!!ern is ased on circi! desi"n da!a,sally !he di"i!al o!p! fro9 a '- sys!e9

sed y circi! desi"ner


29/85


Pho!oresis!

r"anic poly9er !ha! is sensi!ive !o li"h! radia!ion in a

cer!ain /avelen"!h ran"e

Sensi!ivi!y cases ei!her increase or decrease insolili!y of !he poly9er !o cer!ain che9icals

+ypical prac!ice in se9icondc!or processin" is !o

se pho!oresis!s !ha! are sensi!ive !o > li"h!

ecase of i!s shor!er /avelen"!hlso per9i!s farica!ion areas in plan! !o e

ill9ina!ed a! lo/ li"h! levels o!side > and


30/85


Pho!oli!ho"raphy (


31/85


Pho!oli!ho"raphy Processin"

SeBence

Srface of !he silicon /afer has een o


32/85



SeBence 718 Prepare srface, 728 apply resis!, 738 sof! a4e, 78

ali"n 9as4 and e


33/85



SeBence 718 Prepare srface, 728 apply resis!, 738 sof! a4e, 78

ali"n 9as4 and e


34/85


par!ially processed

silicon /afer af!er

several li!ho"raphys!eps 7cor!esy of

Geor"e (. Lane

Manfac!rin"

+echnolo"y

aora!ory, ehi"hniversi!y8


35/85


!her i!ho"raphy +echniBes

s fea!re siCes in in!e"ra!ed circi!s con!ine !o

decrease and > pho!oli!ho"raphy eco9es

increasin"ly inadeBa!e, o!her li!ho"raphy !echniBes!ha! offer hi"her resol!ion are "ro/in" in i9por!ance

(8 li!ho"raphy

(lec!ron ea9 li!ho"raphy

K ray li!ho"raphy Ion li!ho"raphy


36/85


ayer Processes sed in

I' *arica!ion

S!eps !o farica!e I's on a silicon /afer consis! of

che9ical and physical processes !ha! add, al!er, or

re9ove re"ions defined y pho!oli!ho"raphy %e"ions are insla!in", se9icondc!in", and

condc!in" areas !ha! for9 !he devices and !heir

in!raconnec!ions in !he I'

ayers are farica!ed one a! a !i9e, each layerreBirin" a separa!e 9as4, n!il all of !he de!ails

have een farica!ed on!o !he /afer srface


37/85


ayerin" Processes !ha! add or

al!er layers in I' *arica!ion

+her9al o


38/85


+her9al


39/85


Gro/!h of Si2fil9 on a silicon ss!ra!e y !her9al

o


40/85


*nc!ions of Silicon -io


41/85


'he9ical >apor -eposi!ion

7'>-8 A !ypical reac!ions in I'

farica!ion

When a silicon dio- involves "ro/!h of a !hin fil9 on !he srface of a hea!ed ss!ra!e

y che9ical reac!ions or deco9posi!ion of "ases 7Sec!ion 2.#.28

'>- is /idely sed in !he processin" of in!e"ra!ed circi! /afers !o add

layers of Si, Si2, Si

3)

7silicon ni!ride8 and varios 9e!alliCa!ion

9a!erials Plas9a:enhanced '>- is of!en sed ecase i! per9i!s !he reac!ions

!o !a4e place a! lo/er !e9pera!res


42/85


43/85


In!rodc!ion of I9pri!ies

in!o Silicon

I' !echnolo"y relies on !he aili!y !o al!er !he elec!ricalproper!ies of silicon y in!rodcin" i9pri!ies in!o

selec!ed re"ions of !he srface 'alledDoping: addin" i9pri!ies in!o Si srface

'o99on dopin" ele9en!s are oron 78, phosphoros7P8, arsenic 7s8, and an!i9ony 7S8

+echniBes for dopin" silicon;

1. +her9al diffsion

2. Ion i9plan!a!ion


44/85


Ion I9plan!a!ion

-opin"; >aporiCed ions of i9pri!y ele9en! are accelera!ed y an

elec!ric field and direc!ed a! silicon ss!ra!e

!o9s pene!ra!e in!o srface, losin" ener"y and finally s!oppin" a!

so9e dep!h in crys!al s!rc!re de!er9ined y 9ass of ion and

accelera!ion vol!a"e

dvan!a"es;

'an e acco9plished a! roo9 !e9pera!re

Provides e


45/85


Me!alliCa!ion

'o9ines varios !hin fil9 deposi!ion !echnolo"ies

/i!h pho!oli!ho"raphy !o for9 very fine pa!!erns of

condc!ive 9a!erial *nc!ions of condc!ive 9a!erials on /afer srface;

*or9 cer!ain co9ponen!s 7e."., "a!es8 of I'

devices

Provide condc!ion pa!hs e!/een devices onchip

'onnec! !he chip !o e


46/85


Me!alliCa!ion Ma!erials

18l9in9 : 9os! /idely sed 9e!alliCa!ion 9a!erial

Sa!isfies 9os! of !he reBired proper!ies

28 !her 9a!erials; silicon 7Si8D "old 78D refrac!ory9e!als 7e."., W, Mo8D silicides 7e."., WSi2, MoSi2,

+aSi28D and ni!rides 7e."., +a), +i), and Or)8

pplica!ions sch as "a!es and con!ac!s


47/85


Me!alliCa!ion Processes

18 Physical >apor -eposi!ion 7P>-8 A P>- 9e!alliCa!ion

processes inclde vac9 evapora!ion and

sp!!erin"28 'he9ical >apor -eposi!ion 7'>-8 A less co99on

!han P>-

38 (lec!ropla!in" 7'hap!er 28 : occasionally sed !o

increase !hic4ness of !hin fil9s


48/85


(!chin"

18 'er!ain s!eps in I' 9anfac!rin" reBire 9a!erial

re9oval fro9 srface, acco9plished y e!chin"

a/ay n/an!ed 9a!erial28 sally done selec!ively, y 9as4in" areas !ha! are

!o e pro!ec!ed and leavin" o!her areas e


49/85


We! 'he9ical (!chin"

18 se of an aBeos sol!ion 7solven! is @28, sally

an acid, !o e!ch a/ay a !ar"e! 9a!erial

a8(!chan! is selec!ed !o che9ically a!!ac4 !hespecific 9a!erial and no! !he pro!ec!ive layer 7see

+ale 30.28

8Process variales are i99ersion !i9e, e!chan!

concen!ra!ion, and !e9pera!rec8In i!s si9ples! for9, e!chin" involves i99ersin"

!he 9as4ed /afers for a specified !i9e and !hen

i99edia!ely rinsin" !o s!op !he e!chin"


50/85


We! 'he9ical (!chin"

18 se of an aBeos sol!ion 7solven! is @28, sally

an acid, !o e!ch a/ay a !ar"e! 9a!erial

a8(!chan! is selec!ed !o che9ically a!!ac4 !hespecific 9a!erial and no! !he pro!ec!ive layer 7see

+ale 30.28

8In i!s si9ples! for9, e!chin" involves i99ersin"

!he 9as4ed /afers for a specified !i9e and !heni99edia!ely rinsin" !o s!op !he e!chin"

c8Process variales are i99ersion !i9e, e!chan!

concen!ra!ion, and !e9pera!re


51/85


18 Profile of a properly e!ched layer sho/n elo/

28 'he9ical e!chin" reac!ion is isotropic, casin" an nderc!

elo/ pro!ec!ive 9as4

38 Mas4 pa!!ern 7resis!8 9s! e siCed !o co9pensa!e

'he9ical (!chin"


52/85


-ry Plas9a (!chin"

18 ses an ioniCed "as !o e!ch a !ar"e! 9a!erial

a8 IoniCed "as is crea!ed y in!rodcin" an appropria!e

"as 9i

8+he hi"h ener"y plas9a reac!s /i!h !he !ar"e! srface,

vaporiCin" 9a!erial !o re9ove i!

c8 +he advan!a"e of plas9a e!chin" over /e! che9icale!chin" is !ha! i! is 9ch 9ore aniso!ropic. In a flly

aniso!ripic e!ch, !he nderc!elo/ !he pro!ec!ive9as4 is Cero


53/85


Process In!e"ra!ion in

I' *arica!ion 71 of 28

18 -eal! /i!h i!ho"raphy & ayer Processes A no/

loo4in" a! seBence of I' 9anfac!rin" s!eps

28 +ale 30.3 A s99ary of !ypical processes sed !oadd or al!er a layer of "iven 9a!erial !ype.

38 +he se of li!ho"raphy !o apply a par!iclar process

only !o selec!ed re"ions of !he srface is ills!ra!ed in

*i" 30.15.


54/85


Process In!e"ra!ion in

I' *arica!ion 72 of 28

Process in!e"ra!ion in I' farica!ion e


55/85


):'hannel Me!al


56/85


I' *arica!ion SeBence 71 of 28

718 S!ar!in" ss!ra!e is a li"h!ly doped p !ype silicon /afer,

/hich /ill for9 !he ase of n channel !ransis!or. Si 3)9as4

is deposi!ed y '>- on Si ss!ra!e, 728 Si2is "ro/n y

!her9al o


57/85


I' *arica!ion SeBence 72 of 28

7#8 Polysilicon is deposi!ed y '>- and doped n !ype 7n8

sin" ion i9plan!a!ion, 78 poly:Si is selec!ively e!ched

sin" pho!o:li!ho"raphy !o define "a!e elec!rode, 758 sorce

and drain re"ions 7see *i" 30.18 are for9ed y dopin" nin

ss!ra!e, 7?8 Phosphosilica!e "lass 7P:"lass8 is deposi!ed

on!o srface y '>- for pro!ec!ion


58/85


59/85


-esi"n Isses in I' Pac4a"in"

18 (lec!rical connec!ions !o e

28 Ma!erials !o encase chip and pro!ec! i! fro9 !he

environ9en!a8@9idi!y and corrosion

8+e9pera!re

c8>ira!ion and 9echanical shoc4

38 @ea! dissipa!ion

8 Perfor9ance, reliaili!y, and service life

#8 'os!


60/85


Manfac!rin" Isses in

I' Pac4a"in"

18 'hip separa!ion c!!in" /afer in!o individal chips

28 'onnec!in" i! !o !he pac4a"e

38 (ncapsla!in" !he chip8 'irci! !es!in"

Mos! of !he desi"n isses are addressed in o!her !e

so9e en"ineerin" aspec!s of I' pac4a"es 7a.4.a. chip

carriers8 and !he !ypes of pac4a"es are discssed,efore descriin" !he processin" s!eps !o 9a4e !he9.


61/85


I' Pac4a"e -esi"n

18 +hree of !he fac!ors rela!ed !o !he desi"n of an

in!e"ra!ed circi! pac4a"e;

a8)9er of inp!$o!p! !er9inals reBired for anI' of a "iven siCe

8Ma!erials sed in I' pac4a"es

c8Pac4a"e s!yles


62/85


-e!er9inin" !he n9er of

Inp!$!p! 7I$8 +er9inals

18 Prole9 is !o connec! 9any in!ernal circi!s on !he chip !o I$

!er9inals so !ha! !he appropria!e elec!rical si"nals can e

co99nica!ed !o !he o!side /orld

28 s !he n9er of devices in !he I' increases, !he reBiredn9er of I$ !er9inals also increases

a8 %en!s %le; nioQ Cnicm

8 +he para9e!ers ' & 9 depend on !he !ype of circi! and !he

desi"n of !he I'

38 +he prole9 is a""rava!ed y I' !rends;

a8 -ecreases in device siCe

8 Increases in n9er of devices in I'


63/85


-e!er9inin" !he n9er of

Inp!$!p! 7I$8 +er9inals

See https://en.wikipedia.org/wiki/Die_%28integrated_circuit%2

!nte" #eon $&&0 die' mounted on

heat spreader. Die is 22(2)mm*50+ mm2,' and contains-'00'000'000 transistors


64/85


I' Pac4a"e Ma!erials

18 'era9ic 7l9ina $ al9ini9 o


65/85


I' Pac4a"e Ma!erials

18 'era9ic 7l9ina $ al9ini9 o


66/85


+/o asic +ypes of I' Pac4a"e

1. +hro"h hole 9on!in", also called pin in hole 7PI@8

!echnolo"y

a8 I' pac4a"e and o!her co9ponen!s have leadsinser!ed !hro"h holes in P' and soldered on

nderside

2. Srface 9on! !echnolo"y 7SM+8

a8 'o9ponen!s are a!!ached !o srface of oard 7inso9e cases, o!h !op and o!!o9 srfaces8


67/85


+ypes of co9ponen! lead a!!ach9en! on a prin!ed circi!

oard; 7a8 !hro"h hole, and several s!yles of srface 9on!

!echnolo"y; 78 !! lead, 7c8 RJR lead, and 7d8 "ll /in"

+/o asic +ypes of I' Pac4a"e


68/85


MaEor I' Pac4a"e S!yles

18 -al in line pac4a"e 7-IP8

28 SBare pac4a"e

38 Pin "rid array8 So9e of !hese are availale in o!h !hro"h hole and

srface 9on! s!yles, /hile o!hers are desi"ned for

only one 9on!in" 9e!hod


69/85


7a8 -al in line pac4a"e /i!h 1 !er9inals, sho/n here in

!hro"h hole confi"ra!ion and 78 sBare leaded chip

carrier 7''8 for srface 9on!in" /i!h "ll /in" leads

7a8 78

-al In:ine Pac4a"e 7-IP8


70/85


Pin Grid rray 7PG8

18 +/o di9ensional array of pin !er9inals on nderside of

a sBare chip enclosre

a8SBare 9a!ri< 9a


71/85


Pin Grid rray 7PG8 chip carrier



72/85


Processin" S!eps in

I' Pac4a"in"

18 Wafer !es!in"

28 'hip separa!ion

38 -ie ondin"8 Wire ondin"

#8 Pac4a"e sealin"

8 *inal !es!in"


73/85


Wafer +es!in"

18 +es!in" 7called multiprobe8 is acco9plished y

co9p!er con!rolled eBip9en! sin" needle proes

!ha! 9a!ch connec!in" pads on !he chip srfacea8+hese !es!s are perfor9ed /hile I' chips are s!ill on

!he /afer efore separa!ion

8s proes con!ac! pads, !es!s indica!e shor! circi!s

and o!her fal!s, follo/ed y a fnc!ional !es!

i. 'hips !ha! fail are 9ar4ed /i!h an in4 do! and are

no! pac4a"ed


74/85


'hip Separa!ion

18 Wafer is c! in!o individal chips 7dice8 sin" a !hin

dia9ond i9pre"na!ed sa/ lade

a8+he /afer is a!!ached !o a piece of adhesive !ape9on!ed in a fra9e

i.dhesive !ape holds individal chips in place

drin" and af!er sa/in"

ii.+he fra9e is a convenience in sseBen!handlin" of !he chips

8'hips /i!h in4 do!s are no/ discarded


75/85


-ie ondin"

18 !o9a!ed handlin" sys!e9s pic4 separa!ed chips

fro9 !ape fra9e and place !he9 for die ondin"

28 >arios !echniBes are sed !o ond !he chip !o !hepac4a"in" ss!ra!e, incldin";

a8(!ec!ic die ondin" A for cera9ic pac4a"es

8(po


76/85


-ie ondin"; 2 dice onded !o

one chip carrier



77/85


78/85


In!e"ra!ed circi!

fro9 an (P%M

9e9ory 9icrochip

sho/in" !he 9e9oryloc4s, !he

sppor!in" circi!ry

and !he fine silver

/ires /hich connec!

!he in!e"ra!ed circi!die !o !he le"s of !he

pac4a"in".

Wire 'onnec!ions

See https://en.wikipedia.org/wiki/!ntegrated_circuit


79/85


7a8 '!a/ay vie/ sho/in" !he chip a!!ached !o a lead

fra9e and 78 encapsla!ed in a plas!ic enclosre

Pac4a"in" of I' 'hip


80/85


*inal +es!in"

18 pon co9ple!ion of pac4a"in" seBence, each I'

9s! nder"o a final !es!

28 Prpose of !es!;a8-e!er9ine /hich ni!s, if any, have een da9a"ed

drin" pac4a"in"

8Measre perfor9ance charac!eris!ics of each

device


81/85


6ields in I' Processin"

18 *arica!ion of I's consis!s of 9any processin"

s!eps perfor9ed in seBence

a8In /afer processin" in par!iclar, !here 9ay ehndreds of dis!inc! opera!ions perfor9ed on

!he /afer

28! each s!ep, !here is a chance !ha! so9e!hin"

can "o /ron", resl!in" in loss of !he /afer or

por!ions of i! correspondin" !o individal chips


82/85


Proaili!y Model !o Predic! 6ield

18 si9ple proaili!y 9odel !o predic! !he final

yield of "ood prodc! is;

Y QYcYsYwYmYt28 Given !he !ypical vales a! each s!ep, !he final

yield co9pared !o !he s!ar!in" a9on! of silicon

is Bi!e lo/


83/85


718 Pre silicon is for9ed fro9 9ol!en s!a!e in!o in"o! and

!hen sliced in!o /afersD 728 farica!ion of in!e"ra!ed circi!s

on /aferD and 738 /afer is c! in!o chips and pac4a"ed

SeBence in I' Processin"


84/85


85/85

+he Ley !o Sccessfl

I' *arica!ion

18 Wafer processin"; for an I' prodcer !o e profi!ale,hi"h yields 9s! e achieved drin" /afer processin"

28 +his is acco9plished y !iliCin";

a8Pres! possile s!ar!in" 9a!erials

8a!es! processin" !echnolo"ies and eBip9en!

c8Good process con!rol over processin" s!eps

d8Main!enance of clean roo9 condi!ions

e8(fficien! and effec!ive inspec!ion and !es!in"procedres

chapter 30 manufacturing

Documents