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Ch. 6 Combinational Logic Circuits

Logic CircuitsCombinational Logic CircuitsSequential Logic Circuits

Combinational Logic CircuitsAddersSubtractersCode ConvertersParity Generator/CheckerDecodersIncodersMultiplexer/Demultiplexer

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Logic CircuitsCombinational Logic Circuits : Inputs, Logic gates, Outputs

Sequential Logic Circuits : Combinational Logic Circuits + Memory (Flip/Flop)

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Combinational Logic Circuits

AddersHalf Adder

An arithmetic circuit that generates the sum of two binary bits.

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Sum and Carry Functions

0 0

0 0 0 0

0 0

S

A B A BA B

≡

= += ⊕

∑

0

0 0

outC CA B

≡

=

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0 0

0 0 0 0

0 0

S

A B A BA B

≡

= += ⊕

∑

0

0 0

outC CA B

≡

=

Circuit Design

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0 0

0 0 0 0

0 0

S

A B A BA B

≡

= += ⊕

∑

0

0 0

outC CA B

≡

=

Circuit Design by using the HA Symbol

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Full AdderA combinational circuit that forms the arithmetic sum of three input bits.

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Sum and Carry Functions

0 0

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1

1 1

( ) ( )

( ) ( )

in in in in

in in

in in

in

S

A B C A B C A B C A B CA B A B C A B A B C

A B C A B CA B C

≡

= + + +

= + + +

= ⊕ + ⊕

= ⊕ ⊕

∑

0

1 1 1 1 1 1

1 1 1 1( )

out

in in

in

C CA B A B C A B CA B A B C

≡

= + +

= + ⊕

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Circuit Design

0 0

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1

1 1 1 1

1 1

( ) ( )

( ) ( )

in in in in

in in

in in

in

S

A B C A B C A B C A B CA B A B C A B A B C

A B C A B CA B C

≡

= + + +

= + + +

= ⊕ + ⊕

= ⊕ ⊕

∑

0

1 1 1 1 1 1

1 1 1 1( )

out

in in

in

C CA B A B C A B CA B A B C

≡

= + +

= + ⊕

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Circuit Design by using the FA Symbol

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Circuit Design by using Two HA + OR Gate

1A1BinC

1∑outC

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(Ex. 6.1) 4-Bit Binary Adder

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4-Bit Binary Adder by 7483

Look-ahead carryReduce time delay

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8-Bit Binary Adder by 74HC283

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Combinational Logic Circuits

0 0 0 0 0

0 0

D A B A BA B

= +

= ⊕Subtractors

Half Subtractor

1 0 0rB A B=

0 0 0 0

0 1 1 1

1 0 0 1

1 1 0 0

0A 0B 1rB 0D

0A0D

1rB

0B

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Combinational Logic Circuits

Full Subtractor

0 0 0 0 0

1

1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 0

1

0 0 1 1

0 1 0 1

1 1 1 1

2rB1A 1B 1rB 0D

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Combinational Logic Circuits

Logic Functions Check the K-Map !

0 0 0 0 0

1

1

0 1 1 1 0

1 0 0 0 1

1 0 1 0 0

1 1 0 0 0

1

0 0 1 1

0 1 0 1

1 1 1 1

2rB1A 1B 1rB 0D 0 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1

1 1 1

( ) ( )r r r r

r r

r

D A B B A B B A B B A B BA B A B B A B A B B

A B B

= + + +

= + + += ⊕ ⊕

2 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1

1 1 1 1 1

( )

( )

r r r

r

r

B A B A B B A B BA B A B A B B

A B A B B

= + +

= + +

= + ⊕

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Combinational Logic Circuits

Circuit Design

0 1 1 1 1 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 1 1 1

1 1 1

( ) ( )r r r r

r r

r

D A B B A B B A B B A B BA B A B B A B A B B

A B B

= + + +

= + + += ⊕ ⊕

2 1 1 1 1 1 1 1 1

1 1 1 1 1 1 1

1 1 1 1 1

( )

( )

r r r

r

r

B A B A B B A B BA B A B A B B

A B A B B

= + +

= + +

= + ⊕

0D

2rB

1A1B1rB

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Code ConvertersBinary Code Gray Code

BCD 2421 Code : p119

Binary code Gray code

0

1

1

0

0

1

1

0

0 0 0 0 0

0 0 1 0 0

1

0 1 1 0 1

1 0 0 1 1

1 0 1 1 1

1 1 0 1 0

0

0 1 0 0

1 1 1 1

2A 1A 0G1G0A 2G

2 2G A=

1 2 1 2 1

2 1

G A A A AA A

= += ⊕

0 1 0 1 0

1 0

G A A A AA A

= += ⊕

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Code ConvertersBinary Code Gray Code

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Parity Generator 3 Bits Odd parity

0 0 0 1

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0

1 0 1 1

1 1 0 1

1 1 1 0

0A2A 1A P2 1 0 2 1 0 2 1 0 2 1 0

2 1 2 1 0 2 1 2 1 0

2 1 0 2 1 0

2 1 0

( ) ( )

( ) ( )

P A A A A A A A A A A A A

A A A A A A A A A A

A A A A A AA A A

= + + +

= + + +

= ⊕ + ⊕

= ⊕ ⊕

2A1A

0A

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Parity Checker Odd parity checker : Table 6-4, p123

2 1 0 2 1 0 2 1 0 2 1 0 2 1 0 2 1 0

2 1 0 2 1 0

2 1 0 0 2 1 0 0 2 1 0 0 2 1 0 0

2 1 2 1 0 0 2 1 2 1 0 0

2 1 0 2 1 0

2 1

( ) ( ) ( ) ( )

( )( ) ( )( )

( )( ) ( )( )( )

C A A A P A A A P A A A P A A A P A A A P A A A P

A A A P A A A P

A A A P A P A A A P A P A A A P A P A A A P A P

A A A A A P A P A A A A A P A P

A A A P A A A PA A

= + + + + +

+ +

= + + + + + + +

= + + + + +

= ⊕ ⊕ + ⊕ ⊕

= ⊕ ⊕ 0

2 1 0

( )A PA A A P

⊕= ⊕ ⊕ ⊕

2A1A0A

P

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DecodersDecoding is the conversion of an -bit input code to an -bit output code with such that each valid input code word produces an unique output code -to- -line decoder.

2nn m≤ ≤n m

n m

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2-to-4 decoder : Fig. 6-15

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Active Low Output 2-to-4 decoder with an Enable : Fig. 6-16

1A

0A

E

1D2D

0D

3D

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3-to-8 decoder Table 6-6Figs. 6-17, 18

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3-to-8 decoder IC : 74138

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EncodersAn encoder is a digital function that performs the inverse of a decoder.An encoder has (or fewer) input lines and output lines, where the output lines generate the binary code corresponding to the input value.

2n n

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Octal-to-Binary Encoder, Table 6-8

0 1 3 5 7

1 2 3 6 7

2 4 5 6 7

A D D D DA D D D DA D D D D

= + + += + + += + + +

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Implementation of the Octal-to-Binary Encoder: Fig. 6-21

0

1

2

3

4

5

6

7

DDDDDDDD

0A0 1 3 5 7

1 2 3 6 7

2 4 5 6 7

A D D D DA D D D DA D D D D

= + + += + + += + + +1A

2A

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Multiplexer (MUX)A multiplexer is a combinational circuit that selects binary information from one of many inputs lines and directs the information to a single output line. data selector

Input lines : Selection inputs :

2n

n

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(Ex. 6.2) 4-to-1-line multiplexer

( ) ( ) ( ) ( )1 0 0 1 0 1 1 0 2 1 0 3Y S S I S S I S S I S S I= + + +

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Logic diagram for a 4-to-1-line multiplexer

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Logic diagram for a 8-to-1-line multiplexer : 74151

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Demultiplexer

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1x4 Demultiplexer

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1x16 Demultiplexer

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Homework3, 6, 9, 10