arm instruction prgoramming

7/27/2019 Arm Instruction Prgoramming

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ARM Processor

Instruction SETandPro rammin

Dr. C.H. Vithalani

E.C. Department,Government Engineering College,Rajkot



ARM Instruction SetARM instruction set

Data processinginstructions Data transfer

Software interruptinstructions

Block transferinstructions

Multiply instructions

Branching instructions



ARM Instruction Set

• ARM architecture is such that 32-bit ARMinstruction set & 16 bit Thumb instruction bothcan be used.

• Various addressing modes are as follow:

.2. Immediate addressing3. Indirect base and indexed addressing



Register Addressing Modes

• All the operands are within the register itself.• Example:

MOV R1,R2 R2 Æ R1MVN R1,R2 R2’Æ R1 (Complement of R2)

ADD R1,R2,R3 R1= R2+ R3SUB R5,R4,R7 R5= R4-R7

SUB R4,R5,R7,LSR R2• (Logical right shift R7 by the number in the bottombyte of R2, subtract result from R5, and put theanswer into R4)



Immediate Addressing Mode

• Second source operand is immediate operand

• MOV R0,# 0 R0= 0• ADD r6,r7,# 6 R6= R7+ 6• CMP R7,# 1000 Compare content of R7 with 1000

• MOV R1,# 0x17 Hexadecimal value 17h in R1• MOV R2,# 17 Decimal value 17 in R2• MOV R1,R1,LSL # 2

R1 shifted left by 2 bit position and saved back inR1 (R1= R1* 4)



Indirect Base and Indexed addressing

• Major mode for load/store architecture as directabsolute addressing not available

• LDR R1,[R2] ; Load R1 from memory addresspointed by R2 R1 Å * R2

• LDR R1,[R2,-R3]; Load R1 from memory addresspointed by (R2-R3)

R1 Å * (R2-R3)• LDR R1,[R2,# 8]; R1 Å * (R2+ 8)



Indirect Base and Indexed addressing

• STR [R5,# &0C],R4

Store Register R4 to the memory address pointedby R5+ 12• Indirect addressing mode by index plus offset with

For example: LDR R1,[R2],# 8In this instruction R1 is loaded from memory

location pointed by R2 and after loading offset of8 is added into R2 . This is called auto postindexing



Indirect addressing by index plusoffset with pre auto indexing

• LDR R4,[R3,# 8]!Load R4 from memory address pointed by R3after addin offset 8 into R3.

If R3= 0000 0000 0000 0010 then R4 will beloaded from the location (R3+ 8) = 0000 00000000 1010 in case of pre-auto indexing. In case ofpost indexing R4 will be loaded from 0000 00000000 0010 and then R3 becomes 0000 0000 00001010



Arithmetic Instructions• Operations such as addition, subtraction and

multiplication are available in direct and modified

form.• ADD Rd,Rn,< Oprnd> Exa: ADD R1,R2,# 55

Above instruction adds Rn to < Oprnd> and store

result in Rd. (R1= R2+ 55)• ADDS Rd,Rn,< Oprnd> Exa: ADDS R1,R2,# 55

Same as ADD but ADDS has additional effect oftesting the result stored in Rd and setting fourcondition codes in CPSR.



Arithmetic Instructions• ADC Rd,Rn,< oprnd> Exa: ADC R4,R5,R6

ADC includes carry during addition process. In

above example R4= R5+ R6+ Carry. C• SUB Rd,Rn,< oprnd> Exa: SUB R2,R2,R5

R2= R2-R5• SUBS Rd,Rn,< oprnd> Exa: SUBS R2,R2,R5

R2= R2-R5 CPSR is affected by result in R2

• RSB (Reverse subtraction)RSB Rd,Rn,< oprnd> Exa: RSB R2,R2,R5R2= R5-R2

• RSBS (Reverse subtraction with CPSR affected)



Arithmetic Instructions• SBC (Consider carry during subtraction)• SBC Rd,Rn,< oprnd> Exa: SBC R1,R2,R3

R1= R2-R3-NOT(carry)• SBCS (Same as SBC but CPSR is affected by result

in destin tion• RSC Rd,Rn,< oprnd> Exa: RSC R1,R2,R3

R1= R3-R2-NOT(carry)

• RSCS (Same as RSC but CPSR is affected byresult)



Instructions• MUL R1,R2,R3; R1:=R2*R3• MOV R2,R0, LSL #3 ; Shift R0 left by 3 Æ R2

(R2=R0*8)• ADD R9,R5,R5,LSL #2 ; R9=R5*4+R5

(R9=5*R5)

• SUB R10,R9,R8,LSR#4 ; R10=R9-R8/16• MLA R1,R2,R3,R4 ; R1=(R2*R3)+R4

(Multiply and accumulate useful for convolution in

signal processing applications)• MOV R12,R4,ROR R3 ; R12=R4 rotated right by

value of R3



Load and store instructionsTransfers data between memory and processorregisters

• Single Register transfer: Data type supported are32 bit signed or unsigned, 16 bit and 8 bitWord Half-word or B te

• Multiple Register transfer: Transfer multipleregisters between memory and processor in singleinstruction

• Swap: swap content of memory with content ofprocessor registers.



Load and store Instructions• Load/store instructions are basically data transfer

instructions from processor memory to registers and vice-varsa

• Can be used to load PC

LDR Load Word STR Store Word

LDRH Load Half Word STRH Store Half Word

LDRSH Load Signed Half Word STRSH Store Signed Half Word

LDRB Load Byte STRB Store Byte

LDRSB Load Signed Byte STRSB Store Signed Byte



Instructions• LDRH R1,[R2,-R3]!

Load R1 from the contents of the half word

address contained in R2-R3 (both of which areregisters) and write back address to R2• STRH R3,[R4,# 14]

tore t e a wor n 3 at 14+ 14 utdon't write back.• LDRSB R8,[R2] ,# -223

Load R8 with the sign extended contents of thebyte address contained in R2 and write backR2-223 to R2.



Data Transfer Instructions

OffsetAddressing

LDR: Load in register a word (32 bit)

• LDR R0,[R1,#4] R0 Å [R1+4]• LDR R0,[R1,R2] R0 Å [R1+R2]• LDR R0,[R1,R2,LSL #2] R0 Å [R1+R2*4]




Pre-IndexAddressing

• , , =• LDR R0,[R1,R2]! R0 Å [R1+R2] & R1=R1+R2• LDR R0,[R1,R2,LSL #2]! R0 Å [R1+R2*4] &

R1=R1+R2*4




Post-IndexAddressing

• , , =• LDR R0,[R1],R2 R0 Å [R1] & R1=R1+R2• LDR R0,[R1],R2,LSL #2 R0 Å [R1] & R1=R1+R2*4

LDRB: Load a byteLDRH: Load half word (16 Bit)



Data Transfer Instructions• STR: Store a word in register

• STRB: Store a Byte in register• STRH: Store a Half word (16 bit) in register

Exam les: STR R0,#10101010• STR R0,[R1] R0 Æ [R1]

Store word from register R0 to location

specified by R1.• STRH R3,[R1,# 10] R3 Æ [R1+ 10]Store the halfword in R3 at [R1+ 10]



Data Transfer Instructions• STR R1,[R2,R3] R1 Æ [R2+R3]

Store content of R1 at memory location pointed byR2+R3• STR R1,[R2,R3]! R1 Æ [R2+R3] and R2=R2+R3

Store content of R1 at memory location pointed byR2+R3 and R2 becomes R2=R2+R3.• STR R1,[R2],R3 R1 Æ [R2] and R2=R2+R3

Store content of R1 at memory location pointed byR2 and R2 becomes R2=R2+R3 .



Block Transfer Instructions• Load/Store Multiple

instructions (LDM / STM )• Whole register bank or a

subset copied to memory or

R0R1

R2

Mi

Mi+1

Mi+2

LDM

restored with single instruction• It may increase interrupt

latency because thisinstruction usually notinterrupted

R14

R15

+

Mi+15

STM



Example: block transfer• LDMIA R0!, {R1-R3}

• The register R0 specifies base address of thememory from where registers R1,R2 and R3 will beloaded.

• IA: Increment after R0 will be incrementedautomatically after each transfer: R0=R0+4N

• Similarly IB: Increment before, DA: Decrement afterDB: Decrement Before options are also possible.



Swap Instruction• Exchanges a word between

registers• Two cycles but

R0

R1

R2

s ng e a om c ac on

• Support for RT semaphoresR8

R15



Logical Instructions• Bitwise logical operations (like ANR, OR, Ex-OR, Bit

clear) on two source registers is performed and result isstored in destination register.

• Example: BIC R0,R1,R2

• R2 contains binary pattern where every binary 1 in R2.

• Useful in manipulating status flag and interrupt mask .

• For example

• R1: 1011 0111 0111 1111 1011 0000 1111 1010• R2: 0111 1111 0000 0000 1010 0000 0000 1111

• R0: 1000 0000 0111 1111 0001 0000 1111 0000



Compare Instructions• COMP R0,R5

• Flags set as a result of R0-R5

Consider the instructions:CMP R1,#0 ; Compare R1 with 0.BNE LOOP ; Branch if not equal

.instruction is branch instruction, program will jump tolocation specified by label LOOP if R1 is not equal to 0.

• TEQ R1,R2

• Flags set as a result of R1 Ex-OR R2• TST R2,R3

• Flags set as a result of R2 & R3



Modifying the Status Registers• Only indirectly

• MSR moves contentsfrom CPSR/SPSR

R0

R1

MRS

• MRS moves contentsfrom selected GPR

to CPSR/SPSR• Only in privileged

modes

R8

R14

R15

CPSRSPSR

MSR



Shift operations by barrel shifter

DestinationCF 0

LSL : Logical Left Shift

Multiplication by a power of 2

MSB moves to carry flag and 0inserted at LSB

EXAMPLESMOV R0,R1,LSL #2

MOV R0,R1,LSL R2

Destination CF...0

LSR : Logical Shift Right

Division by a power of 2

LSB moves to carry flag and 0inserted at MSB

EXAMPLESMOV R0,R1,LSR #2

MOV R0,R1,LSR R2



The Barrel Shifter

Destination CF

ASR: Arithmetic Right Shift

Division by a power of 2,preserving the sign bit

ROR: Rotate Right

Maintains MSB so that useful tomaintain sign of value

EXAMPLESMOV R0,R1,ASR #2

MOV R0,R1,ASR R2

Destination CF

Bit rotate with wrap aroundfrom LSB to MSB

Destination

RRX: Rotate Right Extended

Single bit rotate with wrap aroundfrom CF to MSB

CF

MSBEXAMPLESMOV R0,R1,ROR #2

MOV R0,R1,ROR R2

Supports 1 bit shift LSB to carryand carry to MSB

EXAMPLEMOV R0,R1,RRX



Register, optionally with shift operation – Shift value can be either be:

• 5 bit unsigned integer• Specified in bottom byte of

another register. – Used for multiplication by constant

Operand1

BarrelShifter

Operand2

Barrel Shifter: Second Operand

Immediate value – 8 bit number, with a range of 0-255.

• Rotated right through evennumber of positions

– Allows increased range of 32-bitconstants to be loaded directly intoregistersResult

ALU



Multiply Instructions• Integer multiplication (32-bit result)

• Long integer multiplication (64-bit result)

• Built in Multiply Accumulate Unit (MAC)

• Multiply and accumulate instructions addproduct to running total



Multiply Instructions• I nstructions:

MUL Multiply 32-bit result

MULA Multiply accumulate 32-bit result

UMULL Unsigned multiply 64-bit result

UMLAL Unsigned mult iply accumulate 64-bit result

SMULL Signed multiply 64-bit result

SMLAL Signed multiply accumulate 64- bit result



Compare and Test Instructions• Comparison instructions are used to compare and test the

content of register with a given 32 bit value.

• The CPSR is always affected but no register is changed• The first operand is register Rd and second operand can be

immediate constant or register with additional shifts or

rotations• TST and TEQ performs Boolean evaluation with AND and

Ex-OR operations

• CMP Rd,< Oprnd2> Update CPSR after Rd - < Oprnd2>• TST Rd,< Oprnd2> Update CPSR after Rd AND < Oprnd2>

• TEQ Rd,< Oprnd2> Update CPSR after Rd EOR < Oprnd2>



Branching Instructions• Branching instructions are used to transfer control

conditionally anywhere in the memory which changessequential flow of instructions. Broadly there are twotypes of branching instructions:

• Branch ( B): Jumps forwards/backwards up to 32 MB

• The notation is B{cond}, Where cond is conditionalcodes used for conditional branch.

• For example: BNE LOOP : If this instruction is given afterCMP R1,#0, then program will jump to location specifiedby LOOP label if R1 is not equal to zero.

• Branch link ( BL): Same as B + saves next instructioni.e. (PC+4) in Link Register (R14)

• BL is suitable for function call/return. When subroutinefinished it can return to main program by copying contentfrom Link register R14.



Conditional Execution• Condition codes specifies which bits in the CPSR need to

be tested.• Conditional codes used with branch instruction B is given

in following table:

EQ equal MI negative HI unsignedhigher GT signed greater

than

NE not equal PL

zeroLS

lower or sameLE

than or equal

CSunsignedhigher orsame

VS overflow GE signed greaterthan or equal AL always

CC unsigned

lowerVC no overflow LT signed less

thanNV special

purpose

• Possible branching instructions using conditionalcodes are BEQ, BMI, BNE, BAL etc.



Example: Conditional ExecutionADDEQ R0,R1,R2

• Instruction executed only if zero flag is setR0=R1+R2 only if zero flag is set.Advanta e of conditional execution

instruction:• Conditional instructions reduces number

of branches and number of pipelineflushes

• Increases code density



Branching Instructions• Two types of branch instructions: B & BL

• B: Ordinary branch instruction• BL: Branch and link instruction

• BL Perform branch operation and saveaddress following the branch (returnaddress) in the link register R14.

• BL <Name of subroutine>



Branching Instructions• Branch and Exchange ( BX)

• This instruction is only executed if thecondition is true.

• This instruction performs a branch bycopying the contents of a general register,Rn, into the program counter (PC)



Branching Instructions• Branch exchange (BX) and

Branch link exchange (BLX) :same as B/BL +exchan e instruction set ARM THUMB

• To return from subroutine to the mainprogram there is no RET instruction but

MOV PC,R14 can be used to return



Example: Conditional ExecutionConsider that value loaded in R1=55 and R2=66

CMP R1,R2

• BEQ <label> : Branch not taken because (R1- 5

• BNE <label> %UDQFK WDNHQ EHFDXVH 5 5

• BGE <lable> : Branch not taken because R1<R2

• BLT <label> : Branch taken because R1<R2

• BMI <label> : Branch taken because result minus (R1-R2)



Example: conditional executionConsider following instructions:

MOVS R0,R1MOVEQS R0,R2

MOVEQ R0,R3Explanation:• The first instruction moves content of register R1 into R0

and chan e N and Z fla de endin on value stored inR0.

• Second instruction will transfer R2 to R0 only if zero flagis set. That means if during first instruction R1=0, secondinstruction will execute. If second instruction is executed itwill change N and Z flag depending on value stored in R2.

• Third instruction transfer register R3 to R0 only if zero flagis set. That means R2=0 during second instruction. Thus,third instruction will be executed only of R1 and R2 bothwere 0.



Program: To add elements of array

_ start:MOV R1,#3 ;total 3 elements in arrayLDR R2,=vect ;Assign address of vectorMOV R0,#0 ; Reset R0 to store result

Loop: LDR R3,[R2] ; R3=vect[i], ,

ADD R2,R2,#4 ; R2 moves to next elementSUB R1,R1,#1 ; Decrement counterCMP R1,#0 ; See whether R1=0 or not

BNE Loop.data

vect: .word 1,5,10,15

.end



Software Interrupt• SWI instruction

– Forces CPU into supervisor mode – Usage: SWI # n

Maximum 2Maximum 2 2424 callscalls

Suitable for running privileged code andSuitable for running privileged code andmaking OS callsmaking OS calls

Cond Opcode Ordinal31 28 27 24 23 0



Thumb Instruction Set• Compressed form of ARM

– Instructions stored as 16-bit, – Decompressed into ARM instructions and

Executed

• Lower performance (ARM 40% faster)• Higher density (THUMB saves 30% space)

• Optimal – “interworking ” (combining two sets) – compiler supported



THUMB Instruction Set• More traditional:

– No condition codes – Two-address data processing instructions

• Access to R0 – R8 restricted to – MOV , ADD , CMP

• PUSH/POP for stack manipulation – Descending stack (SP hardwired to R13)



THUMB Instruction Set• No MSR and MRS ,

must change to ARM to modify CPSR(change using BX or BLX )

• ARM entered automatically after RESETor entering exception mode• Maximum 255 SWI calls



Exercise• Visit website: www.arm.com for latest

updates• Find out what is CAN and utilization of

• List ARM based microcontrollers• What are the features of ARM based

Phillips microcontroller LPC-2129 and LPC-2294?



Thank you ….

arm instruction prgoramming

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