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Approaches to Approaches to design entry design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) [email protected] [email protected] www.testgroup.polito.it Lecture 2.4

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Page 1: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

Approaches to Approaches to design entrydesign entry

Approaches to Approaches to design entrydesign entry

Paolo PRINETTOPolitecnico di Torino (Italy)

University of Illinois at Chicago, IL (USA)

[email protected] [email protected]

www.testgroup.polito.it

Lecture

2.4

Page 2: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

2 2.4

Goal

This lecture introduces the approaches used, during the overall design cycle, to capture the information items related to the design itself, in an Electronic Design Automation (EDA) system.

Page 3: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

3 2.4

Homework

No particular homework is foreseen

Page 4: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

4 2.4

Prerequisites

Lecture # 2.3

Page 5: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

5 2.4

Further readings

No particular suggestion

Page 6: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

6 2.4

Design entryDesign entry

Design Entry (or Design Capture) is the set of steps to go through to enter a design description into an EDA system.

DesignDesignentryentry

Page 7: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

7 2.4

CompilerCompilerCompilerCompiler

DescriptionDescriptionDescriptionDescription

Description translation

Libraries

DesignDesignData BaseData Base

Page 8: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

8 2.4

DesignDesignentryentry

Approaches

Page 9: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

9 2.4

DesignDesignentryentry

Approaches

TextualTextual

Page 10: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

10 2.4

DesignDesignentryentry

Approaches

GraphicGraphicTextualTextual

Page 11: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

11 2.4

DesignDesignentryentry

Approaches

GraphicGraphic

Based on ad-hoc

graphical languages

TextualTextual

Page 12: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

12 2.4

Classification

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

Page 13: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

13 2.4

Classification

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

High LevelHigh LevelGraphicalGraphical

LanguagesLanguages

Page 14: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

14 2.4

High LevelGraphical Languages

Last generation languages that allow the designer to describe the system structure and/or behavior in terms of:

concurrent processes

state transition diagrams

flow-charts

blocks interconnections

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

High LevelHigh LevelGraphicalGraphical

LanguagesLanguages

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

High LevelHigh LevelGraphicalGraphical

LanguagesLanguages

Page 15: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

15 2.4

Example: Statemate

SYSTEM

OFF

WAIT_CMD

A

B

ON

EXECUTING

Y

Z

READ_DATA PROCESS_DATA

RESET

EXECUTE

POWER_OFFPOWER_ON

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

High LevelHigh LevelGraphicalGraphical

LanguagesLanguages

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

High LevelHigh LevelGraphicalGraphical

LanguagesLanguages

Page 16: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

16 2.4

Classification

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

Page 17: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

17 2.4

Classification

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

Schematic Schematic editorseditors

Page 18: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

18 2.4

Schematic Editors

They represent the “traditional” tools to represent system structure in terms of blocks and modules interconnections.

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

Schematic Schematic editorseditors

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

Schematic Schematic editorseditors

Page 19: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

19 2.4

Examplebehavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

Schematic Schematic editorseditors

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

Schematic Schematic editorseditors

Page 20: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

20 2.4

Example of hierarchy

Page 21: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

21 2.4

Example of hierarchy

Page 22: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

22 2.4

Example of hierarchy

Page 23: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

23 2.4

Pro’s & Con’s

Easily to use

Low productivity

Applicability restricted to the structural domain, only.

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

Schematic Schematic editorseditors

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

Schematic Schematic editorseditors

Page 24: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

24 2.4

Status

In 1991, the 85% of industrial designs was based on schematics

Today, most industrial designs are based on

VHDL

Verilog

C++

Java

...

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

Schematic Schematic editorseditors

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

Schematic Schematic editorseditors

Page 25: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

25 2.4

Classification

Representationdomains

behavior structure physical

system

RT

logic

device

Abstractionlevels

Page 26: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

26 2.4

Classification

Representationdomains

behavior structure physical

system

RT

logic

device

Abstractionlevels LayoutLayout

toolstools

Page 27: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

27 2.4

Layout tools

Used today mostly to develop cells libraries

Basis elements are usually represented symbolically (symbolic layout tool).

behavior structure physical

system

RT

logic

device

Abstractionlevels LayoutLayout

toolstools

behavior structure physical

system

RT

logic

device

Abstractionlevels LayoutLayout

toolstools

Page 28: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

28 2.4

Example

IN OUT

+V +V

GND GND

MN

MP

[P.L. Civera]

behavior structure physical

system

RT

logic

device

Abstractionlevels LayoutLayout

toolstools

behavior structure physical

system

RT

logic

device

Abstractionlevels LayoutLayout

toolstools

Page 29: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

29 2.4

DesignDesignentryentry

Approaches

GraphicGraphicTextualTextual

Page 30: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

30 2.4

DesignDesignentryentry

Approaches

GraphicGraphicTextualTextualBased on ad-hoc

programming languages, particularly tailored to the

descriptions of digital systems:

(Hardware Description (Hardware Description Languages Languages or HDL)HDL)

Page 31: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

31 2.4

Problems in Hardware description

Hierarchy

Concurrency

Communications among modules

Timing

Propagation delays

Different domains and abstraction levels

Technology peculiarities

Constraints descriptions

Page 32: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

32 2.4

Application areas

behavior structure physical

system

RT

logic

device

Abstractionlevels

Representationdomains

Page 33: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu

33 2.4

Pro’s & Con’s

Allow mixed-level (system, RT, logic, device) and mixed-domain (behavior, structure, physical) descriptions

Feed EDA & Synthesis tools

Allow a “natural” design documentation

Standards exist (e.g., VHDL, Verilog)

Dramatically improve productivity

Are usually harder to learn than schematic editors.

Page 34: Approaches to design entry Paolo PRINETTO Politecnico di Torino (Italy) University of Illinois at Chicago, IL (USA) Paolo.Prinetto@polito.it Prinetto@uic.edu