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M.H. Perrott Analysis and Design of Analog Integrated Circuits Lecture 12 Feedback Michael H. Perrott March 11, 2012 Copyright © 2012 by Michael H. Perrott All rights reserved.

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Page 1: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Analysis and Design of Analog Integrated CircuitsLecture 12

Feedback

Michael H. PerrottMarch 11, 2012

Copyright © 2012 by Michael H. PerrottAll rights reserved.

Page 2: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Open Loop Versus Closed Loop Amplifier Topologies

Open loop – want all bandwidth limiting poles to be as high in frequency as possible

Closed loop – want one pole to be dominant and all other parasitic poles to be as high in frequency as possible

2

VoutZsrc

Vsrc

SourceAmp VoutZsrc

Vsrc

SourceAmp

Zf

Open Loop Closed Loop

Vout/Vin

(dB)

w (rad/s)wbw w1 w2

Vout/Vin

(dB)

w (rad/s)wbw w1 w2

VinVin

Page 3: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Consider an Open Loop Integrator

Parameterize integrator in terms of its unity gain frequency, wunity rad/s- Define H(s) = wunity/s- Note that |H(wunity)| = 1

3

Vout

Vout/Vin(dB)

w (rad/s)wunity

sVin

wunity

0 dB

H(w)

H(s)Vin Vout

Page 4: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Now Surround the Integrator with a Feedback Path

The feedforward path is H(s) = wunity/s The feedback path is formed by Z1 and Z2

Derivation of closed loop transfer function:

4

VoutZ1

Z2

Vx

Vin

Vout/(Vin-Vx)(dB)

w (rad/s)wunity

0 dB

H(w)

20log

H(s)

Vout − VxZ2

=Vx − 0Z1

and Vout = H(s)(Vin − Vx)

⇒ VoutVin

=H(s)

1 + Z1/(Z1 + Z2)H(s)

Page 5: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Observations of Impact of Feedback

Define = Z1/(Z1+Z2) and rewrite transfer function as:

At low frequencies: At high frequencies:

5

Vout/Vin

w (rad/s)wunity

0 dB

H(w)

20log(1/β)

wbw

20log

VoutZ1

Z2

Vx

Vin

H(s)

VoutVin

=H(s)

1 + Z1/(Z1 + Z2)H(s)=

H(s)

1 + β ·H(s)

¯̄̄̄VoutVin

¯̄̄̄s→0

=∞

1 + β ·∞ =1

β

¯̄̄̄VoutVin

¯̄̄̄s→∞

= |H(w)|

(since |β ·H(w)| ¿ 1)

Page 6: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Vout/Vin

w (rad/s)wunity

0 dB

H(w)

20log(1/β)

wbw

20log

VoutZ1

Z2

Vx

Vin

H(s)

H(s)

β

Vin Vout

General View of Feedback

Closed loop transfer function:

- This is called Black’s formula

6

VoutVin

=H(s)

1 + β ·H(s)

¯̄̄̄VoutVin

¯̄̄̄s→∞

= |H(w)|

At low frequencies: At high frequencies:¯̄̄̄VoutVin

¯̄̄̄s→0

=1

β

Page 7: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

The feedback path sets the closed loop gain at low frequencies- Assumes the open loop gain is large at low frequencies- Implies that accurate closed loop gain can be achieved

at low frequencies despite variations in open loop gain The feedback path also influences the closed loop

bandwidth

Vout/Vin

w (rad/s)wunity

0 dB

H(w)

20log(1/β)

wbw

20log

H(s)

β

Vin Vout

General Observations of Feedback

7

VoutVin

=H(s)

1 + β ·H(s)

Page 8: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

The low frequency gain is:

The bandwidth roughly corresponds to:

Vout/Vin

w (rad/s)wunity

0 dB

H(w)

20log(1/β)

wbw

20log

H(s)

β

Vin Vout

Gain Bandwidth Product for Closed Loop Systems

8

VoutVin

=H(s)

1 + β ·H(s)

|H(wbw )| ≈1

β

¯̄̄̄VoutVin

¯̄̄̄s→0

=1

β

⇒¯̄̄̄wunitywbw

¯̄̄̄≈ 1

β⇒ wunity =

1

β· wbwFor H(s) =

wunitys

Closed loop systems exhibit constant gain-bandwidth productset by the unity gain frequency of the open loop amplifier

Page 9: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

The low frequency gain is:

The bandwidth roughly corresponds to:

Gain bandwidth product is wunity:

Vout/Vin

w (rad/s)wunity

0 dB

H(w)

20log

H(s)

β = 1

Vin Vout

Example: Unity Gain Amplifier

9

VoutVin

=H(s)

1 +H(s)

|H(wbw )| ≈ wunity

¯̄̄̄VoutVin

¯̄̄̄s→0

= 1

Unity gain closed loop amplifiers maximize theclosed loop bandwidth assuming closed loop gain ≥ 1

1 · wunity = wunity

Page 10: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Let us now model H(s) as:

To first order, the closed loop bandwidth and gain are relatively unchanged

Vout/Vin

w (rad/s)wunity

0 dB

H(w)

20log

H(s)

β = 1

Vin Vout

wdominant

20log(K)

Issue: Open Loop Amplifiers have Finite DC Gain

10

VoutVin

=H(s)

1 +H(s)

H(s) =K

1 + s/wdominant

What is the impact of having finite, open loop, DC gain?

Page 11: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

H(s) =K

1 + s/wdominant

For unity gain configuration of closed loop amplifier:

We see that finite open loop DC gain leads to a slight reduction of the closed loop DC gain- We want K >> 1 for the unity gain closed loop amplifier

Vout/Vin

w (rad/s)wunity

0 dB

H(w)

20log

H(s)

β = 1

Vin Vout

wdominant

20log(K)

Further Examination of Finite, Open Loop, DC Gain

11

VoutVin

=H(s)

1 +H(s)

¯̄̄̄VoutVin

¯̄̄̄s→0

=H(s)

1 +H(s)

¯̄̄̄s→0

=K

1 +K=

1

1 + 1/K

Page 12: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

H(s) =K

1 + s/wdominant

For general configuration of closed loop amplifier:

Finite open loop DC gain still leads to reduction of closed loop DC gain- We want K >> 1/ in this case- We will see implications of this issue later in the class

Vout/Vin

w (rad/s)wunity

0 dB

H(w)

20log(1/β)

wbw

20log

H(s)

β

Vin Vout20log(K)

More General View of Finite, Open Loop, DC Gain

12

VoutVin

=H(s)

1 + β ·H(s)

¯̄̄̄VoutVin

¯̄̄̄s→0

=K

1 + β ·K =

µ1

β

¶1

1 + (1/β)/K

Page 13: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Practical amplifiers have non-dominant poles, too:

- Of course, there can be multiple parasitic poles and also zeros

A key issue of such parasitic poles is their influence on the stability of the closed loop amplifier

Vout/Vin

w (rad/s)

H(w)

20log(1/β)

wbw

20log

H(s)

β

Vin Vout20log(K)

wp

H(s) =

µK

1 + s/wdominant

¶µ1

1 + s/wp

The Issue of Parasitic Open Loop Poles

13

VoutVin

=H(s)

1 + β ·H(s)

Page 14: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

We define the open loop response, A(s), as:

Note that the unity gain frequency, w0 , of A(w) is approximately the same as the closed loop bandwidth, wbw

- Looking at the plot above, we can see that the intersection of |H(w)| and 1/ corresponds to the closed loop bandwidth, wbw

|A(w0)| = 1 ⇒ β · |H(w0)| = 1 ⇒ |H(w0)| = 1/β

Vout/Vin

w (rad/s)

H(w)

20log(1/β)

wbw

20log

H(s)

β

Vin Vout20log(K)

wp

A(s) = β ·H(s)

Key Tool for Assessing Stability: Open Loop Response

14

VoutVin

=H(s)

1 + β ·H(s)

Page 15: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Stability Analysis Based on Phase Margin of A(w)

Phase margin is a key metric when examining the stability of a system- Phase margin is defined as 180° + phase{A(w0)}

w0 corresponds to the unity gain frequency of the open loop response (i.e., |A(w0)| = 1)

w0 is approximately the same as the closed loop bandwidth, wbw- Phase margin must be greater than 0 degrees for the

closed loop system to be stable Typically want phase margin to be greater than 45°

Key skill: you must be able to plot Bode plots in both magnitude and phase!

15

Page 16: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Review of Bode Plot Basics

Example:

- Log of magnitude (dB):

Taking the log allows the poles and zeros to be plotted separately and then added together

- Phase:

Phase of poles and zeros can also be plotted separately and then added together

16

A(w) =1 + jw/wz

(1 + jw/wp1)(1 + jw/wp2)

20 log |A(w)|= 20 log |1 + jw/wz |− 20 log |1 + jw/wp1|− 20 log |1 + jw/wp2|

6 A(w)

= 6 (1 + jw/wz)− 6 (1 + jw/wp1)− 6 (1 + jw/wp2)

Page 17: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Review: Plotting the Magnitude of Poles

Plot the magnitude response of pole wp1

- For w << wp1:

- For w >> wp1:

17

20 log |Ap1(w)| = 20 log¯̄̄̄

1

1 + jw/wp1

¯̄̄̄= −20 log |1 + jw/wp1|

20 log |Ap1(w)| ≈ −20 log |1| = 0

20 log |Ap1(w)| ≈ −20 log |w/wp1|

ω

20log|Ap1(ω)|

0 dB

-20 dB/decadeωp1

Page 18: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Plotting the Phase of Poles

Plot the phase response of pole wp1

- For w << wp1:

- For w = wp1:

- For w >> wp1:

18

6 Ap1(w) ≈ − arctan (0) = 0◦

ω

Ap1(ω)

0o ωp1ωp1/10 ωp1∗10

-45o

-90o

6 Ap1(w) = − 6 (1 + jw/wp1) = − arctan (w/wp1)

6 Ap1(w) ≈ − arctan (1) = −45◦

6 Ap1(w) ≈ − arctan (∞) = −90◦

Page 19: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Review: Plotting the Magnitude of Zeros

Plot the magnitude response of zero wz

- For w << wz:

- For w >> wz:

19

20 log |Az(w)| = 20 log |1 + jw/wz|

20 log |Az(w)| ≈ 20 log |1| = 0

20 log |Az(w)| ≈ 20 log |w/wz |

ω

20log|Az(ω)|

0 dB

20 dB/decade

ωz

Page 20: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Plotting the Phase of Zeros

Plot the phase response of zero wz

- For w << wz:

- For w = wz:

- For w >> wz:

20

6 Az(w) ≈ arctan (0) = 0◦

ω0oωzωz/10 ωz∗10

45o

90oAz(ω)

6 Az(w) = 6 (1 + jw/wz) = arctan (w/wz)

6 Az(w) ≈ arctan (1) = 45◦

6 Az(w) ≈ arctan (∞) = 90◦

Page 21: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Example of Closed Loop Stability Evaluation

Consider the case where:

- This implies that:

21

Vout/Vin

w (rad/s)

H(w)

20log(1/β)

wbw

20log

H(s)

β

Vin Vout

wp

VoutVin

=H(s)

1 + β ·H(s)

H(s) =

µK

s

¶µ1

1 + s/wp

A(s) = β

µK

s

¶µ1

1 + s/wp

Page 22: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Phase Margin Versus Open Loop Gain

Note the closed loop pole locations versus open loop gain- Is the closed loop system unstable for any case above?

22

-90o

-180o

-120o

-150o

20log|A(f)|

f

angle(A(f))

Open loopgain

increased

0 dB

PM = 33o for C

PM = 45o for B

PM = 59o for A

A

A

A

B

B

B

C

C

C

Evaluation ofPhase Margin

Closed Loop PoleLocations

Dominantpole pair

fp

Re{s}

Im{s}

0

Page 23: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Corresponding Closed Loop Behavior

Frequency response sees more peaking with higher open loop gain- How does this relate to the movement of the closed loop pole

locations? Step response see more ringing with higher open loop gain

- How does this relate to the closed loop frequency response? 23

5 dB0 dB

-5 dB

f

A

C

fp

B

Closed Loop Frequency Response

1.4

0

1

0.6

t

AB

C

Closed Loop Step Response

Page 24: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Some Key Observations

We have seen that increasing the open loop gain of A(w)leads to higher closed loop bandwidth- How is this consistent with the statement that increasing

closed loop gain leads to lower closed loop bandwidth? As an exercise, consider the impact of the following:

- Keep unchanged and increase the open loop gain of H(w)- Keep H(w) unchanged and increase

24

Vout/Vin

w (rad/s)

H(w)

20log(1/β)

wbw

20log

H(s)

β

Vin Vout

wp

VoutVin

=H(s)

1 + β ·H(s)A(s) = β ·H(s)

Page 25: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Example 2 of Closed Loop Stability Evaluation

Consider the case where:

- This implies that:

25

Vout/Vin

w (rad/s)

H(w)

20log(1/β)

wbw

20log

H(s)

β

Vin Vout

wp1,wp2,wp3

VoutVin

=H(s)

1 + β ·H(s)

H(s) =

µK

s

¶µ1

1 + s/wp1

1

1 + s/wp2

1

1 + s/wp3

A(s) = β

µK

s

¶µ1

1 + s/wp1

1

1 + s/wp2

1

1 + s/wp3

Page 26: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Phase Margin Versus Open Loop Gain

Note the closed loop pole locations versus open loop gain- Is the closed loop system unstable for any case above?

26

-90o

-315o

-165o

-180o

-240o

20log|A(f)|

ffp3

angle(A(f))

Open loopgain

increased

0 dB

PM = 51o for B

PM = -12o for C

PM = 72o for A

Non-dominantpoles

Dominantpole pair

ABC

B

A

A

B

C

C

Evaluation ofPhase Margin

Closed Loop PoleLocations

fp1 fp2

Re{s}

Im{s}

0

Page 27: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Corresponding Closed Loop Behavior

Frequency response again sees more peaking with higher open loop gain- How does this relate to the movement of the closed loop pole

locations? Step response ringing grows for high open loop gain

- How does this relate to the closed loop pole locations? 27

0 dB

Closed Loop Frequency Response Closed Loop Step Response

1

TimeFrequency

A

C

B

CB

A

Page 28: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott

Open Loop Versus Closed Loop Amplifier Topologies

Now that we understand the phase margin criterion, can you explain why amplifiers designed to be within a closed loop system should have one dominant pole that is much lower in frequency than the parasitic poles?

28

VoutZsrc

Vsrc

SourceAmp VoutZsrc

Vsrc

SourceAmp

Zf

Open Loop Closed Loop

Vout/Vin

(dB)

w (rad/s)wbw w1 w2

Vout/Vin

(dB)

w (rad/s)wbw w1 w2

VinVin

Page 29: Analysis and Design of Analog Integrated Circuits …vppsim.com/CircuitLectures/Lecture12.pdf · M.H. Perrott Open Loop Versus Closed Loop Amplifier Topologies Open loop – want

M.H. Perrott 29

Summary

Feedback systems offer the benefit of accurate gain at low frequencies- Assumes accurate feedback and high open loop DC gain- Gain-bandwidth product of the closed loop system

equals wunity of the open loop amplifier Accuracy of the closed loop DC gain is reduced with

lower open loop DC gain- Want the open loop DC gain to be much higher than the

desired closed loop DC gain for reasonable accuracy Stability of the closed loop system is often evaluated

using the phase margin criterion- Examines the phase at unity gain frequency of the open

loop response, A(w0) = · H(w0), where |A(w0)| = 1 w0 is approximately the same as the closed loop

bandwidth, wbw