analog circuits ii lab manual

7/25/2019 Analog Circuits II Lab Manual

http://slidepdf.com/reader/full/analog-circuits-ii-lab-manual 1/47

KIT’s COLLEGE OF ENGINEERINGGokul Shirgaon, Kolhapur- 416 !4

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.N.LOG CIRCITS-II

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Gokul Shirgaon, Kolhapur- 416 !4

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CONTENTS

E@"T

NON.0E OF TAE E@"ERI0ENT

".GE

NO

01 Design of RC phase shift oscillator using BJT 01

02 Design of Colpitts oscillator using BJT 05

03 Design of Hartley oscillator using BJT 08

04 Design of sta!le "ulti#i!rator$ 12

05 Design of "onosta!le "ulti#i!rator using BJT 1%

0% Designs of &ch"itt trigger using BJT$ 1'

0( Design an) fre*uency response of t+o stages RC couple) a"plifier$ 22

08 Design an) fre*uency response of #oltage series fee)!ac, a"plifier$ 2%

0' Design an) fre*uency response of current &eries fee)!ac, a"plifier using BJT$ 32

10 Design an) fre*uency response of )irect couple) a"plifier$ 3(

11 Design of #oltage regulator using -.31($

12 Design of #oltage regulator using /C(23$



Analog Circuits-II Laboratory Manual -

E&No#$1 RC "A.SE SAIFT OSCILL.TOR

.I0#

Design RC phase shift oscillator using BJT +hich generates repetiti#e +a#efor" &inusoi)al

signal of fre*uency H$O/BECTIE#

To generate a sinusoi)al +a#efor" of )esire) fre*uency using RC phase shift oscillator$

CO0"ONENTS REDIRE*#

Sl No Co9pon+n's *+'ails Sp+=i7i=a'ion D'

1$ Transistor

2$ Capacitors

3$ Resistors

DC &upply CR6 +ith 7ro!e

CIRCIT *I.GR.0#

TAEOR

n oscillator is a circuit that generates the sinusoi)al oscillation output at fre*uency ranging fro"

au)io !an) up to se#eral 9H$ /n a))ition the fre*uency "ay !e #aria!le$ :or lo+er fre*uencies the

oscillator usually in#ol#es RC co"ponent for fre*uency selection !ut for higher fre*uencies it relyupon -C resonant circuits$

Depart"ent of ;lectronics < Teleco""unication = /TC6; 1

Q11

2

3

R

1k

VCC

A B C

R1

R2

RC

RE CE

Cc

CC

: 0anual - $6ESL!;

CC C

RR

D




R+uir+9+n' 7or os=illa'ion#

1$ for linear oscillation i$e$ oscillation +hich are relati#ely free fro" )istortion the pro)uct of

fee)!ac, factor , an) # shoul) !e greater than one

K.2 H 1

This con)ition is calle) the Bar,hausen criteria of oscillation$

2$ The total phase shift of the circuit shoul) !e ero$ The output shoul) !e gi#en in phase +ith

the input i$e$ a positi#e fee)!ac,$

practical circuit of phase shift oscillator using >7> transistor in co""on e"itter

configuration is as sho+n in fig$ R- is a loa) resistor in the collector circuit$ R!1 an) R!2 are

!ias resistors$ The phase shift of signal at input gets re#erse) +hen the a"plifier a"plifies it$

The output of the a"plifier goes to the fee)!ac, net+or,$ The fee)!ac, net+or, consists of

the three i)entical RC section pro#i)es a phase shift of %0 o each$ Thus the total of the

fee)!ac, net+or, pro#i)es 3 ? %0 @ 180 phase shift$ The output of the fee) !ac, net+or, isthe output of this net+or, is in phase +ith the original input signal to the a"plifier$ /f the

con)ition # A @1 is "et oscillation +ill !e sustaine)$

The fre*uency at +hich the RC net+or, pro#i)es eactly 180o phase shift is gi#en !y

1

: @

2∏ RC %4 RC ER

This is the fre*uency of oscillation$ lso it can !e sho+n that at this fre*uency the

fee)!ac, factor of RC net+or, is @ 1E2' fro" the Bar,hausenFs criteria +e get # G 2'This "eans that the gain # of the a"plifier "ust !e greater than 1E2' only then the oscillation can !e

starte)$

.2an'ag+s o7 RC phas+ shi7' os=illa'or#

1$ /t )oes nee) transfor"er an) in)uctor$ &o less !ul,y$

2$ Circuit is cheap an) si"ple as contains only resistors an) capacitors$

3$ a#efor" o!taine) fro" circuit is eceptionally pure an) sinusoi)al since core saturation

effect an) har"onic )istortion are a!sent as no transfor"er is use)$

4$ This circuit can !e use) to pro)uce #ery fe+ fre*uencies$

5$ /t pro#i)es goo) fre*uency sta!ility$

*isa2an'ag+s o7 RC phas+ shi7' os=illa'or#

1$ /t is )ifficult for circuit to start the oscillation as fee)!ac, is generally s"all$ This is

!ecause of reactance of R < C$

2$ Due to the s"all fee)!ac, it gi#es the s"all output$

3$ Circuit nee)s high #oltage !attery$ /t is !ecause of s"all fee)!ac, to pro#i)e sufficient

output$

4$ /t cannot !e use) for higher fre*uencies$

5$ /t has high gain$





"ROCE*RE#

1$ .a,e the connections as sho+n in the circuit )iagra"$

2$ Chec, the circuit for !iasing$

3$ )Iust the 1, potentio"eter to get sinusoi)al +a#efor" at the output$4$ To "easure the phase shift

0+'ho 1#

Connect the channel 1 of the CR6 to point D an) channel 2 to point $ e +ill get t+o sine

+a#es +ith a phase )ifference$ .easure the )ifference !y con#erting the ti"e into angle$

0+'ho #

a Connect channel 1 to point D an) channel 2 to point $

7ress the ?K ,no! an) "easure the phase shift$

7hase angle La @ θ @&inM1

aE! appro$ @%00

! Connect channel 2 to point B the graph is as sho+n

θ @ &inM1aE!N 7hase angle L! @1800M θ appro$ @ 1200

C Connect channel 2 to point C$

The transfer function +ill !e al"ost a straight line an) θ @ 00 an) therefore phase

angle Lc @1800 M 00 @ 1800

J.EFOR0#

0 t

f @ 1 E T


!

a

!

a




RESLT# Thus a RC phase shift oscillator is )esigne) constructe) an) teste)$

Theoretical fre*uency fTh @

7ractical fre*uency f7 @

CONCLSION#

ST* DESTION#

1$ ;plain Bar,hausen criteria of oscillations$

2$ >a"e the )ifferent types of oscillator circuits an) "ention their range of fre*uencies$3$ hat is an oscillatorO -ist its typesO

4$ hat are RC oscillatorsO hat are its typesO

5$ hat is the phase shift gi#en !y each RC sectionO





E&No#$ COL"ITT’S OSCILL.TOR

.I0

Design of Colpitts oscillator for a gi#en Ra)io fre*uency of f 0 @ H using BJT$

CO0"ONENTS REDIRE*#


1$ Transistor

2$ Capacitors

3$ Resistors

4$ /n)uctors


CIRCIT *I.GR.0#

TAEOR

n oscillator is a circuit that generates the sinusoi)al oscillation output at fre*uency ranging fro"au)io !an) up to se#eral 9H$ /n a))ition the fre*uency "ay !e #aria!le$ :or lo+er fre*uencies the


R2 C

ERE

BC109

CB

CcR1

Vcc

Rc

P6

Variable1 K Pot

L

GND

C2C1




oscillator usually in#ol#es RC co"ponent for fre*uency selection !ut for higher fre*uencies it rely

upon -C resonant circuits$

Requirement for oscillation:

1 :or linear oscillation i$e$ oscillation +hich are relati#ely free fro" )istortion the pro)uct of

fee)!ac, factor , an) # shoul) !e greater than one Q# G 1

This con)ition is calle) the Bar,hausen criteria of oscillation$

1 The total phase shift of the circuit shoul) !e ero$ The output shoul) !e gi#en in phase +ith the

input i$e$ a positi#e fee)!ac,$

practical circuit of Colpitts oscillator using >7> transistor in co""on e"itter

configuration is as sho+n in fig$ R - is a loa) resistor in the collector circuit$ R 1 an) R 2 are !ias

resistors$ The phase shift of signal at input gets re#erse) +hen the a"plifier a"plifies it$ The output of

the a"plifier goes to the fee)!ac, net+or,$ The fee)!ac, net+or, is )esigne) using t+o capacitors

an) an in)uctor$ Poltage across C2 is 180 out of phase +$r$t$ #oltage across C1 an) thus 180 phaseshift is pro#i)e) !y the fee)!ac, net+or,$ Ho+e#er re"aining 180 phase shift is pro#i)e) !y C;

stage so that total phase shift is in the loop is 0 or 3%0$ /t uses in)uctor in parallel +ith series of

capacitor an) acts as filter to pass the )esire) oscillating fre*uency an) !loc, all other fre*uencies$

t resonance ?- @ ?CT

here ?CT is the reactance of the capacitance connecte) in parallel

+ith in)uctance cell$

This gi#es the fre*uency of oscillation

f osc @ 1E2S -CT 1here CT @ C1 C2

The -C fee)!ac, net+or, sho+s the attenuation fro" a"plifier output an) is )ue to potential )i#i)er

effects of - an) C2$ Therefore gain of fee)!ac, net+or, is

@ P:EP6 @ ?C1E ?-M?C1 2

t 180 phase shift the in)ucti#e is #ery s"all )ue to s"all resistance of coil i$e$ U@ V-ER is large$

Therefore ?-M?C1 W ?C2 3

:ro" e*n$ 2 @ P:EP6 @ ?C2E?C1@ C2EC1

&ince ?C2 @ 1E2SfC2 an) ?C1 @1E2SfC1:or the re*uire) oscillation the loop gain "ust !e greater than unity$

Therefore P A 1E @ C1EC2

"ROCE*RE#

1$ Rig up the circuit as sho+n in the circuit )iagra"$2$ Before connecting the fee)!ac, net+or, chec, the circuit for !iasing con)itions i$e$ chec,

PC; an) PR;$3$ fter connecting the fee)!ac, net+or,$ Chec, the output$4$ Chec, for the sinusoi)al +a#efor" at output$ >ote )o+n the fre*uency of the output

+a#efor" an) chec, for any )e#iation fro" the )esigne) #alue of the fre*uency$5$ To get a sinusoi)al +a#efor" a)Iust 1 Ω potentio"eter$

%$ DCBED/B can !e #arie) to #ary the fre*uency of the output +a#efor"$

Depart"ent of ;lectronics < Teleco""unication = /TC6; %




J.EFOR0#

Po

0

t

T

∴ fre*uency fo @ 1ET

RESLT# Thus a Colpitts oscillator is )esigne) constructe) an) teste)$



CONCLSION#

ST* DESTION#

1$ ;plain Bar,hausenFs criteria of oscillations$2$ >a"e the )ifferent types of oscillator circuits an) "ention their range of fre*uencies$3$ hat type of fee)!ac, is use) in 6scillator circuitO4$ hat are the applications of -C oscillatorsO5$ hat type of fee)!ac, is use) in oscillatorsO%$ hat is the epression for the fre*uency of oscillations of colpitts oscillatorO($ /s an oscillator DC to C con#erterO8$ hat is the loop gain an) loop phase shift of an oscillatorO'$ Ho+ )oes colpitts )iffer fro" HartleyO10$ hich pair in circuit for"s sta!iliing circuitO

11$ hat is the function of input an) output capacitorO12$ hat is the con)ition for sustaine) oscillations in this oscillatorO13$ 6utput capacitor acts as aO

Depart"ent of ;lectronics < Teleco""unication = /TC6; (




E&No#$4 A.RTLE OSCILL.TOR

.I0

Design of Hartley oscillator for a gi#en Ra)io fre*uency of f 0 @ H using BJT$

CO0"ONENTS REDIRE*#


1$ Transistor

2$ Capacitors

3$ Resistors

4$ /n)uctors


CIRCIT *I.GR.0#

TAEOR

6scillators are )e#ices +hich generate oscillations$ The fre*uency of oscillations )epen)s on

the fee)!ac, net+or,$ :ee)!ac, "ay !e of t+o types na"ely positi#e an) negati#e$ /n positi#e

fee)!ac, the fee)!ac, signal is applie) in phase +ith the input signal thus increasing it$ /n negati#e

fee)!ac, the fee)!ac, signal is applie) out of phase +ith the input thus re)ucing it$ The fee)!ac,

use) in oscillators is positi#e fee)!ac,$ The oscillators +or, on the principle of Bar,hausen criteria$This states that for sustaine) oscillations





i -oop gain #β "ust !e e*ual to 1$

ii The phase shift aroun) the loop "ust !e 0 )eg of 3%0 )eg$

Here # is the gain of the a"plifier an) β is the attenuation of the fee)!ac, net+or,$ Consi)er the

fee)!ac, net+or, sho+n in the fig 1 !elo+$ ssu"e an a"plifier +ith input signal Pin$ The output

signal P6 +ill !e 180 )eg out of phase +ith Pin$ &o to get an in phase output the fee)!ac, net+or, pro#i)es 180M)eg phase shift$ Therefore the output P f fro" the fee)!ac, net+or, can !e "a)e in

phase an) e*ual in a"plitu)e to Pin an) Pin can !e re"o#e)$ ;#en then the oscillations continue$

7ractical oscillations )o not nee) any input signal to start oscillations$ They are selfMstarting )ue to

ther"ally pro)uce) noise in resistors an) other co"ponents$ 6nly one fre*uency f o of noise

satisfies Bar,hausen

criteria an) the circuit oscillates +ith that fre*uency$ The "agnitu)e of f o ,eeps on increasing each

ti"e it goes aroun) the loop$ The a"plification of fo is li"ite) !y circuitFs o+n nonMlinearities$

Therefore to start oscillations #β A 1 an) to sustain it the loop gain #β @ 1$

:ig 1$

The fee)!ac, net+or, use) here consists of - an) C$ Consi)er the circuit sho+n !elo+ fig 2$

This circuit consists of - an) C in parallel$ The capacitor stores energy in its electric fiel) +hene#er

there is #oltage across it an) the in)uctor stores energy in its "agnetic fiel) +hene#er there is current

through it$ /nitially let us assu"e that the capacitor has charge) to P #olts$ hen & is close) c@ 0$

hen & is close) at t @ t0 capacitor starts charging through the in)uctor$ Thus a #oltage gets !uilt up

across the in)uctor )ue to the change in current through it$ /f the capacitor +as change) +ith the

polarity as sho+n in the fig 2 the current starts flo+ing fro" the positi#e plate of the capacitor to the

negati#4 plate of the capacitor$ s sho+n the #oltage across the capacitor re)uces )uring the )ischarge

ti"e # re)uces an) / increases$ t ti"e t1 # +ill !e 0 an) / +ill !e "ai"u" as c is fully )ischarge)

the capacitor charges li,e sinusoi)al oscillations$ Thus the circuit oscillates +ith the fre*uency

fo @ 1E 2π√-C

The Hartley oscillator consists of t+o in)uctors an) a capacitor$ The resonant fre*uency fo for Hartley

oscillator is

fo @1E 2π √-e*C MMMMMM+here -e* @ -1 -2$

Depart"ent of ;lectronics < Teleco""unication = /TC6; '

L C

i

+

-

S t = t o

v

B

A vV i n

V f

V o

A m p l i f i e r

:ig$2




"ROCE*RE#

1$ Rig up the circuit as sho+n in the circuit )iagra"$

2$ Before connecting the fee)!ac, net+or, chec, the circuit for !iasing con)itions i$e$ chec, PC;an) PR;$

3$ fter connecting the fee)!ac, net+or,$ Chec, the output$

4$ Chec, for the sinusoi)al +a#efor" at output$ >ote )o+n the fre*uency of the output +a#efor"an) chec, for any )e#iation fro" the )esigne) #alue of the fre*uency$

5$ To get a sinusoi)al +a#efor" a)Iust 1 Ω potentio"eter$

%$ DCBED/B can !e #arie) to #ary the fre*uency of the output +a#efor"$

J.EFOR0#

Po

0

t

T

∴ fre*uency fo @ 1ET

RESLT# Thus a Hartley oscillator is )esigne) constructe) an) teste)$



CONCLSION#





ST* DESTION#

1$ ;plain Bar,hausenFs criteria of oscillations$2$ >a"e the )ifferent types of oscillator circuits an) "ention their range of fre*uencies$3$ hat are the applications of -C oscillationsO4$ hat type of fee)!ac, is use) in oscillatorsO5$ hat the epression for fre*uency of oscillationsO

%$ hether an oscillator is )c to ac con#erterO($ hat is the loop gain of an oscillatorO8$ hat is the )ifference !et+een a"plifier an) oscillatorO'$ hat is the con)ition for oscillationsO10$ Ho+ "any in)uctors an) capacitors are use) in Hartley 6scillatorO11$ Ho+ the oscillations are pro)uce) in Hartley oscillatorO10$ hat is the )ifference !et+een )a"pe) oscillations un)a"pe) oscillationsO





E&No#$4 .ST./LE 0LTII/R.TOR

.I0

Design sta!le "ulti#i!rator to run at H fre*uency an) to o!ser#e the response at

!ase an) collector points of the transistors an) plot the"$

CO0"ONENTS REDIRE*#


1$ Transistor

2$ Capacitors

3$ Resistors

4$ Brea) !oar)DC &upply CR6 +ith 7ro!e

CIRCIT *I.GR.0#

0O*EL J.EFOR0S#





TAEOR

The circuit for sta!le .ulti#i!rator is sho+n in figure a!o#e$ &ince capacitor coupling is use) !et+een stages

neither transistor can re"ain per"anently in cut off state$ The circuit has t+o *uasiMsta!le states it "a,estransistor to change continuously !et+een these t+o states$ Therefore asta!le circuit is consi)ere) as an

oscillator an) is use) as a generator of Xs*uare +a#eY an) since it re*uires no triggering signal is itself often a

!asic source of fast +a#efor"s$ s one can see the co"ponents in one half of the circuit are consi)ere) to !e

e*ual to their counterparts in the other half$

a hen the po+er is applie) one transistor +ill con)uct "ore than the other )ue to so"e circuit

i"!alance$ ssu"e U 1 is con)ucting an) U2 is cut off$ Then Pc1 the output of U1is approi"ately ero

#olt an) Pc2 @ Pcc$

! The capacitor C2 +ill no+ starter to charge up through Rc an) !ase e"itter Iunction of U$

c .ean +hile C1 ha) pre#iously charge) up to Pcc through Rc of U1 +hen U2 +as con)ucting$ But no+

+hen U1 con)ucts a path is pro#i)e) for C1 to )ischarge through U1 an) R 1$The initial pulse of

)ischarge current fro" C1 through R 1 "a,es the !ase of U2 su))enly #ery negati#e$ Due to #oltage

)e#elope) across R 1 approi"ately = Pcc +hich causes U2 to go into cut off$

) The charging current of C2 slo+ly ceases as the capacitor charges to Pcc$ U1 is ,ept in the con)ucting

state !y !ase current pro#i)e) fro" Pcc through R 2$ &o +e see that initially that P! 1 is slightly "ore

positi#e !ecause it has t+o currents flo+ing through it$

e The length of the ti"e for +hich U2 is hel) off is )eter"ine) !y the ti"e constant of )ischarging of C 1

through U1$ 6nce the capacitor )ischarges co"pletely it starts to charge in the sa"e )irection an) at

the instant +hen its #oltage reaches the for+ar) !ias #oltage of U2 U2 turns on an) state to con)uct$





f t the sa"e instant C2 is allo+e) to )ischarge through U2 an) R 2 coupling a large negati#e pulse in

the !ase of U1 )ue to #oltage )e#elope) across R2 upon initial )ischarge of C 2$ This turns U1 off

*uic,ly an) collector #oltage Pc1 rises to+ar)s Pcc Ho+e#er this #oltage at collector is less than Pcc

at this instant )ue to #oltage )rop across Rc occurring +hile C1 is recharging$$This is relati#ely short

ti"e !ut it cause a roun)ing of rising e)ge in Pc1$

g U1 is hel) in non con)ucting state for an inter#al )epen)s upon the R 2 an) C2 ti"e constant$ fter +hichU1 !egins to con)uct C1 )ischarges through U1$

/t shoul) !e note) that the turning 6> of the one transistor U2 an) its falling #oltage at the collector per"its the

)ischarging of capacitor +hich )ri#es transistor U1 into cut off$ The rising #oltage at U 1Fs collector Zfee)s !ac,F

to !ase of U2 ten)ing to turn it 6> "ore$ The process is sai) to !e regenerati#e or cu"ulati#e +ith *uit fast

s+itching results$ The length of the ti"e for +hich U1 is hel) off is no+ )eci)e) !y the R2C2 ti"e constant$

The ti"e of the *uasi sta!le states are T1 @ 0$%' R1C1 n) T2 @ 0$%' R2 C2

:or the sy""etric s*uare +a#e R1 C1 @ R2 C2

Therefore total ti"e of s*uare +a#e T @ T1 T2 @ 1$388 RC

The fre*uency of oscillation is gi#en !y f @ 1ET @ 0$(2 E RC

"ROCE*RE#

1$ ll the connections are "a)e as per the circuit )iagra"$

2$ .easure )ifferent #oltages at !ase an) collector points of t+o transistors +$r$t groun) as PC1PC2 PB1 an) PB2$

3$ ll the +a#efor"s are plotte) on the graph sheet the a"plitu)es an) ti"e perio)s are note))o+n$

4$ Perify o!ser#e) fre*uency an) )uty cycle of "ulti#i!rator +ith calculate) one for sy""etrical s*uare+a#e$

5$ Theoretical #alues of a"plitu)es an) ti"e perio)s are co"pare) +ith practical #alues$

RESLT#

CONCLSION#





ST* DESTIONS#1$ Define sta!le state of a transistorO2$ Define se"iMsta!le state of transistorO3$ hat are the other na"es of sta!le .ulti#i!ratorO4$ ;plain the operation of a sta!le .ulti#i!ratorO5$ Ho+ "any sta!le states an) se"iMsta!le states present in the sta!le .ulti#i!ratorO%$ Dra+ the +a#efor"s of PC1 an) PC2 of a sta!le .ulti#i!ratorO($ hat is the for"ula for the theoretical #alue of T in sta!le .ulti#i!ratorO





E&No#$? 0ONOST./LE 0LTII/R.TOR

.I0

Design a "onosta!le "ulti#i!rator using transistors to generate a pulse +i)th an)

to o!ser#e the response at !ase an) collector points of the transistors an) plot the"$

CO0"ONENTS REDIRE*#


1$ Transistor

2$ Capacitors

3$ Resistors


CIRCIT *I.GR.0#

0O*EL J.EFOR0S#

Depart"ent of ;lectronics < Teleco""unication = /TC6; 1%




TAEOR

The circuit )iagra" of .onosta!le .ulti#i!rator is as sho+n in fig$ /t is also calle) as collector to !ase

couple)$ .onosta!le .ulti#i!rator as "ore si"ply the collector couple) "ulti#i!rator$ /t has a per"anent

sta!le state < one *uasi sta!le state$ /n this configuration a triggere) signal is re*uire) to inclu)e a transition

fro" the sta!le state to *uasista!le$ The circuit "ay re"ain in *uasista!le state for a ti"e +hich is #ery long in

co"parison +ith the ti"e of transition !et+een states$ ;#entually it +ill return to fro" the *uasista!le state to

its state no eternal signal !eing re*uire) to in)uce this re#erse transition$ &ince +hen it is triggere) the

circuit returns to its original state !y itself after a ti"e ZTF it is ,no+n as a Zone shotF a Zsingle cycleF a Zsingle

step circuitF or aFuni#i!ratorF$ &ince it generates rectangular +a#efor"s < hence can !e use) to gate other

circuits it is also calle) a Zgating circuitF$ :urther"ore the gate +i)th ZTF is gi#en !y

T@ Rin 2PccMP/ satMPB; sat EPccMPr @ [Rin2RinPccM\PC; sat PB; outE2]E PccMPr

t roo" te"perature PC; sat PB; sat @2#r for either Ce so

T@R/n2@0$%'RR0 C@ 0$%'RC$

&ince Ro for a transistor is saturation is s"all +ith R$ The large Pcc is co"pare) to the function #oltage$ The

!etter is the approi"ation$ The internal T is not particularly sta!le against te"perature #ariation$ The !ase to

e"itter #oltage PB; sat )ecreases as te"perature increases at the rate of a!out 2"#Ec +here as PC; sat has

a te"p coefficient +hich is at opposite sign an) su!stantially s"aller the gate +i)thZtF )ecreases as the

te"perature increases$ The #alue of PCC s"aller is this effect$ e consi)er ho+ the effect of the re#erse

saturation current on the ti"e ZTF of sta!le state )uring the internal +hen U2 is cutMoff a no"inal current / CB6

flo+s out of !ase of transistor of U2$Then the #oltage at the !ase of U2 +ith C )isconnecte) +oul) not !e PCC

!ut /CB6QR $ The initial #oltage PC in the sta!le state is not PCC !ut is PCCM/ CB6QRC +here no+ /CB6 is the

collector current of U1 +hen it is off$

Conse*uently the )rop in #oltage PCC +hen "ulti trigger is o!taine)$ /t has one sta!le an) one *uasi sta!le

state$ /t is also calle) as Zone shotF or Z)elay circuitF or Zuni #i!ratorF$ n eternal trigger signal is re*uire) to !e

applie) to an appropriate in the circuit to cause transition fro" sta!le state to *uasi sta!le state an) after a ti"e

)eter"ine !y the state circuit co"ponents$ /t returns to its original sta!le state an its calle) as .onosta!le

.ulti#i!rator$ .onosta!le .ulti#i!rator has the application in pulse circuitry$ /t "ay !e use) to esta!lish a fie)ti"e inter#al one !eginning an) en) of +hich are "ar,e) !y an a!rupt )iscontinuity in a #oltage +a#efor"$

Depart"ent of ;lectronics < Teleco""unication = /TC6; 1(




The pulse +i)th of .onosta!le .ulti#i!rator is gi#en !y T @ 0$%'3 RC$ Thus !y changing the #alues of RC the

pulse +i)th of .onosta!le .ulti#i!rator can !e a)Iuste)$

"ROCE*RE#

1$ Connect the circuit on the !rea)!oar)$

2$ 9i#e the po+er supply$

3$ 9i#e the trigger pulse$

4$ 6!ser#e the +a#e for" on CR6$

5$ 7lot the graph$

C.LCL.TION ) O/SER.TION#

Cal=ula'ions#

Tgate pulse @ 0$%'3RC@ @

O5s+r2a'ions#

Tgate pulse @ @

CONCLSION#

ST* DESTIONS#1$ Define sta!le state of a transistorO2$ hat is the significance of the ter" .onosta!leO3$ ;plain the ter"s &ta!le Uuasi sta!le unsta!le$4$ hat is the use of co""utating capacitorsO5$ hile gi#ing the trigger for the transistor Transistor to !e s+itche) fro" 6> to 6:: or fro" 6:: to

6> stateO Justify your ans+er$%$ hat are the other na"es of .onosta!le .ulti#i!ratorO($ Ho+ "any sta!le an) se"i sta!le states present in the .onosta!le .ulti#i!ratorO8$ ;plain the operation of .onosta!le .ulti#i!ratorO'$ hat is the theoretical #alue of T O10$ hat is the na"e of !ase capacitor an) +hat is the purpose of !ase capacitorO





E&No#$6 SCA0ITT TRIGGER

.I0

To stu)y an) Design &ch"itt trigger circuit$

CO0"ONENTS REDIRE*#


1$ Transistor

2$ Capacitors

3$ Resistors

4$ Brea) !oar)


CIRCIT *I.GR.0#

0O*EL J.EFOR0S#

Depart"ent of ;lectronics < Teleco""unication = /TC6; 1'




TAEOR

&ch"itt trigger is generally !ista!le circuit$ /t is also calle) as e"itter = couple) !inary$ The circuit

)iagra" sho+s &ch"itt trigger using transistor U1 < U2$ This circuit is an a"plitu)e co"parator to

"ar, the "o#e"ent at +hich an ar!itrary +a#e for" attains a particular reference le#el$ The eistence

of any t+o states result fro" the fact that the :or+ar) Biasing is incorporate) into the circuit <fro"the further fact loop gain of the circuit is greater than unity$

/f transistor ZU2F is con)ucting this +ill cause a #olu"e )rop across R +hich +ill ele#ate the

e"itter at U1 conse*uently$ /f Pin is s"all enough in #olu"e U1 +ill !e in cut off$ s Pin rises the

circuit +ill not respon) until U1 reaches itFs cut in point$ ith U1 con)ucting the circuit +ill

a"plifying < since the gain ^Po E^Pin is #e the output +ill rise in response to the rise of Pin$ s

Pin continues to rise RB )rop also increases$ Therefore #oltage of Pin +ill !e achie#e) at +hich U2 is

turne) 6:: $t this point Po @ Pr"s < output again is no longer respon)s to the input $ plot of Po

against P is )ra+n fro" rea)ings$ The #oltage at +hich U1 reaches cut in "ar,e) P @ P1 hysteresis$/n "any instance the hysteresis of the &ch"itt Trigger circuit is not a "atter of concern shoul) !e the

case if +e ha) a perio)ic signal of a"plitu)e large in co"parison +ith the hysteresis range P T an) our

interest is using the circuit as one +ay co"paring another application$ Thus e#en +hen use) as one

+ay co"parator if the signal +ere s"aller than #e #oltage then the co"parator ha#ing respon)e) !y

the transition in one )irection +oul) ne#er reset itself to hysteresis "ay !e eli"inate) !y a)Iusting

the loop gain of the circuit to !e unity$

CIRCIT O"ER.TION#To stu)y the circuit operation of &ch"itt trigger consi)er the follo+ing cases$

Cas+ 1# Ps @ 0

/n this U1 is 6:: < U2 is 6>$ This is the first sta!le state$ s no input signal is there !ecause of the

#oltage )i#ision across Pcc )ue to Rc1 an) Rc2 an) Rc +e get U1 in 6:: state < U2 is in 6> state$

Cas+ # _pper transition point _T7

pply the input signal < increase the "agnitu)e$ The "agnitu)e of input signal to "a,e first transition

!ecause of +hich U1 +ill !e in 6> state < U2 +ill !e in 6:: state is calle) as _T7$

Cas+ ! -o+er transition point -T7

-et us consi)er applie) input signal a"plitu)e +e are )ecreasing then after particular a"plitu)e #alue

there is again transition happens +hich cause U1 to !e in 6:: state < U2 to !e in 6> state$ The "agnitu)e of

input signal at +hich secon) transition ta,es is calle) as -T7$

"ROCE*RE#

1$ Connect the circuit on the !rea)!oar)$

2$ 9i#e the po+er supply an) apply sinusoi)al input #oltage$

3$ 6!ser#e the input an) output +a#efor" on CR6$

4$ lso o!ser#e hysteresis loop on CR6 an) fin) _T7 < -T75$ :inally plot the graph$





CONCLSION#

$

ST* DESTIONS#1$ ;plain the Hysteresis loop of &ch"itt trigger$2$ ;plain the +or,ing of &ch"itt trigger$3$ Define upper trigger potentialO4$ Define lo+er trigger potentialO5$ Define hysteresisO%$ hat are the other na"es of &ch"itt triggerO($ :or any type of iEp +hat is the oEp of a &ch"itt triggerO8$ ;plain the operation of a &ch"itt triggerO'$ hat is the theoretical #alue of _T7O10$ hat is the theoretical #alue of -T7O





E&No#$; 0LTIST.GE .0"LIFIER JITAOT FEE*/.CK

.I0

To Design an) stu)y fre*uency response of t+o stages RC couple) a"plifier an)

)eter"ine the effect of casca)ing on gain an) !an)+i)th$

O/BECTIE

a To stu)y an) )esign t+o stages RC couple) a"plifier +ithout fee)!ac,$

CO0"ONENTS REDIRE*#


1$ Transistor

2$ Capacitors

3$ Resistors

4$ Brea) !oar)


CIRCIT *I.GR.0#

TAEOR

This is "ost popular type of coupling as it pro#i)es ecellent au)io fi)elity$ couplingcapacitor is use) to connect output of first stage to input of secon) stage$ Resistances R1R2R; for" !iasing an) sta!iliation net+or,$ ;"itter !ypass capacitor offers lo+ reactance

paths to signal coupling Capacitor trans"its ac signal !loc,s DC$ Casca)e stages a"plifysignal an) o#erall gain is increase) total gain is less than pro)uct of gains of in)i#i)ual





stages$ Thus for "ore gain coupling is )one an) o#erall gain of t+o stages e*uals to@1Q2 +here 1@#oltage gain of first stage an) 2@#oltage gain of secon) stage$hen ac signal is applie) to the !ase of the transistor its a"plifie) output appears across thecollector resistor Rc$ /t is gi#en to the secon) stage for further a"plification an) signalappears +ith "ore strength$ :re*uency response cur#e is o!taine) !y plotting a graph

!et+een fre*uency an) gain in )! $The gain is constant in "i) fre*uency range an) gain

)ecreases on !oth si)es of the "i) fre*uency range$ The gain )ecreases in the lo+ fre*uencyrange )ue to coupling capacitor Cc an) at high fre*uencies )ue to Iunction capacitance C!e$

"ROCE*RE#

1$ pply input !y using function generator to the circuit$2$ 6!ser#e the output +a#efor" on CR6$3$ .easure the #oltage at a$ 6utput of first stage !$ 6utput of secon) stage$4$ :ro" the rea)ings calculate #oltage gain of first stage secon) stage an) o#erall gain of t+ostages$ Disconnect secon) stage an) then "easure output #oltage of first stage calculate#oltage gain$

5$ Co"pare it +ith #oltage gain o!taine) +hen secon) stage +as connecte)$%$ >ote )o+n #arious #alues of gain for )ifferent fre*uencies$($ graph is plotte) !et+een fre*uency an) #oltage gain$

0O*EL GR."A#

/>7_T P; :6R.

:/R&T &T9; 6_T7_T

&;C6>D &T9; 6_T7_T





:R;U_;>CK R;&76>&;

O/SER.TION T./LE# inpp :::::::::

RESLT .N* CONCLSION#

$


SrNo Fr+

(A

o

( GainM.2M

oin

Gain in / M.2M/

$log1$(oin

SrNo Fr+(A o

( GainM.2M

oin

Gain in / M.2M/

$log1$(oin

1 10 1( ( 2 20 18 ' 3 30 1' 10 4 50 20 20 5 (0 21 30 % '0 22 50 ( 100 23 (0 8 200 24 '0 ' 300 25 100

10 500 2% 200 11 (00 2( 300 12 '00 28 500 13 1 2' (00 14 2 30 '00 15 3 31 1.1% 5




ST* DESTIONS#

1$ hat is the necessity of casca)ingO2$ hat is 3)B !an)+i)thO3$ hy RC coupling is preferre) in au)io rangeO4$ hich type of coupling is preferre) an) +hyO5$ ;plain #arious types of CapacitorsO

%$ hat is loa)ing effectO($ hy it is ,no+n as RC couplingO8$ hat is the purpose of e"itter !ypass capacitorO'$ hich type of !iasing is use) in RC couple) a"plifierO





E&No#$% 0LTIST.GE .0"LIFIER JITA FEE*/.CK

.I0

To Design an) stu)y fre*uency response of t+o stages RC couple) a"plifier +ith#oltage series fee)!ac, an) )eter"ine the effect of casca)ing on gain an) !an)+i)th$

O/BECTIE

! To stu)y an) )esign t+o stage RC couple) a"plifier +ith #oltage series fee)!ac,$

CO0"ONENTS REDIRE*#


1$ Transistor

2$ Capacitors

3$ Resistors

4$ Brea) !oar)


CIRCIT *I.GR.0#





0O*EL GR."A#

/>7_T P; :6R.

:/R&T &T9; 6_T7_T

&;C6>D &T9; 6_T7_T

:R;U_;>CK R;&76>&;





TAEOR

/n #oltage a"plifier +ithout fee)!ac, the output #oltage Pout @ # Q Pin +here the a"plification #

also ,no+n as open loop gain "ay in general !e a function of !oth fre*uency an) #oltage$

6pen loop gain # is gi#en !y # @ PoutEPin `$1

&uppose +e ha#e the fee)!ac, loop so that a fraction Pout of the output is a))e) to the input$ b is,no+n as the fee)!ac, factor an) is )eter"ine) !y the fee)!ac, net+or, that is connecte) aroun) the

a"plifier$ The fee)!ac, net+or, "ay !e "o)ifie) using reacti#e ele"ents li,e capacitors or in)uctors

to gi#e fre*uency )epen)ent close) loop gain as in e*ualiation tone control circuits or construct

oscillators$ The input to the a"plifier is no+ PinF +here

PinF @ Pin Pout `2

The close) loop gain #f is gi#en !y

#f @ PoutE PinF `3

&u!stituting for PinF fro" 2 #f @ PoutE Pin Pout `4

Rearranging an) )i#i)ing !oth si)es !y Pin

1 Pout E Pin @ Pout E Pin Q #f `5

&ince # @ PoutE Pin

Then 1 # @ #E #f `% an) #f @ #E 1 # `(

/f #AA1 then #f 1E an) the effecti#e a"plification or close) loop gain #f is set !y the

characteristics of fee)!ac, constant thus "a,ing linearising an) sta!iliing the a"plification

characteristics straightfor+ar)$ /f there are con)itions +here # @ M1 the a"plifier has infinitea"plification an) a"plifier starts oscillating$ >o+ a"plifier +or,s as an oscillator an) the syste" is

unsta!le$

.2an'ag+s o7 n+ga'i2+ 7++5a=k#

1 /"pro#es sta!ility of gain 2/ncreases input i"pe)ance

3 Decreases output i"pe)ance 4 Re)uces )istortion < internally generate) noise$

5 /ncreases the !an)+i)th$

fre*uency response cur#e is graphical representation of the relationship !et+een the a"plifier

gain an) operating fre*uency$ The circuit po+er gain re"ains relati#ely constant across the "i)!an)

range of fre*uencies$

s operating fre*uency )ecreases fro" "i)!an) area of the cur#e a point is reache) +here the

po+er gain !egins to )rop off$ The fre*uency at +hich the po+er gain e*uals 50d of its "i)!an)

#alue is calle) Z-o+er cut off fre*uency fcl F$

s operating fre*uencies increases fro" "i)!an) area of the cur#e a point is reache) +here the

po+er gain !egins to )rop off again$ The fre*uency at +hich the po+er gain e*uals 50d of its

"i)!an) #alue is calle) Z_pper cut off fre*uency fcuF$

>ote the !an)+i)th of the circuit is foun) as the )ifference !et+een the cut off fre*uencies$

&o the !an)+i)th is





B@ fcu-fcl

NEE* OF C.SC.*ING#

@ \Mhfe R-1Ri

/t !eco"es #ery )ifficult to get #ery high gain using single stage a"plifier$ Thus it is necessary to go

for the casca)ing$

T"ES OF CO"LING#

hile coupling the output of first stage as input to the other )ifferent types of coupling are use)$

Direct coupling DC coupling tune) in)ucti#e coupling transfor"er coupling an) optical coupling are

fe+ i"portant types$ The a"plifier use) for practical purpose is RC coupling "etho)$

Due to casca)ing effecti#e !an)+i)th of the a"plifiers gets re)uce) !ecause gain has !een !ooste)$

To get proper !oosting in gain it is necessary to "atch the i"pe)ance i$e$ output i"pe)ance of first

stage +ith input i"pe)ance of the secon)$ :or practical circuit as sho+n in figure #oltage series

fee)!ac, is use) i"pro#e sta!ility$FREDENC RES"ONSE#

1 (?$A# The reactance of coupling capacitor Cc is *uite high an) hence #ery s"all range of

signal +ill pass fro" one stage to net stage$

2 .' high 7r+u+n=(P$KA# The reactance of Cc is #ery s"all an) it !eha#es as a short

circuit$ This increases the loa)ing effect of net stage an) causes to re)uce the #oltage gain$

.oreo#er at high fre*uency capaciti#e reactance of !aseMe"itter Iunction is lo+ +hich

increases the !ase current$ T+o reason the gain )rop off at high fre*uency$

"ROCE*RE#

1$ _se the co"ponents as per )esign an) !uil) the circuit on !rea)!oar)$2$ pply Pcc to the circuit$3$ Chec, the DC #oltage across collector an) e"itter$ Confir" that transistor is operate) in

acti#e region$4$ pply the input #oltage of a"plitu)e 50"P an) fre*uency 1H$5$ 6!ser#e output on CR6$%$ 6!ser#e output +ith an) +ithout fee)!ac,$($ Calculate gain as # @ Pout E Pin8$ To plot the fre*uency response #ary the fre*uency in the regular inter#als fro" 20 H to 20

H$ .easure the output #oltage an) calculate the #oltage gain$'$ Do the #oltage gain con#ersion in the for" of )eci!els as )B@ 20 logPoutEPin10$ Calculate Ban)+i)th fro" fre*uency response$





O/SER.TION T./LE# inpp :::::::::

RESLTS .N* CONCLSION#

$

ST* DESTIONS#

1$ hat is "eant !y :ee)!ac,O2$ hat are the types of fee)!ac, a"plifiersO ;plainO3$ Dra+ the circuit for #oltage series fee)!ac,O4$ hat are the )ifferences !et+een positi#e an) negati#e fee)!ac,O5$ hat is the effect of negati#e fee)!ac, on gain of an a"plifierO%$ hat is the for"ula for #oltage gain +ith negati#e fee)!ac,O($ hat are the other na"es for positi#e an) negati#e fee)!ac, circuitsO8$ hat is the for"ula for input resistance of a #oltage series fee)!ac,O'$ hat is the for"ula for output resistance of a #oltage series fee)!ac,O


Sr

No

Fr+

(A

o

(

Gain

M.2M

oin

Gain in / M.2M

/

$log1$(oin

Sr

No

Fr+

(A

o

(

Gain

M.2M

oin

Gain in / M.2M

/

$log1$(oin

1 10 1( (

2 20 18 ' 3 30 1' 10 4 50 20 20 5 (0 21 30 % '0 22 50 ( 100 23 (0 8 200 24 '0 ' 300 25 100 10 500 2% 200 11 (00 2( 300 12 '00 28 500

13 1 2' (00 14 2 30 '00 15 3 31 1.1% 5




E&No#$> CRRENT SERIES FEE*/.CK .0"LIFIER

.I0

To Design an) stu)y fre*uency response current series fee)!ac, a"plifier using BJT

an) )eter"ine the effect of fee)!ac, on gain an) !an)+i)th$

O/BECTIE

a To "easure the #oltage gain of current M series fee)!ac, a"plifier$

! To "easure the !an)+i)th +ith an) +ithout fee)!ac,$CO0"ONENTS REDIRE*#






1$ Transistor

2$ Capacitors

3$ Resistors


CIRCIT *I.GR.0#

0O*EL GR."A# />T7_T P;:6R.

6_T7_T P;:6R.

:R;U_;>CK R;&76>&;





TAEOR#

hen any increase in the output signal results into the input in such a +ay as to cause the

)ecrease in the output signal the a"plifier is sai) to ha#e negati#e fee)!ac,$ The a)#antages

of pro#i)ing negati#e fee)!ac, are that the transfer gain of the a"plifier +ith fee)!ac, can

!e sta!ilie) against #ariations in the hy!ri) para"eters of the transistor or the para"eters of the other acti#e )e#ices use) in the circuit$ The "ost a)#antage of the negati#e fee)!ac, is

that !y proper use of this there is significant i"pro#e"ent in the fre*uency response an) in

the linearity of the operation of the a"plifier$ This )isa)#antage of the negati#e fee)!ac, is

that the #oltage gain is )ecrease)$ /n CurrentM&eries :ee)!ac, the input i"pe)ance an) the

output i"pe)ance are increase)$ >oise an) )istortions are re)uce) consi)era!ly$

"ROCE*RE#

1 Connections are "a)e as per circuit )iagra"$

2 eep the input #oltage constant at 30"P pea,Mpea, an) #ary the fre*uency fro"

20H to 1.H an) note )o+n the output #oltage an) calculate the gain !y using the

epression # @ 20log P0 E Pi )B$

3 Re"o#e the e"itter !ypass capacitor C; an) repeat &T;7 2$n) o!ser#e the effect

of fee)!ac, on the gain of the a"plifier$

4 :or plotting the fre*uency response the input #oltage is ,ept constant at 30"P pea, to

pea, an) the fre*uency is #arie) fro" 100H to 1.H$

5 >ote )o+n the #alue of output #oltage for each fre*uency$ ll the rea)ings are

ta!ulate) an) the #oltage gain in )B is calculate) !y using epression # @ 20log

P0 E Pi )B$

% The Ban)+i)th of the a"plifier is calculate) fro" the graph using the epression

Ban)+i)th B$ @ f2 = f1$ here f1 is lo+er cut off fre*uency of C; a"plifier an) f2

is upper cut off fre*uency of C; a"plifier$

( The gainM!an)+i)th pro)uct of the a"plifier is calculate) !y using the epression

9ainMBan)+i)th 7ro)uct @ 3M)B "i)!an) gain ? Ban)+i)th$





O/SER.TION T./LE (8i'hou' 7++5a=k# inpp :::::::::

O/SER.TION T./LE (8i'h 7++5a=k# inpp :::::::::



Sr

No

Fr+

(A

o

(

Gain

M.2M

oin

Gain in / M.2M

/

$log1$(oin

Sr

No

Fr+

(A

o

(

Gain

M.2M

oin

Gain in / M.2M

/

$log1$(oin1 10 1( ( 2 20 18 ' 3 30 1' 10 4 50 20 20 5 (0 21 30 % '0 22 50 ( 100 23 (0 8 200 24 '0 ' 300 25 100 10 500 2% 200 11 (00 2( 300 12 '00 28 500 13 1 2' (00 14 2 30 '00 15 3 31 1.1% 5

Sr

No

Fr+

(A

o

(

Gain

M.2M

oin

Gain in / M.2M

/

$log1$(oin

Sr

No

Fr+

(A

o

(

Gain

M.2M

oin

Gain in / M.2M

/

$log1$(oin

1 10 1( ( 2 20 18 ' 3 30 1' 10 4 50 20 20 5 (0 21 30 % '0 22 50 ( 100 23 (0 8 200 24 '0

' 300 25 100 10 500 2% 200 11 (00 2( 300 12 '00 28 500 13 1 2' (00 14 2 30 '00 15 3 31 1.1% 5




ST* DESTIONS#

1 hat is the effect of CurrentM&eries :ee)!ac, a"plifier on the input i"pe)ance of thea"plifierO

2 hat is the effect of negati#e fee)!ac, on the Ban)+i)th of an a"plifierO

3 &tate the reason for the usage of negati#e fee)!ac, in an a"plifierO4 hat are the fun)a"ental assu"ptions that are "a)e in stu)ying fee)!ac, a"plifiersO5 hat are the a)#antages of pro#i)ing negati#e fee)!ac, a"plifierO% hat are the i)eal characteristics of a #oltage a"plifierO( Dra+ the circuit for the current series fee)!ac,O8 hat is the other na"e for current series fee)!ac, a"plifierO' hat is the for"ula for input resistance of a current series fee)!ac,O10 hat is the for"ula for output resistance of a current series fee)!ac,





E&No#1$ *IRECT CO"LE* .0"LIFIER

.I0To Design an) stu)y fre*uency response of )irect couple) a"plifier $

O/BECTIE

a To "easure the #oltage gain of )irect couple) a"plifier$

! To "easure the !an)+i)th of )irect couple) a"plifier$

CO0"ONENTS REDIRE*#


1$ Transistor

2$ Capacitors

3$ Resistors

4$ Brea) !oar)


CIRCIT *I.GR.0#

0O*EL GR."A





TAEOR#

s sho+n in the !elo+ )iagra" the )irect couple) a"plifier DC is consist of t+o transistors U1 an)

U2 a #oltage )i#i)er !ase !ias resistor net+or, R1 R2 +hich is pro#i)e) on the transistor U1 !ase

t+o collector resistors Rc1an) Rc2 the transistor U2 is self !iase) +e also use to+ e"itter !y

pass resistors R;1an) R;2$ The )irectMcouple) a"plifier is operate) +ithout the using of fre*uency

sensiti#e co"ponent li,e capacitor in)uctor an) Transfor"er etc$ The )irect couple) a"plifier

a"plifies the $C signal +ith fre*uency as lo+ a fraction of Hert H$ :irst of all +hen +e applie) a

#e half cycle at the /E7 of U1 transistor +hich is alrea)y !iase) through the )i#i)er !ias net+or,$

The #e half cycle for+ar)e) !ias the transistor U1 +hich start the con)uction an) gi#e an in#erte)

an) a"plifie) 6E7 at the collector$ s +e ,no+ that PC;@ Pcc = /cRc$ This a"plifie) M#e signe) is

pro#i)e) to the !ase of U2 transistor +hich is selfM!ias !ecause they are connecte) in casca)e

con)ition$ The !ase of U2 transistor is a re#erse) an) )i) not con)uct the 6E7 of transistor U2 is

a"plifie) signal in#erting to /E7 of U2 +hen the U2 )i) not con)uct an) the #oltage )rop across

collector e"itter +ill !e ero therefore the PCC is e*ual to /cRc$ The 6E7 e*ual to the #oltage

)rop across the collector resistors$

.ppli=a'ion o7 *ir+=' =oupl+ .9pli7i+r

1$ 7ulse a"plifier2$ Differential "plifier 3$ Regulator circuits of electronic po+er supply

4$ Co"puter circuitry5$ Jet engine control%$ ;lectronic instru"ents

"ROCE*RE#

1$ Construct the circuit as sho+n in the )iagra"$2$ &et the input #alue in the "ill #olts range$3$ Pary the fre*uency an) note the output Po in the CR6$4$ By ta,ing the fre*uency in ?Mais an) gain in KMais )ra+ the graph$5$ >ote the lo+er an) upper cutoff fre*uency !y )ra+ing the 3)! line$%$ :ro" these t+o fre*uencies calculate the !an) +i)th of the DC a"plifier$





O/SER.TION T./LE # inpp :::::::::



Sr

No

Fr+

(A

o

(

Gain

M.2M

oin

Gain in / M.2M

/

$log1$(oin

Sr

No

Fr+

(A

o

(

Gain

M.2M

oin

Gain in / M.2M

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1 10 1( ( 2 20 18 ' 3 30 1' 10 4 50 20 20 5 (0 21 30 % '0 22 50 ( 100 23 (0 8 200 24 '0 ' 300 25 100 10 500 2% 200 11 (00 2( 300 12 '00 28 500 13 1 2' (00 14 2 30 '00 15 3 31 1.1% 5




E&No#11 OLT.GE REGL.TOR SING L0;!

.I0

To Design an) construct a)Iusta!le #oltage regulator using /C -.(23$

O/BECTIEa To )esign lo+ #oltage regulator using -.(23$

! To )esign high #oltage regulator using -.(23$

CO0"ONENTS REDIRE*#


1$ /C

2$ Capacitors

3$ Resistors

4$ Brea) !oar)

DC &upply connecting +ires etc$

CIRCIT *I.GR.0#

a To +sign lo8 2ol'ag+ lo8 =urr+n' (LLC r+gula'or using L0;!

"osi'i2+ Lo8 2ol'ag+ r+gula'or =ir=ui' iagra9 an pin =onn+='ion using L0;!





! To +sign high 2ol'ag+ lo8 =urr+n' (ALC r+gula'or using L0;!

TAEOR#

#oltage regulator is a circuit that supplies a constant #oltage regar)less of changes in loa)current an) input #oltage #ariations$ _sing /C (23 +e can )esign !oth lo+ #oltage an) high#oltage regulators +ith a)Iusta!le #oltages$ :or a lo+ #oltage regulator the output P6 can !e#arie) in the range of #oltages Po Pref +here as for high #oltage regulator it is P6 A Pref$The #oltage Pref is generally a!out ($5P$lthough #oltage regulators can !e )esigne) using 6pMa"ps it is *uic,er an) easier to use /C

#oltage Regulators$ /C (23 is a general purpose regulator an) is a 14Mpin /C +ith internalshort circuit current li"iting ther"al shut)o+n currentE#oltage !oosting etc$ :urther"ore itis an a)Iusta!le #oltage regulator +hich can !e #arie) o#er !oth positi#e an) negati#e #oltageranges$ By si"ply #arying the connections "a)e eternally +e can operate the /C in there*uire) "o)e of operation$ Typical perfor"ance para"eters are line an) loa) regulations+hich )eter"ine the precise characteristics of a regulator$ The pin configuration is sho+n inin the )iagra"$"ROCE*RE#

a Lin+ R+gula'ion: For o ? an o 1!

1$ Construct the circuit as sho+n in the )iagra"$2$ 6!tain R1 an) R2 for Po @ 5P E 13 P3$ By #arying Pin fro" 3 to 12P "easure the output #oltage Po for -P-C regulator$4$ By #arying Pin fro" 10 to 20P "easure the output #oltage Po for -P-C regulator$4$ Dra+ the graph !et+een Pin an) Po as sho+n in "o)el graph a5$ Calculate the line regulation$

5 Loa R+gula'ion: For o ? an o 1!

1$ &et Pi such that Po@ 5 P E 13P2$ By #arying R- "easure /- an) Po$3$ 7lot the graph !et+een /- an) Po as sho+n in "o)el graph!

4$ Calculate the loa) regulation$





0O*EL GR."AS#

a Lin+ R+gula'ion 5 Loa R+gula'ion

O/SER.TION T./LE#

a Lo8 2ol'ag+ lo8 =urr+n' 2ol'ag+ r+gula'or

-ine regulation R- @

Pin Po /-

5 Aigh 2ol'ag+ lo8 =urr+n' 2ol'ag+

r+gula'or

-ine regulation R- @

Pin Po /-


-oa) regulation Po @

R- /- Po

-oa) regulation Po @

R- /- Po




E&No#1 OLT.GE REGL.TOR SING L0!1;

.I0

To Design an) construct a)Iusta!le #oltage regulator using /C -.31($

O/BECTIE

a To )esign lo+ #oltage regulator using -.31($

CO0"ONENTS REDIRE*#


1$ /C

2$ Capacitors

3$ Resistors

4$ Brea) !oar)

DC &upply connecting +ires etc$

CIRCIT *I.GR.0#

TAEOR#

-.31( a)Iusta!le positi#e #oltage regulator$ The connection )iagra" is sho+n a!o#e$ Theresistors R1 an) R2 )eter"ine the output #oltage Pout$ The resistor R2 is a)Iuste) to get theoutput #oltage range !et+een 1$2 #olts to 5( #olts$ The output #oltage that is re*uire) can !ecalculate) using the e*uation ou' r+7 (1QRR1 Q Ia3 R

/n this circuit the #alue of Pref is the reference #oltage !et+een the a)Iust"ent ter"inals an)the output ta,en as 1$25 Polt$ The #alue of /a)I +ill !e #ery s"all an) +ill also ha#e aconstant #alue$ Thus the a!o#e e*uation can !e re+ritten as ou' 1? (1QRR1





/n the a!o#e e*uation )ue to the s"all #alue of /a)I the )rop )ue to R2 is neglecte)$ Theloa) regulation is 0$1 percent +hile the line regulation is 0$01 percent per #olt$ This "eansthat the output #oltage #aries only 0$01 percent for each #olt of input #oltage$ The ripplereIection is 80 )! e*ui#alent to 10000$

The -. 33( series of a)Iusta!le #oltage regulators is a co"ple"ent to the -. 31( series)e#ices$ The negati#e a)Iusta!le #oltage regulators are a#aila!le in the sa"e #oltage an)current options as the -. 31( )e#ices$

"ROCE*RE#

a Lin+ R+gula'ion: For o 6

1$ Construct the circuit as sho+n in the )iagra"$2$ 6!tain R1 an) R2 for Po @ %P$3$ By #arying Pin fro" 5 to 15P "easure the output #oltage Po for -P-C regulator$4$ Dra+ the graph !et+een Pin an) Po as sho+n in "o)el graph a5$ Calculate the line regulation$

5 Loa R+gula'ion: For o 6

1$ &et Pi such that Po@ % P$2$ By #arying R- "easure /- an) Po$3$ 7lot the graph !et+een /- an) Po as sho+n in "o)el graph !4$ Calculate the loa) regulation$

0O*EL GR."AS#

a Lin+ R+gula'ion 5 Loa R+gula'ion

O/SER.TION T./LE#


analog circuits ii lab manual

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