towards an ieee 802.15.4 sdr transceiver - josep sabater · rapid prototyping of an all-digital...

Towards an IEEE 802.15.4 SDR Transceiver

Rapid prototyping of an all-digital implementation

Josep Sabater ( jsabaterm@el.ub.es)Departament d'ElectrònicaUniversitat de Barcelona

Towards an IEEE 802.15.4 SDR Transceiver 2

IndexTopics of the presentation

1) Introduction: IEEE 802.15.4 – SDR.

2) The system: An all-digital transceiver.

2a) The transmitter.2b) The receiver.

3) Results.

4) Conclusion and future work.

Towards an IEEE 802.15.4 SDR Transceiver 3

IntroductionOverview of the IEEE 802.15.4 standard (2003 - 2006)

• Specifies Physical (PHY) and Medium Access Control (MAC) layers for Low-Rate Wireless Personal Area Networks (LR-WPAN).

• Four PHYs that use three ISM bands: (3) 868/915 MHz and (1) 2.4 GHz.

• Four over-the-air data rates: 20 Kb/s (868 - 2003) 40 Kb/s (915 - 2006) 100 Kb/s (868 – 2006 1)

250 Kb/s (2.4 – 2003 / 868 – 20061 / 915 - 20061)

• Lower power and lower cost than other WPAN (e.g. Bluetooth).

Europe USA Worldwide

(1) Optional PHY

Towards an IEEE 802.15.4 SDR Transceiver 4

IntroductionOverview of PHY 868 MHz - 2003

Differential Encoder Bit To Chip BPSK

Modulator

En = B

n xor E

n - 1

PPDU

Two 15-chip PN seq.

'0' : 111101011001000'1' : 000010100110111

Preamble (0x00)

SFD (167

10)

FrameLength PHY Payloadr

PPDU (PHY Protocol Data Unit) Format

4B 1B 7b 1b variable

- 1 symbol (phase) / chip : (0 - π)- Raised cosine (roll-off = 1)

DSSS Protection against phase inversion

Pulse Shaping Chip to Symbol

20 Kb/s 300 KChip/s

600 KHz

868.3 MHz

DSSS: Direct Sequence Spread SpectrumPN: Pseudo NoiseBPSK: Binary Phase Shift Keying

Towards an IEEE 802.15.4 SDR Transceiver 5

Cognitive Radio and Software Radio

Introduction

• A Cognitive Radio (CR) terminal is:

● Aware of (sense) its environment.

● Capable of altering its PHY behaviour to adapt to the environment.

• Software Radio (SR) was first coined by Joseph Mitola (1995) to designate a single device:

● Whose behaviour is determined by software (upgradable).

● Can operate in different bands.

● Can use several modulations, coding schemes and bandwidths.

DSS +

QoS

DSS Dynamic Spectrum Sharing.QoS: Quality of Service.

reconfigurability +

programmability

Towards an IEEE 802.15.4 SDR Transceiver 6

IntroductionSoftware Radio vs Software Defined Radio

• The ideal SR architecture has been inspired by Joseph Mitola's view (1995):

• SR is a radio that employs wideband ADC / DAC and a processor to service an entire spectrum allocation in a single integrated module.

• Software Defined Radio (SDR) is a radio where some functions (including PHY) are defined in software.

SDR is a compromising and practical version of SR.

LNALNA ADCADC

DACDAC

Rx

TxPAPA

DSP

Towards an IEEE 802.15.4 SDR Transceiver 7

The designed systemAn overview

32 MHz

Transmitter

Test Unit

Receiver

FPGA

PA

CMP < 0

LNA

μP

Normal / Test

Normal / Test

1 bit

1 bit8 bits

8 bits

8 bits

1 bit

- An oversampled second order tunable 1-bit Bandpass Delta Sigma Modulator (BPDSM) transmitter with digital RF upconversion.

- A subsampling receiver.

PA: Power Amplifier.LNA: Low-Noise Amplifier.CMP: Comparator.

Towards an IEEE 802.15.4 SDR Transceiver 8

The designed systemThe transmitter and receiver submodules

IF Upconv. BP-ΔΣ

ModulatorRF

Upconv.Tx PHY Framer

Baseband Modulator

DPLLBaseband

Demod.Digital

DownconvRx PHYDeframer Correlator

32 MHz

1 bitRx In

I (fx s32.5)

Q (fx s32.5)32

MHz

Tx Out

1 bit1 bitfx s18.11 fx s9.6

Data Clk 1 bit

Data Stream8 bits

Rx Out

Byte Clk

8 bits

1 bit

1 bit

Chip Stream1 bit

Chip Clk1 bit

Correlation Sum (0 - 15)4 bits

Bit Clk1 bit

Tx In

Transmitter

Receiver

Fc = 4.3 MHz

BW = 600 Khz

Fc = 0 Hz

BW = 300 Khz

Fc = 4.3 MHz

BW = 600 KhzF

c = 868.3 MHz

BW = 600 Khz

α = 4.3

Sin = 4.3 MHz

8 bits

Towards an IEEE 802.15.4 SDR Transceiver 9

Design methodologyTransceiver design flow & test constraints

Behavioral Model

Behavioral Model

HDLSimulation

HDLSimulation

Recoding '.m' and sim files. VHDL files

Testbenches(VHDL)

SynthesizeSynthesize

VHDL files

FPGAFPGA

Synth. Mod. (VHDL)

+Flip-Flop & time

Mod.(VHDL)

bit file

User constraints

(UCF)

Matlab + Simulink

Modelsim

Xilinx ISE

Xilinx Impact + ML 501

• It has been tested in a Virtex 5 FPGA using Test submodule.

- Xilinx ML501 evaluation board.

• With an operating freq. of 32 MHz.

• For rapid validation of the systeman RF of 128 MHz is selected.

- Virtex 5 Digital Clock Manager (DCM).

Clk

32 MHz

Towards an IEEE 802.15.4 SDR Transceiver 10

ResultsLogic analyzer plots [1/2]: txStream vs rxStream

Towards an IEEE 802.15.4 SDR Transceiver 11

ResultsLogic analyzer plots [2/2]: BPSK wave

Towards an IEEE 802.15.4 SDR Transceiver 12

Conclusion and future workTowards an IEEE 802.15.4 SDR Transceiver

• An all-digital FPGA implementation of a transceiver inspired on the 868 band of the IEEE 802.15.4-2003 standard has been designed and tested.

• Independent modules for implementation in any FPGA device.

• Efficient multiplication algorithm is fundamental for a good performance. → Delay time: limits max. clock frequency of the whole system.

•A final RF-Upconversion stage in the range of 868 MHz. K. A Shehata, M A Abdoul-Dahab, S. H. El Ramly and K.A. Hamouda “An FPGA based 1-bit all digital transmitter

Employing Delta-Sigma modulation with RF output for SDR”, Signals, Circuits and Systems, 2008. SCS 2008. 2nd International Conference on, pp.1-6, 7-9 Nov. 2008.

• Improvement and additional filtering will be needed for higher freqs. • A better quality study and measurements (SNR, BER ...)

•

Towards an IEEE 802.15.4 SDR Transceiver 13

Questions?Thank you very much for your attention

Xilinx ML 501 board +

Agilent Logic Analyzer

Towards an IEEE 802.15.4 SDR Transceiver 14

Digital to digital modulation2nd order tunable Band-Pass Delta Sigma Modulator (BPDSM) [1/2]

• A Delta Sigma Modulator (DSM) is composed of a linear filter, a quantizer and a feedback loop.

• The quantification error (superimposed noise) can be shaped out from the desired frequency band modifying the transfer function of the filter.

H(f)

Low-Pass → LPDSM (integrator)

H(f) Band-Pass

→ BPDSM (resonator)

OSRBPDSM =f s / 2

BW signal

SQNRBPDSM ≈ 10 log10 3

21L OSRL1

OSR = 25

Tunable central freq (α) → α = 4.3

Towards an IEEE 802.15.4 SDR Transceiver 15

Digital to digital modulation2nd order tunable Band-Pass Delta Sigma Modulator (BPDSM) [2/2]

• The tunable resonator (2 in the design) is its basic function block.

• Configurable central frequency according to the α factor applied.

• As a result of real-time computation an efficient multiplier has been implemented

S z TBPDSM = z−1

− z−2

1−2 z−1z−2

x * y = (xe + x

o)(y

e + y

o) = x

e y

e+ x

ey

o + x

o y

e+ x

oy

o

P = x * y = Pee

+ Peo

+ Poe

+ Poo

Even comp

Odd comp

Two step process:

• Partial products• Final addition

Towards an IEEE 802.15.4 SDR Transceiver 16

Sampling + mixing operationSubsampling – Bandpass sampling – Undersampling

• It is the act of sampling a signal at a lower rate than Nyquist → 2 x fmax

• It achieves frequency translation via intentional aliasing

fs > 2 x BW

- fcarrier

= n f

s +

fif

→ f

carrier =

864 MHz +

4.3 MHz

= 868.3 MHz (for n = 27 and f

s = 32 MHz)

fcarrier

→ fif ϵ [0, f

s/2]

f (Hz)fif

2 fs

3 fs

n fs

fif

BW

Towards an IEEE 802.15.4 SDR Transceiver 17

Digital downconv. + Symbol detection

LUT-based mixing + arc tangent

CIC Filter(LPF + Decimation)

f0 = 4.3 MHz

arctan PDC

Phase Drift Compensator

I

Q

(fx s32.5)

(fx s32.5)

symbol

LUT

0o

90o

sin (w0t) / -sin(w

0t)

cos(w0t) / -cos(w

0t)

1 bit

sin(w0t)

-sin(w0t)

cos(w0t)

-cos(w0t)

CIC Filter(LPF + Decimation)

I

Q

0

1

234

5

6

7

Baseband Demod.Digital Downconv.

CIC: Cascaded Integrator-CombLPF: Low-Pass FilterLUT: Look-Up Table

Towards an IEEE 802.15.4 SDR Transceiver 18

IF UpconversionLUT based carrier generation at 4.3 MHz

• Mixing operation (fixed point arithmetic multiplication) of a 4.3 MHz carrier with the baseband signal.

• A.A. Khatibzadeh, K. Raahemifar and M. Ahmadi, "A 1.8 V 1.1 Ghz novel digital multiplier," Electrical and Computer Engineering, 2005. Canadian Conference on, pp.686-689, 1-4 May 2005.

x * y = (xe + x

o)(y

e + y

o) = x

e y

e+ x

ey

o + x

o y

e+ x

oy

o

P = x * y = Pee

+ Peo

+ Poe

+ Poo

Towards an IEEE 802.15.4 SDR Transceiver 19

Baseband modulatorDifferential Encoding, DSSS, Pulse Shaping and T

chip generation

320 entries

LUT

+ 3

signal Tchip

signal Tchip

- 300

1

Sinc amp

Q rcos

- f clock

= 32 Mhz- T

Chip = 106 * T

clock = 3.3125 us → 3.333 us

D Q

Clk

D

Clk

Q

Chip Stream

nQ rcos

I rcos nI rcos

qClk

iClk

Pulse shaped signal

+

Towards an IEEE 802.15.4 SDR Transceiver 20

Digital Downconversion

• Mixes input with a local 4.3 MHz sin generated in the same way characteristics that the one present in the IF upconversion stage of the transmitter.

• Low-pass filtering and decimation (sample-rate reduction) via a Cascaded Integrator-Comb (CIC) filter.

- It only uses addition and substraction arithmetics (multiplication) → embedded.

- Its frequency response envelope is like sin (x) / x → FIR compensation.

Moving information to baseband - Filtering

I I ↓R CC

fs f

s / R

Integrator Comba) N = 5 (stages), M = 2 (delay) and R = 16

b) fcut-off

= 300 Khz - Nulls placed at multiples of (fs/R) / M = 1 MHz

Towards an IEEE 802.15.4 SDR Transceiver 21

DPLL (Digital Phase Lock Loop)

Generating the chip sampling clock (Ts_chip

)

• When DPLL is synchronized with data stream, the received signal is sampled in the centre point of chip cell (T

s_chip).

• Using a sampling rates (fs) of 8 MHz, we obtain that:

Ts_chip

≈ 27 x Ts

T chip

Ts_chip

8 5 81 5

-2 -1 0 +1 +2

Ts_chip + 1

= Ts_chip

Ts_chip + 1

= Ts_chip

- 2

Sampling is delayed Sampling is advanced