fsm optimization

Sequential Logic Optimization

Vineet Sahula

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 2

Finite State Machine- Model

●p=2l

●Input variables, xi

●Input vector Ij={x

1,x

2, ...x

l}

●Input alphabet I={I1,I

2, ...I

p}

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 3

Finite State Machine- Model

●q=2m

●Output variables, zi

●Input vector Oj={z

1,z

2, ...z

m}

●Input alphabet O={O1,O

2, ...O

q}

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 4

Finite State Machine- Model

●n=2k

●State variables, yi

●Input vector Sj={y

1,y

2, ...y

k}

●Input alphabet S={S1,S

2, ...S

n}

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 5

Machine Specification- Set theoritic

● M=(I,O,S,)

● : I×S → S

● : I×S → O Mealy machine

● : S → O Moore machine

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 6

State Machine model-Tabular

xX1 X2

S

S1 S2 S1

S2 S3 S2

S3 S2 S1

xX1 X2

S

S1 Y1 Y2

S2 Y3 Y1

S3 Y2 Y3

XX1 X2

S

S1

S2 S1

Y1 Y2

S2

S3 S2

Y3 Y1

S3

S2 S1

Y2 Y3

state outputs

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 7

Mealy Machine Model-Graph

XX1 X2

S

S1

S2 S1

Y1 Y2

S2

S3 S2

Y3 Y1

S3

S2 S1

Y2 Y3

S1

S2

X1/Y1

X2/Y2

S3

X1/Y2

X2/Y3

X1/Y3

X2/Y1

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 8

Moore Machine Model-Graph

xX1 X2 Y

S

S1 S2 S1 Y2

S2 S3 S2 Y1

S3 S2 S1 Y3

S1/Y2

X1

X2

X1X2

X1

S2/Y1

S3/Y3

X2

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 9

Capabilities & Limitations of FSMs

● What FSM can do?– Transit through sequence of states– For input of a length of more than n vectors (each

vector is l-tuple, and is one of p vectors)● Machine will arrive in one of n states for more than n

inputs

● Limitations– The FSM can transit to one of n-states– The maximal length of non-repeating sequence is

≤ n

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 10

k-distinguishablility

● Two states Si, S

j are distinguishable

● If there exists at least one finite input sequence, which when applied to FSM M, causes different output sequence, depending on whether S

i or S

j is INITIAL

state● The sequence which distinguishes these states is called

a distinguishing sequence of pair (Si,S

j)

● (Si,S

j) is called k-distinguishable, if a

distinguishable seq. Of length k exists

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 11

k-equivalence● Two states S

i, S

j are k-equivalent

● If they are NOT k-distinguishable

● If they are k-equivalent– They are also r-equivalent, r < k

● They are equivalent– If they are k-equivalent for all k

● If states Si, S

j are equivalent

– All their corresponding X-successors are also equivalent

● The STATE-EQUIVALENCE is an equivalence relation

● The sates which are equivalent, are said to form equivalence-class

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 12

State MinimizationGoal : identify and remove redundant states

(states which can not be observed from the

FSM I/O behavior)

Why : 1. Reduce number of latches– assign minimum-length encoding– only as the logarithm of the number

of states

2. Increase the number of unassigned states

codes– heuristic to improve state-assignment

and logic-optimization

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 13

Algorithmic State Minimization

● Goal – identify and combine states that have equivalent behavior

● Equivalent States: – Same output– For all input combinations, states transition to same

or equivalent states● Algorithm Sketch

1. Place all states in one set2. Initially partition set based on output behavior3. Successively partition resulting subsets based on

next state transitions4. Repeat (3) until no further partitioning is required

● states left in the same set are equivalent

Polynomial time procedure

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 14

State Minimization Definition

● Completely-specified state machine– two states are equivalent if outputs are

identical for all input combinations

Next states are equivalent for all input

combinations– equivalence of states is an equivalence relation

which partitions the states into disjoint equivalence classes

● Incompletely specified state machines

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 15

Classical State Minimization

1. Partition states based on input output values

asserted in the state

2. Define the partitions so that all states in a partition transition into the same next-state partition (under corresponding inputs)

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 16

Classical State Minimization Algorithm

1. Partition the set of internal states based on input output values asserted in the state

2. Define the partitions so that all states in a partition transition into the same next-state partition (under corresponding inputs)

Only for Completely specified Machines

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 17

PS NSx=0 x=1

A E,0 D,1

B F,0 D,0

C E,0 B,1

D F,0 B,0

E C,0 F,1

F B,0 C,0

Machine M1

● (ABCDEF)● (ACE)(BDF)● (ACE)(BD)(F)● (AC)(E)(BD)(F)● (AC)(E)(BD)(F)

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 18

Example (FSM in PS-NS state format)

Ex :

0 A B 0

1 A C 0

0 B D 0 (A,B,C,D,E,F,H) (G)

1 B E 0

0 C F 0 (A,B,C,E,F,H)(G)(D)

1 C A 0

0 D H 0 (A,C,E)(G)(D)(B,F)(H)

1 D G 0

0 E B 0

1 E C 0

0 F D 0

1 F E 0

0 G F 1

1 G A 0

0 H H 0

1 H A 0

States A, C and E can be combined to one stateStates B and F can be combined States B and F can be combined to one stateto one state

G has other input-output response than other states

D has other input-output response than other states because it goes to G which is known to be non-equivalent state-goes to red and blue groups

B and F go to D

Please check this using triangular table

You can also marke each new group with a new symbol and check transitions to thus marked groups

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 19

Example of partition based minimization

Ex :

0 A B 0

1 A C 0

0 B D 0 (A,B,C,D,E,F,H)(G)

1 B E 0

0 C F 0 (A,B,C,E,F,H)(G)(D)

1 C A 0

0 D H 0 (A,C,E,H)(G)(D)(B,F)

1 D G 0

0 E B 0 (A,C,E)(G)(D)(B,F)(H)

1 E C 0

0 F D 0

1 F E 0

0 G F 1

1 G A 0

0 H H 0

1 H A 0

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 20

Input Next State OutputSequence Present StateX=0 X=1 X=0 X=1

Reset S0 S1 S2 0 00 S1 S3 S4 0 01 S2 S5 S6 0 000 S3 S0 S0 0 001 S4 S0 S0 1 010 S5 S0 S0 0 011 S6 S0 S0 1 0

State Minimization Example● Sequence Detector for 010 or 110

S0

S3

S2S1

S5 S6S4

1/00/0

1/0

1/00/1

0/01/00/0

1/00/0

1/00/1

1/00/0

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 21

( S0 S1 S2 S3 S4 S5 S6 )

( S0 S1 S2 S3 S5 ) ( S4 S6 )

( S0 S3 S5 ) ( S1 S2 ) ( S4 S6 )

( S0 ) ( S3 S5 ) ( S1 S2 ) ( S4 S6 )

Input Next State OutputSequence Present StateX=0 X=1 X=0 X=1

Reset S0 S1 S2 0 00 S1 S3 S4 0 01 S2 S5 S6 0 000 S3 S0 S0 0 001 S4 S0 S0 1 010 S5 S0 S0 0 011 S6 S0 S0 1 0

S1 is equivalent to S2

S3 is equivalent to S5

S4 is equivalent to S6

Method of Successive Partitions

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 22

Input Present Next State OutputSequence State X=0 X=1 X=0 X=1

Reset S0 S1' S1' 0 00 + 1 S1' S3' S4' 0 0X0 S3' S0 S0 0 0X1 S4' S0 S0 1 0

Minimized FSM

● State minimized sequence detector for 010 or 110

S0

S1’

S3’ S4’

X/0

1/0

1/00/1

0/0

X/0

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 23

U5

SR_FF

Q

~Q

S

R

Asynchronous sr flip-flop

U2

NOR2

U3

NOR2

r

s

Q

notQ

U3

NAND2

U2

NAND2

U1

NAND2

U4

NAND2

s

r

Q

notQ

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 24

asynchronous flip-flop sr

s r Q(t+1)

0 0 Q(t)

0 1 0

1 0 1

1 1 -

Q(t)Q(t+1) s r

0 0 0 -

0 1 1 0

1 0 0 1

1 1 - 0

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 25

Negated sr FF

U2

NAND2

U3

NAND2

not_s

not_r

Q

notQ

U5

SR_FF

Q

~Q

~S

~R

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 26

Negated sr FF

This version has negated inputs

This FF realizes the function:

Q(t+1)

0 0 -

0 1 1

1 0 0

1 1 Q(t)

Q(t)Q(t+1)

0 0 - 0

0 1 0 1

1 0 1 0

1 1 0 -

s r s r

s r

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 27

Classical State Minimization Algorithm

1. State transitions are NOT defined Pressure that machine starts only in

KNOWN state, OR Presume un-specified STATE to be labeled,

may be T

2. Outputs are NOT defined

InCompletely specified Machines

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 28

Covering State

● States Si, of M

1 is said to cover or contain S

j of

machine M2 iff every input sequence

applicable to Sj is also applicable to S

i

● And its application to M1 and M

2 when they are

initially in Si, S

j respectively, results in identical

output sequences whenever the outputs of M2

are specified

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 29

Covering Machine

● Machine M1 is said to cover M

2 iff for every

state Sj in M

2 , there is corresponding S

i in M

1

Si covers S

j

● If state Si, of M covers another state S

j of the

same machine, then only Si must be retained,

while Sj maybe deleted

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 30

Compatible states● Two states S

i, S

j of machine M are compatible iff,

for every input sequence applicable to both Si,

Sj , the same output sequence will be produced

whenever both outputs are specified and regardless of whether S

i, or S

j , is initial state

● Hence, Si, S

j are compatible iff their outputs are

NOT conflicting and their Ii-successors for every

Ii for which both are specified, are either same

OR also compatible

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 31

Compatibility

● Three or more states are compatible, iff they are pair-wise compatible

● A set of compatible states (Si, S

j,S

k.....) is

called compatible● A compatible C

i is said to cover (or larger than)

another compatible Cj if every state in C

j is

also contained in Ci

● A compatible is maximal if it is not covered by any other compatible

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 32

Closed set of Compatibles

● A set of compatibles is said to be closed if for every compatible contained in the set, all its implied compatibles are also contained

● A closed set of compatibles which contain all the states of M is called closed covering

● Teh set of all possible maximal compatibles is a closed covering– It is also an upper bound on # of states in reduced

machine

V. Sahula, 2012-13 Computer Arith. & Microarchitecture: FSM-1 33

Minimization Procedure● Form merger TABLE or merger GRAPH

● Form a GROUP of all possible pairwise compatible states

● Opton-1● Find all possible CLIQUES in graph● Find minimal set of cliques (clique cover) so that all vertices

are covered. Here, each vertex represents a pair of compatible state

● Option-2● From table, proceed from right to left, column-wise and

keep finding maximal compatibles

● From set of maximal compatibles find minimal closed cover

● Using compatibility graph