final year project presentation a remote fpga laboratory environment david hehir 4 th year ee...

Final Year Project Presentation

A Remote FPGA Laboratory

EnvironmentDavid Hehir 4th Year EE 03460673

Supervisor: Fearghal Morgan

Topics Of Discussion

• Introduction To Project• Development Environment• Logon Functionality/Filespace

Allocation/Security Timeout• Webpage• Further Functionality• Graphical User Interfaces• Software/Coding Involved• Questions?

IntroductionThe basic aims of this project are to develop a remote

Spartan-3 FPGA lab environment that will:• Allow a user to logon to a dedicated host PC

running the FPGA development system• Upload/download a configuration bitstream to the

remote FPGA development system• Manipulate the board using GUIs and visual

interfaces• Compile/run configurations on the FPGA which will

be viewable on a webcam connected to the host PC

Development Environment

• Host PC/Workstation and Webcam

• A Spartan-3 FPGA Development System

• Xilinx ISE / Modelsim

• Visual Basic Host GUI

• Web Development Package

• Remote Server

Logon/Account Functionality

• Each user will be allocated their own account on the system allowing logon via user/password function.

• Adequate filespace will be provided so the user can create/delete files and folders as needed.

• Only one user will be able to connect at a time.• A security/timeout mechanism will be running on

the server telling the user how much time he/she has left on the FPGA

• Password retrieval function via e-mail to be also included

Local PC

Webcam

Spartan-3 FPGA

Workstation/Server

Schematic of Basic Setup

A PC will connect via a webpage to the secure workstation/server PC

Webcam connected and constantly refreshing image of FPGA

Server dedicated to running the FPGA Lab Environment connected to Webcam,and to Spartan-3 via serial

Webpage

Webpage will consist of:• Login screen which enables users to enter a predefined

username and password• iMPACT: Allows users to perform device configuration as

a batch operation or through a GUI• An upload/browse screen which enables users to

manipulates folders and bitstream files on their userspace

• A live webcam view of the FPGA with interactive radio buttons connected to the 4 toggle buttons and 8 switches on the FPGA

Example Webpage Layout

Other Possible Functions

• Data processing• Digital Signal

Processing (DSP)• Image processing

such as edge detection

• Possible USB connectivity for faster data transfer

Graphical User Interface (AppliedVHDL)

Software/Coding Involved

• HTML/Dreamweaver/Web Development Package/Dynamic HTML scripting

• Visual Basic/C/C++

• Possibility of some JAVA being implemented for GUIs

Visual Basic GUI

• A Visual Basic GUI will be included to incorporate a remote/local hardware selection option and radio buttons to enable 8 x virtual toggle switches and 4 x virtual spring-loaded switches.

• Transfer of the switch settings to FPGA will be VIA the serialIO element to the system under test.

Visual Basic GUI

Radio buttons

Reset Button

Further Functionality

Further functionality to be developed may include:

• Extending the system for use with the NEXYS Spartan-3 development system, its GUI and USB interface.

• Develop a new memory controller within the appliedVHDL system to allow operation on the NEXYS system.

NEXYS BoardThe Nexys board provideslarge external memory arrays, a collection ofuseful I/O devices, and• USB/USB2 port for FPGA configuration andhigh-speed data transfers• 16MB of fast Micron PSDRAM and 4MBof Intel StrataFlash Flash ROM• Xilinx Platform Flash ROM that storesFPGA configurations indefinitely•• 50MHz oscillator• Connector for 1/8 VGA hi-res graphicsLCD panel or 16x2 character LCD display•• 8 LEDs, 4-digit seven-segment display, 4 pushbuttons, 8 slide switches