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Digital IC Design Flow

EE Summer Camp 2009Ashish Bhatia

Why design ICs?

Electronic systems are used everywhere in industry todayMechanical components are being replaced with electronic chips

Design flow of Digital and analog IC are different

we will focus on digital IC design in this lecture

How digital ICs are designed?

Design Specification

What the IC is suppose to do?Power constraints

Embedded devices are more power constraints Budget Constraints

IC for satellites have far more budget than IC for consumer electronics

Timing ConstraintsGPU IC's extremely fastembedded microcontrollers have much relaxed timing constraints

Fault redundancyspace bound electronics have much larger redundancy than common logic gates

Design Specification

TestabilityDescribe Digital Design in terms of

State Spaces (no notion of time)Transition Diagrams (notion of time)

Eg. Designing a ProcessorArchitecture Type? Harvard/NeumannInstruction set? RISC/CISCPower consumption?On chip cache size? Cost?Time to develop

Design Partitioning

Partition whole design into function unitsease of sythesisease of testing

For example, Processor divided intoInstruction Fetch and DecodeALUMemory Interface unit

ALU further divided into adder and multiplier

Design Entry

Design of Function unit in HDLVerilog, VHDL and SystemC are popularwe will stick to Veriloghigh level abstractionportableease of designused for gate level synthesis of circuit

Eg. output = input1 + input2 (adder)

Design Verification

SimulationFormal Verification

done first for individual functional unitsand then for combined system

Presynthesis Sign-off

All disperancies between Design specifications and HDL design are resolved before going any further

Gate Level Synthesis (Technology Mapping)

Boolean logic (optimal) for complete system is generated Map this to standard cell of FPGA (netlist generation)

Post synthesis Design Verification

Design specifications might differ from post synthesis results

unsynthesizable constructs ignored during synthesisDesign specifications - higher level abstractionssynthesized implementation - based on FPGA standard cell

Post synthesis Timing Validation

Simulations ignored parasitics of metal interconnectsSynthesized ciruit has interconnectsTime margin might fail (specially along critical path)

Gate Level Schematics

After successful testing on FPGAcomplete system described in terms of schematic of transistors (MOSFET, BJT)

Layout Design

design layout of each unitcombine units (placement and routing)Design rule checks (min. metal width, min. oxide thickness etc.)

Timing Analysis

to consider parasitics (generated after layout)

Design Sign-off

mask is ready for tape outFurther testing done on fabricated chips made to find if they are faulty or not

This is to account for process induced errorsnot logic based errors (they are supposed to be taken care of earlier)

Fabrication

Mask GenerationWafer ProcessingPackagingTestingProduction of chips

Referencewww.ee.ucl.ac.uk/~yyang/ELEC3027_Outline.pdf