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Digital IC Design Flow EE Summer Camp 2009 Ashish Bhatia

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Page 1: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Digital IC Design Flow

EE Summer Camp 2009Ashish Bhatia

Page 2: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Why design ICs?

Electronic systems are used everywhere in industry todayMechanical components are being replaced with electronic chips

Page 3: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Design flow of Digital and analog IC are different

Page 4: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

we will focus on digital IC design in this lecture

Page 5: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

How digital ICs are designed?

Page 6: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 7: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 8: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Design Specification

What the IC is suppose to do?Power constraints

Embedded devices are more power constraints Budget Constraints

IC for satellites have far more budget than IC for consumer electronics

Timing ConstraintsGPU IC's extremely fastembedded microcontrollers have much relaxed timing constraints

Fault redundancyspace bound electronics have much larger redundancy than common logic gates

Page 9: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Design Specification

TestabilityDescribe Digital Design in terms of

State Spaces (no notion of time)Transition Diagrams (notion of time)

Eg. Designing a ProcessorArchitecture Type? Harvard/NeumannInstruction set? RISC/CISCPower consumption?On chip cache size? Cost?Time to develop

Page 10: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 11: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Design Partitioning

Partition whole design into function unitsease of sythesisease of testing

For example, Processor divided intoInstruction Fetch and DecodeALUMemory Interface unit

ALU further divided into adder and multiplier

Page 12: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 13: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Design Entry

Design of Function unit in HDLVerilog, VHDL and SystemC are popularwe will stick to Veriloghigh level abstractionportableease of designused for gate level synthesis of circuit

Eg. output = input1 + input2 (adder)

Page 14: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 15: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Design Verification

SimulationFormal Verification

done first for individual functional unitsand then for combined system

Page 16: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 17: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Presynthesis Sign-off

All disperancies between Design specifications and HDL design are resolved before going any further

Page 18: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 19: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Gate Level Synthesis (Technology Mapping)

Boolean logic (optimal) for complete system is generated Map this to standard cell of FPGA (netlist generation)

Page 20: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 21: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Post synthesis Design Verification

Design specifications might differ from post synthesis results

unsynthesizable constructs ignored during synthesisDesign specifications - higher level abstractionssynthesized implementation - based on FPGA standard cell

Page 22: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 23: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Post synthesis Timing Validation

Simulations ignored parasitics of metal interconnectsSynthesized ciruit has interconnectsTime margin might fail (specially along critical path)

Page 24: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 25: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Gate Level Schematics

After successful testing on FPGAcomplete system described in terms of schematic of transistors (MOSFET, BJT)

Page 26: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 27: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Layout Design

design layout of each unitcombine units (placement and routing)Design rule checks (min. metal width, min. oxide thickness etc.)

Page 28: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 29: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Timing Analysis

to consider parasitics (generated after layout)

Page 30: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 31: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Design Sign-off

mask is ready for tape outFurther testing done on fabricated chips made to find if they are faulty or not

This is to account for process induced errorsnot logic based errors (they are supposed to be taken care of earlier)

Page 32: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable
Page 33: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Fabrication

Mask GenerationWafer ProcessingPackagingTestingProduction of chips

Page 34: Digital IC Design Flow - ashishb.net · Design Entry Design of Function unit in HDL Verilog, VHDL and SystemC are popular we will stick to Verilog high level abstraction portable

Referencewww.ee.ucl.ac.uk/~yyang/ELEC3027_Outline.pdf


CPE 626 The SystemC Language – VHDL, Verilog Designer’s Guide

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Praktikum: SystemC - (Hardware-Software-Co-Design) › … · 2013-07-05 · Praktikum: SystemC SystemC-TLM Fractal Labs Joachim Falk ([email protected]) Friedrich-Alexander-Universität

Praktikum: SystemC - (Hardware-Software-Co-Design) · Praktikum: SystemC SystemC-TLM Tutorial Joachim Falk ([email protected]) Friedrich-Alexander-Universität Erlangen-Nürnberg Joachim

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Basic Logic Design with Verilog HDL - 國立臺灣大學media.ee.ntu.edu.tw/...media=verilog:121102...verilog_student_zbt.pdfBasic Logic Design with Verilog HDL ... Write Verilog code

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A GENERATION AHEAD - gongterr.co.kr Seminar_Overview_William.… · –Timed (architectural): VHDL, Verilog, SystemC Ideal for

Verilog 2 - Design Examples

Verilog 2 - Design Examplescsg.csail.mit.edu/.../lectures/L03-Verilog-Design-Examples.pdf · 6.375 Spring 2006 • L03 Verilog 2 - Design Examples • 2 Course administrative notes

SystemC: Introduction. SystemC A C++ based class library and design environment for system-level design. Suitable for functional description that

Thesis Functional verification with SystemC Verification with SystemC Funktionell verifiering med SystemC Author: George Kalo Employer: ... usually in VHDL or Verilog. As the complexity

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ESL, SystemC and TLM 2.0: Why You Should Care · ... SystemC and TLM 2.0: Why You Should Care ... – Integrates easily into a Verilog/SystemVerilog ... – Independent refinement

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GSC - A SystemC to Verilog translator - SourceForgegscc.sourceforge.net/gsc.pdf · 2007-04-11 · Each SystemC method has a sensitivity list associated, and is triggered every time

Verilog digital system design

SystemC - CAE Usershomepages.cae.wisc.edu/~ece734/SystemC/SystemC-Tutorial.pdf · SystemC Introduction Why not leverage experience of C/C++ developers for H/W & System Level Design?