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© Copyright 2012 Xilinx .

A GENERATION AHEAD SEMINAR SERIES A GENERATION AHEAD

Vivado Design Suite Overview


Portfolio: All Programmable FPGAs, SoCs and 3D ICs today

Product: Extra node of performance, power and integration

Productivity: Unmatched time to integration and implementation

A Generation Ahead at 28nm

28nm Xilinx at 28nm


System Integration bottlenecks

– Design and IP reuse

– Integrating algorithmic and RTL level IP

– Mixing DSP, embedded, connectivity, logic

– Verification of blocks and “systems”

Implementation bottlenecks

– Managing hierarchy & reuse in implementation

– Getting estimates early & closing on timing, utilization, power

– Debugging across tools, abstractions, changes

– Run time and scalability impact on turn times

– Late ECOs and rippling effect of changes

Next Generation Productivity Challenges

3D


The First SoC Strength Design Suite

IP & System Centric Next Generation Design Environment

Accelerating Integration & Implementation up to 4X

From Months to Weeks


Vivado Design Suite Technology Advantages

Accelerating

System Integration

Accelerating

Implementation

Integrated Design Environment

De

bu

g a

nd

An

aly

sis

Scalable to 100M Gates

Fast, Hierarchical and

Deterministic Closure

Automation w/ ECO

IP & System-centric

Integration with Fast

Verification

Sh

are

d S

cala

ble

Da

ta M

od

el


Reduced design iterations

– Advanced analysis and reporting at every design step

– Shared design info throughout the flow to converge faster

– Interactive cross-probing accelerates debug

– Advanced P&R, 4x faster than competing solutions

– Superior QoR, 1 speed grade over ISE

Efficient memory utilization

– ½ the memory requirements

Vivado Integrated Design Environment

Reports

entity FIR is port (clk : in rst : in din : in

Timing Report

Timing Path #1 Timing Path #2 Timing Path #3

RTL Schematics Placement

Code

Changes

Tool

Settings Placement

Edits

IP Assembly

IP Integrator


Vivado Accelerates System Integration


IP-Centric and System Integration & Verification

Tcl SDC

w/ HW Co-sim ISim Vivado

Ru

ntim

e


Vivado ESL Offerings Fastest path from Algorithm to Implementation

Vivado HLS - untimed algorithm to timed RTL

– Untimed (functional): C, C++, SystemC

– Timed (architectural): VHDL, Verilog, SystemC

Ideal for…

– Accelerating verification and implementation • 10,000x faster simulation than RTL

• Explore multiple RTL architecture from the same C/C++

– Embedded designers interested in HW acceleration

– Best for applications with parallel processing

System Generator

– Implement DSP algorithms in a fraction of time of RTL

– Automatic RTL generation from Simulink® and MATLAB®

Comprehensive integration

– Supports AXI-4 and automatically packages the RTL for Vivado’s IP catalog

“…we used C to implement a key algorithm…the results showed that Vivado HLS is

very useful in an FPGA design flow.” Hengqi Liu, CTO, ZTE Inc.

“…we used C to implement a key algorithm…the results showed

that Vivado HLS is very useful in an FPGA design flow.”

Hengqi Liu, CTO, ZTE Inc.


Rapid correct by construction IP integration

– Interface level connections speeds assembly

– IP parameter changes are propagated to ensure correct behavior

– Full and arbitrary hierarchy supports reuse and readability

– Automated generation of RTL for processor-based or non-processor based designs

Rapid verification and easy reuse

– Integrated with Vivado Logic Analyzer and Vivado Simulator for debug and analysis

– Integrated with Vivado IP Packager to build, share and reuse your own IP subsystem

Beta now, production release early 2013

Vivado IP Integrator – Accelerated Integration


Share IP within your team, project or company

3rd party IP delivered with a common look and feel

Only tool that enables reuse IP at any point in

the implementation process

– Source, placed, or placed and routed

Package IP & IP Subsystems for Reuse

IP Packager

Source (C, RTL, IP, etc)

Simulation Models

Documentation

Example Designs

Test Bench

Vivado IP Integrator Standardized IP-XACT

representation

Xilinx IP

3rd Party IP

User IP

Reuse in different designs

Reuse multiple times


Vivado Simulation & Synthesis

Saves Time and Money

Tightly integrated into Vivado IDE

– Easy cross probing between sources and

waveforms and reports

Accelerated verification

– 3X faster than Xilinx ISE Simulator

– 2X less memory

– Accelerate verification even more with HW

co-simulation

Synthesis:

– Superior SystemVerilog support

– 3x faster runtime

– 15x with “quick-synthesis” option

– Easley mark nets for hardware debug with

Vivado Analyzer


Vivado Accelerates Implementation


Industry’s Most Deterministic Design Closure

Time

Full compile

Full compile

Full compile

Full compile

Incremental

Incremental

TOP

MEM DMA

CPU CNTRL DATA

Optimizer

Analyzer


Up to 4x faster than alternative solutions

Vivado supports large designs where competition fails

Less variability with design size more predictable run-times

Vivado Provides Consistent Runtime Advantage with

Greater Predictability and Higher Scalability

0

5

10

15

20

25

0K 500K 1,000K 1,500K 2,000K

Ru

nti

me

(h

ou

rs)

Design Size (LC)

~4x run-time

advantage

More

predictable

run-times

Run-time Comparison for 100+ designs

Xilinx Competition

Supports multi-million LC designs where competition fails

(scalable to 100M gates)


Only Vivado can route design with:

– High routing Complexity

– High utilization

Runtime advantage increases with:

– Routing Complexity

– Device Utilization

QoR Advantage

– Up to 3 speed grades vs. Competitor’s

28nm solution

Vivado Game Changing Implementation Results

Ro

uti

ng

Co

mp

lex

ity o

f d

es

ign

20x

12x 12x 12x

6x 6x 6x 6x

4x 4x 4x 4x 5x

3x 3x 3x 4x 5x

2x 2x 3x 4x 5x

2x 2x 3x 4x 5x

2x 2x 3x 4x 5x

30% 40% 50% 60% 70% 80%

Device Utilization

Runtime Comparison 48 Designs of Increasing Size

and Routing Complexity

Competition

Vivado 2012.2

Nx

Runtime ratio

Competition / Vivado

Only Vivado can

route these designs


Team design or module reuse

– Implement modules out of context from top level design

– Iterate without overhead of the full design

Partial reconfiguration

– Provides system flexibility

– Reduces cost, size and total power

IP-XACT Packaged modules for reuse in new designs

– Reuse pre-verified placed & routed modules

– Accelerates design re-use and leverages your IP

Rapid ECO changes

– Incremental Implementation, 3x faster than recompile

– Post P&R edits with Vivado Device Editor

Hierarchical flows are in Beta now, production release 2013

Flexible Design Flows Accelerate Productivity


Vivado: From Months to Weeks, A Generation Ahead

a generation ahead - gongterr.co.kr seminar_overview_william.… · –timed (architectural): vhdl,...

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