chris h. kim, kaushik roy, steven k. hsu*, ram k....
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1
An On-Die CMOS Leakage Current Sensor for Measuring
Process Variation in Sub-90nm Generations
Chris H. Kim, Kaushik Roy, Steven K. Hsu*, Ram K. Krishnamurthy*, Shekhar Borkar*
Purdue University, West Lafayette, IN*Circuit Research, Intel Labs,
Intel Corporation, Hillsboro, ORIntel Labs
2
Outline
Motivation and prior art
Proposed leakage sensing technique
Leakage sensor test chip implementation
in 90nm
Leakage binning results
Conclusions
3
Process Variation
0.4
0.6
0.8
1.0
1.2
1.4
0.01 0.1 1 10 100Normalized IOFF
Nor
mal
ized
I ON
NMOSPMOS
100X
2X
150nm CMOS, 110°C
IOFF spread > 100X, ION spread > 2XDevice parameters are NOT deterministic any more
4
Off-current meas.Off-current meas.
Process Variation Detection
Sub-threshold CMOS device:
T. Kuroda, JSSC, Nov. 1996
Test row devicesProcess monitor
Decay sensors
Strong inversion CMOS device:
M. Griffin, JSSC, Nov. 1998Y. Kim, IEICE, Nov. 1999
Delay line:M. Miyazaki, ISLPED, Aug. 1998
On-current meas.On-current meas.
Process detection method optimized for each applicationResolution, area, complexity, testing cost, etc.
5
Leakage Variations Impact
Dynamic circuit NMOS pull-down leakage variation:Keeper size determined for target robustness at worst-case leakage cornerExcess leakage dies: fail to meet target robustnessLower leakage dies: over-designed for robustness
Dynamic 8-way Bitline
0.7
1
1.3
1.6
0.25 1 1.75
Nor
mal
ized
Del
ay
Keeper upsizin
g 20%
5%
10%
DC noise robustness
8%
Target robustness
clk
...RS0
D0
RS1
D1
RS7
D7
Dyn_out
WKPR
R. Krishnamurthy et al, VLSI Circuits Symp. 2001
6
Target Application: Process Compensating Dynamic Circuit
3-bit programmable conditional keeper
clk
. . .RS0 RS7
D0 D7
RS1
D1
LBL0
LBL1
N0
b[2:0]
W 2W 4Ws s s
On-die leakage current sensor required to generate b[2:0] based on NMOS pull-down leakage
Conventional
C. Kim, S. Hsu et al, VLSI Circuits Symp. 2003
7
Usage Model and Design Goal for On-Die Leakage Sensor
83μm
73μ
m
current reference
comparators
current m
irrors
VBIASgen.
NMOS device
test interface
High leakage sensing gain (> 3b resolution)No complicated timing controlCompact analog design
On-Die Leakage Sensors
8
Previous Leakage Current Sensing Circuits
Susceptible to P/N skew and supply fluctuationLarge area due to multiple analog bias circuitsLimited leakage sensing gain
+- d0
IREFd0VBIAS
+-
VSEN
VDD/2
VSEN
T. Kuroda et al., JSSC, Nov. 1996 M. Griffin et al., JSSC, Nov. 1998
9
Proposed Single Channel Leakage Sensing Circuit
Basic principle: Drain induced barrier loweringLow sensitivity to P/N skew and supply fluctuation
IREF
M1 (saturation)
M2 (subthreshold)
+-
VBIAS+- d0
VREF
VSEN
10
PV Insensitive Current Reference (IREF)
• Sub-1V process, voltage compensated MOS current generation concept
• Reference voltage, external resistor not required• Scalable, low cost, flexible solution
2/0.4
2/0.4
6/0.4
6/0.4
1/1.6
18/0.4
18/0.4
18/0.4
6/0.4 2/0.4
6/0.8 6/0.8 4/0.8 4/0.8
IREF
Vt generation circuit Subtraction circuit
S. Narendra et al., VLSI Circuits Symp. 2001
11
PV Insensitive Bias Voltage (VBIAS)
8/0.4 1/0.4
96/0.2
2/0.2IREF
VBIAS )(log2
1=WW
qkT
(W1=96μm, W2=2μm)
E. Vittoz et al., JSSC, June 1979
• PTAT containing no resistive dividers• Based on weak inversion MOS characteristics• Desired output voltage achieved via sizing
12
Comparator
• 2-stage differential amplifier• Already designed IREF is used for bias current
4/0.4 4/0.4
8/0.48/0.4 8/0.4
4/0.44/0.4
+- =
(+)(-)
output
IREF
Subtraction circuit
13
PV Sensitivity of Designed IREF, VBIAS
• IREF variation < 4%, VBIAS variation < 2%• Under realistic process skews, ±100mV supply
voltage fluctuations
1.2V, 90nm CMOS, 80˚C
VDD (V)
1.00 0.991.000.99 1.00 1.00
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.1 1.2 1.3
IREFVBIAS
1.011.000.99 1.000.99 1.01
0.0
0.2
0.4
0.6
0.8
1.0
1.2
fast typical slow
Process skew
IREFVBIAS
14
Proposed Leakage Current Sensing
IREF
M1 (saturation)
M2 (sub-threshold)
+-
VBIAS+- d0
VREF
VSEN
PMOS M1
0 0.2 0.4 0.6 0.8 1 1.2
VSEN (V)
I ds
fasttypicalslow
0 0.2 0.4 0.6 0.8 1 1.2
VSEN (V)
I ds
fasttypicalslow
NMOS M2
1.2V, 90nm CMOS, 80˚C
15
Superimposed I-V Curves
• 1.9-10.2X higher VSEN swing than prior-art• Process-voltage insensitive design
0 0.2 0.4 0.6 0.8 1 1.2
VSEN (V)
I ds
slowtypicalfast
1.2V, 90nm CMOS, 80˚C
∆VSEN=0.93V
16
6-Channel Leakage Sensor Test Chip
IREF+-
VBIAS
-+
WP 2WP 3WP 4WP 6WP 9WP
WN
VSEN
1
VREF
Bubblerejection
circuit
V1 V2 V3 V4 V5 V6
V1V2V3
V1V4V5
V2V4V6
OUT[2]
OUT[1]
OUT[0]
WN WN WN WN WN
VSEN
2
VSEN
3
VSEN
4
VSEN
5
VSEN
6
Incremental mirroring ratio for multi-bit resolution leakage sensingShared bias generators compact designProcess-voltage insensitive IREF, VBIAS gen.
-+ -+ -+ -+ -+
17
Multi-Bit Resolution Leakage Sensing
Leakage level determined by comparing VSEN1 through VSEN6 with VREF6-channel leakage sensor gives 7 level resolution
0
0.2
0.4
0.6
0.8
1
1.2
fast typical slow
Volta
ge (V
) VSEN6VSEN5VSEN4VSEN3VSEN2VSEN1VREF
Process skew
1.2V, 90nm CMOS, 80˚C
18
Example: Operation at Fast Process Corner
IREF+-
VBIAS
WP 2WP 3WP 4WP 6WP 9WP
WN
VSEN
1
VREF
Bubblerejection
circuit
V1 V2 V3 V4 V5 V6
V1V2V3V1V4V5V2V4V6
OUT[2]
OUT[1]
OUT[0]
WN WN WN WN WN
VSEN
2
VSEN
3
VSEN
4
VSEN
5
VSEN
6
1 1 1 1 0 0
1 1 1 1 0 1
00.20.40.60.8
11.2
fast typical slow
Volta
ge (V
)
VREF
1
0
1
-+ -+ -+ -+ -+ -+
Fast corner: output code ‘101’
19
Example: Operation at Typical Process Corner
IREF+-
VBIAS
WP 2WP 3WP 4WP 6WP 9WP
WN
VSEN
1
VREF
Bubblerejection
circuit
V1 V2 V3 V4 V5 V6
V1V2V3V1V4V5V2V4V6
OUT[2]
OUT[1]
OUT[0]
WN WN WN WN WN
VSEN
2
VSEN
3
VSEN
4
VSEN
5
VSEN
6
1 0 0 0 0 0
1 0 1 1 1 1
00.20.40.60.8
11.2
fast typical slow
Volta
ge (V
)
VREF
0
1
0
-+ -+ -+ -+ -+ -+
Typical corner: output code ‘010’
20
current reference
comparators
current m
irrors
VBIASgen.
NMOS devices
test interface
6 channels (7 levels)Resolution1.2VVDD
83 X 73 μm2Dimensions 0.66 mW @ 80°CPower consumption
90nm dual-Vt CMOSTechnology
On-Die Leakage Sensor Test Chip
21
Leakage Sensor Results
• Effective leakage binning for PCD technique• Scalable beyond 90nm generation
001 010 011 100 101 110 111Output codes from leakage sensor
Leakage current (normalized)
I DSA
T(n
orm
aliz
ed)
Die
cou
nt (%
) 1.2V, 90nm CMOS, 80˚C
22
ConclusionsPost silicon tuning is becoming promising for process compensationOn-die leakage current sensors assist inter/intra-die process compensationMulti-channel leakage current sensor– No complicated timing control– 1.9-10.2X higher sensitivity to leakage– Shared analog components for compact
design
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