ap bl ad ti pha programmable adaptive phase- shiftinggg...
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A P bl Ad ti PhA Programmable Adaptive Phase-Shifting PLL for Enhancing Clock g g
Data Compensation under Resonant Supply NoiseResonant Supply Noise
Dong Jiao and Chris H. Kim
University of Minnesota, Minneapolis
Agenda• Resonant supply noise and clock
data compensation effectdata compensation effect• Clock modulation and adaptive p
clocking techniqueP d h hifti PLL• Proposed phase-shifting PLL
• 65nm test chip results65nm test chip results• Conclusions
2
Resonant Supply NoiseN. Kurd, Intel, JSSC 2009
• IR and Ldi/dt noise: 10-15% of nominal Vdd
• Resonance between package/bondingResonance between package/bonding inductance and die capacitance
• Typical resonant frequency: 40-300MHzTypical resonant frequency: 40 300MHz• Large magnitude, affects the entire chip
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Clock Data CompensationDatapath
Clock path
Supply Nominal Vdd
PLL
Nominal Vdd
CLK
Supply voltage
DatapathCLK
Datapath output
P P P F P P P P P P P P P PF F F FConstant-period clock Actual clock
PassP: F : Fail
• Both clock and data are affected by resonant supply noise
• Modulated clock can partially compensate for the datapath delay increase
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Existing Clock Modulation SchemesVDD
10% dip in core supply
2% dip in filtered supply
Clock buffer
[3] I t l N h l N[1] Intel Pentium 4, N. Kurd, et al., JSSC’01
[2] D. Jiao, et al., JSSC’10
[3] Intel Nehalem, N. Kurd, et al., JSSC’09
Cl k di t ib ti ith RC filt d l• Clock distribution with RC-filtered supply• Clock buffers with built-in RC filters
N i iti PLL ti d ti l k
5
• Noise sensitive PLL generating adaptive clock
Adaptive Clocking Technique
DD
clk
clk
clk
• Point A coincides with E for best compensation• Adjust both phase shift & supply noise
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sensitivity for optimal compensation
Proposed Phase-Shifting PLL
AVDD...
DVDD
AVDD2C
C
C 6
Cu
Ceq=(Cu+Cd)||Cf
SV=Cu/CdCf
VCP, VCN
AVDD
AVDD
...
AVDD
VCP25C6
C 2C 26C
C 2C 26C
...
M2
VCN
VCP
IN+ IN-OUT+OUT-
VCPVB VCN26CM1
Cd
AVDD
UPD
RST
Q
+-
VREFVB
AVDD VCN
Ref. clock Supply
Tracking Differential VCP
DN
D
RST
Q
-+
VREF
AVDD
Tracking Modulator
VCOVCN
AVDD: PLL VDD
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AVDD
Freq. dividerDVDD: Digital VDD
Noise Sensitivity & Phase Shift Controlge
(V)
trol
vol
tag
PLL
cont
• S (=C /Cd) controls supply noise sensitivitySv ( Cu/Cd) controls supply noise sensitivity• Ceq (=Cf ||(Cd+Cu)) controls phase shift and
noise sensitivity
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noise sensitivity• Both Sv and Ceq are digitally programmable
Test Chip OrganizationTiming
RST
10b ripple counter
gerror
BER<9:0>PLL Logic and
interconnect th
CLK...
...
x8
CLK
AVDD
pathsH-tree clock networks
BER<n>
TBER
x 2n+1% of timing errors = TCLK
TREESEL
VB2
OUT
DVDDSEL<> x32
x 2% of timing errors = TBER
...VB1
DVDD GND
Local supply noise monitorx16
Switches for colored noise
VCO & clock pattern control
...
x16
SEL<> ...
Clock tree Buffer style Interconnect#1
Inverter(single ended)
None#2 Short#3 Medium#4 Long#5 Short
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Supply noise generation blocks
LFSRs for random noise#5 Differential Short#6 Long#7 RC buffer [5] Short#8 Long
Die Photo & Performance Summary
Random noise
i j ti
Datapath & BER monitor
Local noise
monito
Phase-
injection (LFSRs) Clock
distribution (8 clock trees)
o tor
shifting PLL trees)Resonant
noise injection Technology
T t l
65nm LP CMOS
350 250 2Total area
Regulation frequency
350 x 250 µm2
40MHz-300MHzSensiti
vity
NoneConv.
Modulation
Phase shift
Programmable
1st droop
VDD
PLL area
Fmax
1.2V
120 x 100 µm2Clock path
Conv.
[1][2]
PLL[3]
10
Fmax improvement 3.4%-7.3%PLLThis
work
BER Measurements & Noise Patterns
• BER increases quickly at higher fclk
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q y g clk
• Define Fmax as clock frequency when BER=10-6
Fmax vs. Noise Sensitivity & Phase Shift
Equiv
Equivvalent cap
valent cappacitance (
pacitance (Ceq )
(Ceq )
• Chip tested at different Vdd and fnoise
• Optimal configuration varies significantly on
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Optimal configuration varies significantly on operating condition
Fmax vs. Noise FrequencyVDD=1.2V, first droop noise VDD=1.0V, sinusoidal noise
7%1.11 7.5%0.69
% improvement % improvement
4%1.06
(GH
z) 5%0.66
This This work(GH
z)
1%1.01
F max
(
2.5%0.63
Conventional
work
Conventional
F max
-2%0.968 32 128 512
Noise Frequency (MHz)
1%0.68 32 128 512
Noise Frequency (MHz)
• Tested under different Vdd & noise waveform• 3-7% improvement on F for typical resonant
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• 3-7% improvement on Fmax for typical resonant band (40-300MHz) at 1.2V and 1.0V
Fmax vs. Different Clock Trees
• Tested under different Vdd, fnoise and noise patt.• 3-7% improvement on F with various clock
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• 3-7% improvement on Fmax with various clock distribution designs under 1.2V and 1.0V
Conclusions• Resonant noise is an important concern
in power supply network designs• Inherent timing compensation between
clock and data improves Fmax
• A 65nm phase-shifting PLL demonstrated– Enhances clock data compensation effecta ces c oc data co pe sat o e ect– Programmable supply noise sensitivity and
phase shift for optimal compensationp p p– 3-7% Fmax improvement for typical resonant
noise frequencies (40-300MHz)
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