8- xilinx fpga

Digital System DesignLecture 8: Xilinx FPGAs

Amir Masoud Gharehbaghiamgh@mehr.sharif.edu

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Table of Contents

IntroductionXilinx FPGAs

XC3000XC4000XC5000New series

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Introduction

The largest manufacturer of SRAM-based FPGAsMain Families:

XC2000XC3000XC4000XC5000…

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Xilinx Series Comparison

6000-15000

784-1,936

196-484

148-244

XC5000

1,600-25,000

256-2,569

64-1,024

64-256XC4000

1,300-9,000

256-1,320

64-48464-176XC3000

800-1,800

122-174

64-10058-74XC2000

Gate Count

FFsCLBsI/O Blocks

Series

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Xilinx FPGA Structure

Fixed array of Configurabe Logic Blocks (CLBs) connectable by a system of pass-transistors, driven by SRAM cells

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XC3000 CLB

32-bit (5-input) look-up tableCLB propagation delay is fixed (LUT access time) and independent of the logic function7 inputs to the XC3000 CLB:

5 CLB inputs (A–E)2 FF outputs (QX and QY)

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XC3000 CLB ConfigurationsUse 5 (of 7) inputs with the entire 32–bit LUT (CLB outputs F and G are then identical)Split the 32-bit LUT in half to implement 2 functions (F and G) of 4 variables each; choose 4 inputs (from 7)Split the 32-bit LUT in half, using one of the 7 input variables as a select input to a 2:1 MUX that switches between F and G (to implement some functions of 6 and 7 variables)

1

2

3

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Methods of InterconnectionDirect interconnect: Adjacent CLBs are wired together in the horizontal or vertical direction. The most efficient interconnect (< 1 ns delay)General-purpose interconnect: used mainly for longer connections or for signals with a moderate fan-out

Few, so problem in fitting a large design into XC3000, and 2000

Long line interconnect: for time critical signals (e.g. clock signal need be distributed to many CLBs)

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Design Example

Q2* = Q2’ Q1 + Q2 Q0Q1* = X’ Q2’ Q1’ Q0 + X’ Q2’ Q0’ + X’ Q2 Q0’ + Q1 Q0Q0* = Q0’Z = X Q1 + X’ Q1’

Functions have maximum 4 variables4 LUT of 4 variables3 FFs2 CLB required

FPGA ImplementationQ2*, Q0* in one CLBQ1*, Z in one CLB

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Design Example Implementation

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Xilinx 4000 Series

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Xilinx 4000 Specs

Two FF per CLB + Two per I/O cell25 gates per CLB for logic32 bits of RAM per CLBSpecial fast carry logic between CLBsInterconnects:

Direct and general-purpose wires replaced with more efficient single-length and double-length lines.Sufficient resources for most applications.

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Xilinx 4000 CLB

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CLB Function Generators

Use RAM for truth tablesF, G: 4 input -> 16 bits of RAM (each)H: 3 input –> 8 bits of RAMRAM is loaded at system initialization from external PROM

MUX control logic maps 4 control inputs into 4 inputs:

LUT input H1Direct In (DIN)Enable Clock (EC)Set/Reset control (S/R) for FFsControl F,G LUTs as 32 bit SRAM

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CLB Function Generators (cont.)

Broad capability:Any 2 functions of 4 variables plus a function of 3 variablesAny function of 5 variablesAny function of 4 variables plus some functions of 6 variablesSome functions of 9 variables

Parity4-bit cascadable equality checking

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CLB input and output connections

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Programmable Switch Matrix

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XC5200 Logic Block

Similar to CLBs in XC2000/3000/4000, but simplerA group of 4 Logic Cells (LCs) is a CLB in XC5200LC contains 4-input LUT

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State-of-the-art FPGAs

XCS00/XL (Spartan)5v, 3v2,000-40,000 typical gate

XC2S00/XL (Spartan-II)2.5v6,000-150,000 typical gate

XCV00 (Virtex)2.5v34,000-1,124,000 typical gate

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State-of-the-art FPGAs (cont.)

1999: Virtex-E2000: Virtex-II2002: Vitex-II Pro

125,136 logic cell10 Mb RAM556 18*18 MultiplierUp to 4 PowerPC 405 cores

300 MHz+, 420 MIPS