lecture 10 xilinx fpga memories part 1
DESCRIPTION
ECE 448 – FPGA and ASIC Design with VHDL Recommended reading Spartan-6 FPGA Block RAM Resources: User Guide Google search: UG383 Spartan-6 FPGA Configurable Logic Block: User Guide Google search: UG384 Xilinx FPGA Embedded Memory Advantages: White Paper Google search: WP360 ISE In-Depth Tutorial, Section: Creating a CORE Generator Tool Module Google search: ISE In-Depth Tutorial ECE 448 – FPGA and ASIC Design with VHDLTRANSCRIPT
ECE 448 – FPGA and ASIC Design with VHDL
Lecture 10
Xilinx FPGA Memories
Part 1
2ECE 448 – FPGA and ASIC Design with VHDL
Recommended reading• Spartan-6 FPGA Block RAM Resources: User Guide
Google search: UG383
• Spartan-6 FPGA Configurable Logic Block: User Guide
Google search: UG384
• Xilinx FPGA Embedded Memory Advantages: White Paper
Google search: WP360
• ISE In-Depth Tutorial, Section: Creating a CORE Generator Tool Module
Google search: ISE In-Depth Tutorial
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Memory Types
4
Memory Types
Memory
RAM ROM
Single port Dual port
With asynchronous read
With synchronous read
Memory
Memory
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Memory Types specific to Xilinx FPGAs
Memory
Distributed (MLUT-based)
Block RAM-based(BRAM-based)
Inferred Instantiated
Memory
Manually Using CORE Generator
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FPGA DistributedMemory
7
Location of Distributed RAMRAM blocks
Multipliers
Logic blocks
Graphics based on The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
DSP unitsRAM blocks
Logic resources
(#Logic resources, #Multipliers/DSP units, #RAM_blocks)
Logic resources(CLB slices)
8ECE 448 – FPGA and ASIC Design with VHDL
Three Different Types of Slices
50% 25% 25%
9
16-bit SR
16 x 1 RAM
4-input LUT
The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Spartan-6 Multipurpose LUT (MLUT)
64 x 1 ROM
(logic)
64 x 1 RAM
32-bit SR
10ECE 448 – FPGA and ASIC Design with VHDL
Single-port 64 x 1-bit RAM
11
Memories Built of Neighboring MLUTs
ECE 448 – FPGA and ASIC Design with VHDL
• Single-port 128 x 1-bit RAM: RAM128x1S• Dual-port 64 x 1-bit RAM : RAM64x1D
Memories built of 2 MLUTs:
Memories built of 4 MLUTs:
• Single-port 256 x 1-bit RAM: RAM256x1S• Dual-port 128 x 1-bit RAM: RAM128x1D• Quad-port 64 x 1-bit RAM: RAM64x1Q• Simple-dual-port 64 x 3-bit RAM: RAM64x3SDP (one address for read, one address for write)
12
Dual-port 64 x 1 RAM
ECE 448 – FPGA and ASIC Design with VHDL
• Dual-port 64 x 1-bit RAM : 64x1D• Single-port 128 x 1-bit RAM: 128x1S
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Total Size of Distributed RAM
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FPGA Block RAM
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Location of Block RAMsRAM blocks
Multipliers
Logic blocks
Graphics based on The Design Warrior’s Guide to FPGAsDevices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
DSP unitsRAM blocks
Logic resources
(#Logic resources, #Multipliers/DSP units, #RAM_blocks)
Logic resources(CLB slices)
16
Spartan-6 Block RAM Amounts
17
Block RAM can have various configurations (port aspect ratios)
0
16,383
1
4,095
40
8,191
20
2047
8+10
1023
16+20
16k x 1
8k x 2 4k x 4
2k x (8+1)
1024 x (16+2)
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19
20
Block RAM Port Aspect Ratios
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Block RAM Interface
22
Block RAM Ports
23
Block RAM with synchronous readin Read-First Mode
CE
24
Features of Block RAMs in Spartan-6 FPGAs