1 ee121 john wakerly lecture #12 pld-based state machine structures with statements finite-memory...

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EE121 John Wakerly Lecture #12

PLD-based state machine structures

WITH statements

Finite-memory state-machine design

PLD-based state-machine design

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PLD-based state-machine

timing

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Multiple PLDs

registeredpipelined

registeredpipelined

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Normal vs. pipelined Moore outputs• Assume 3 state variables, Q1, Q2, Q3.

Z = G(Q1, Q2, Q3) [Moore output]

Z := ?? [equivalent pipelined Moore output]

• Transition equationsQ1 := F1(Q1,Q2,Q3,inputs);

Q2 := F2(Q1,Q2,Q3,inputs);

Q3 := F3(Q1,Q2,Q3,inputs);

• Pipelined output equation:Z := G( F1(Q1,Q2,Q3,inputs), F2(Q1,Q2,Q3,inputs),

F3(Q1,Q2,Q3,inputs) );

• Can’t do this with Mealy outputs unless “inputs” are applied one clock tick earlier.

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WITH statements

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Example: Another combination lock

• Unlock after input sequence 0110111• Also provide “hint” output (1 => correct move).

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WITH recommendations

• If you must use WITH statements, be sure to assign an output value for all states/transitions.

• Be very careful about registered vs. combinational assignments.

• It’s usually more convenient to specify output values using separate equations in the “equations” section of the program:

UNLK = (S==X0110111) & (X==0);HINT = (S==ZIP) & (X==0) # (S==X0) & (X==1) ... # (S==X0110111) & (X==0);

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Finite-Memory State Machines

• In general, a state machine’s future operation depends on all the inputs it received since reset.

• Some state machines depend only on the inputs received over the last few clock ticks.

• Idea:– Use a register to keep track of the machine’s input

values over the last few clock ticks.– Determine the current output as a combinational

function of the past inputs history.

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Example: the combination lock again

This program has a bug(I can unlock in just sixclock ticks after reset.)

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T-bird tail-lights example

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Statediagram

Inputs:LEFT, RIGHT, HAZ

Outputs:Six lamps(function of state only

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ABEL program

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ABEL “state diagram”

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Output logic

• Implement this table in another PLD that has Q2, Q1, Q0 (QSTATE) as inputs.

• Total # of PLD outputs is 3 + 6 = 9.

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Output-coded state assignment

• Each state has a unique encoding using just the lamp-output bits.

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Sunnyvale Traffic-Light Controller

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Traffic-Light I/O

• Inputs– NSCAR (north-south car sensors)– EWCAR (east-west car sensors)– TMSHORT (short timer -- 5 seconds)– TMLONG (long timer -- 5 minutes)

• Outputs– NSRED, NSYELLOW, NSGREEN (lights)– EWRED, EWYELLOW, EWGREEN (lights)– TMRESET (timer start)

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State Diagram (ABEL)

• Outputs will be a function of state

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• East-west states are symmetric.

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State encoding

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Output logic

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Output-coded state assignment

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Next Time

• Digital-to-analog conversion• Analog-to-digital conversion• Read D-to-A and A-to-D notes