advanced vlsi chap3-3

7/28/2019 ADVANCED VLSI CHAP3-3

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Modern VLSI Design 4e: Chapter 3 Copyright 2008 Wayne Wolf

Topics

Wire delay.

Buffer insertion.

Crosstalk.

Inductive interconnect.

Switch logic.


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Wire delay

Wires have parasitic resistance, capacitance.

Parasitics start to dominate in deep-

submicron wires.

Distributed RC introduces time of flight

along wire into gate-to-gate delay.


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RC transmission line

Assumes that dominant capacitive coupling

is to ground, inductance can be ignored.

Elemental values are ri, c

i.


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Elmore delay

Elmore defined delay through linear

network as the first moment of the network

impulse response.


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RC Elmore delay

Can be computed as sum of sections:

E= r(n - i)c = 0.5 rcn(n-1)

Resistor rimust charge all downstream

capacitors.

Delay grows as square of wire length. Minimizing rc product minimizes growth of

delay with increasing wire length.


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RC transmission lines

More complex analysis.

Step response:

V(t) 1 + 1exp{

1t/RC}.


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Wire sizing

Wire length is determined by layout

architecture, but we can choose wire width

to minimize delay. Wire width can vary with distance from

driver to adjust the resistance which drives

downstream capacitance.


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Optimal wiresizing

Wire with minimum delay has an

exponential taper.

Optimal tapering improves delay by about

8%.


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Approximate tapering

Can approximate optimal tapering with a few

rectangular segments.


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Tapering of wiring trees

Different branches of tree can be set to

different lengths to optimize delay.

source

sink 1

sink 2


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Spanning tree

A spanning tree has segments that go directly

between sources and sinks.

source

sink 1

sink 2


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Steiner tree

A Steiner point is an intermediate point for

the creation of new branches.

source

sink 1

sink 2

Steiner point


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RC trees

Generalization of RC transmission line.


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Buffer insertion in RC

transmission lines

Assume RC transmission line.

Assume R0is drivers resistance, C

0is

drivers input capacitance.

Want to divide line into k sections of length

l. Each buffer is of size h.


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Buffer insertion analysis

Assume h = 1:

k = sqrt{(0.4 Rint

Cint)/(0.7R

0C

0)}

Assume arbitrary h:

k = sqrt{(0.4 Rint

Cint)/(0.7R

0C

0)}

h = sqrt{(R0C

int)/(R

intC

0)}

T50%

= 2.5 sqrt{R0C

0R

intC

int}


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Buffer insertion example

Minimum-size inverter drives metal 1 wire

of 2000 x 3 .

R0= 3.9 k, C0= 0.68 fF, Rint= 53.3 k, Cint=

105.1 fF.

Then

k = 1.099.

H = 106.33.

T50%

= 9.64 E-12


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RC crosstalk

Crosstalk slows down signals---increases

settling noise.

Two nets in analysis:

aggressor net causes interference;

victim net is interfered with.


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Aggressors and victims

victim net

aggressor net


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Wire cross-section

Victim net is surrounded by two aggressors.

victimaggressor aggressor

substrate

WS

T

H


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Crosstalk delay vs. wire aspect

ratio

Increasing aspect ratio

relativeRCd

elay

increased spacing


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Crosstalk delay

There is an optimum wire width for any

given wire spacing---at bottom of U curve.

Optimium width increases as spacing

between wires increases.


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RLC transmission lines

Most results come from curve fitting.

Propagation delay is largely a factor of.

50% propagation delay can be calculated in

terms of.


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Kahng/Muddu model

Analytical model of similar complexity to

Elmore model.

Let Rs, Ls be source impedance, Rint, Cint, Lint

be transmission line impedance, CLbe load

impedance.

Delay t = KC2b

2/sqrt(4b

2 b

1

2), KCusually

1.66.


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Switch logic

Can implement Boolean formulas as

networks of switches.

Can build switches from MOS transistorstransmission gates.

Transmission gates do not amplify but have

smaller layouts.


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Types of switches


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Behavior of n-type switch

n-type switch has source-drain voltage drop

when conducting:

conducts logic 0 perfectly;

introduces threshold drop into logic 1.

VDD

VDD

VDD

- Vt


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n-type switch driving static logic

Switch underdrives static gate, but gate

restores logic levels.

VDD

VDD

VDD - Vt

t it h d i i it h


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n-type switch driving switch

logic

Voltage drop causes next stage to be turned

on weakly.

VDD VDD - Vt

VDD

B h i f l t


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Behavior of complementary

switch

Complementary switch products full-supply

voltages for both logic 0 and logic 1:n-type transistor conducts logic 0;

p-type transistor conducts logic 1.


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Layout characteristics

Has two source/drain areas compared to one

for inverter.

Doesnt have gate capacitance.

advanced vlsi chap3-3

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