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  • 7/28/2019 ADVANCED VLSI CHAP7-1

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Topics

    Block placement.

    Global routing.

    Switchbox routing.

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Floorplanning strategies

    Floorplanning must take into account

    blocks of varying function, size, shape.

    Must design:

    space allocation;

    signal routing;

    power supply routing;

    clock distribution.

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    data path

    RAM

    std cell

    Bricks-and-mortar floorplan

    blocks

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Purposes of floorplanning

    Early in design:

    Prepare a floorplan to budget area, wire

    area/delay. Tradeoffs between blocks can benegotiated.

    Late in design:

    Make sure the pieces fit together as planned.Implement the global layout.

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Types of routing

    Channel routing:

    channel may grow in one dimension to

    accommodate wires;

    pins generally on only two sides.

    Switchbox routing:

    cannot grow in any dimension;

    pins are on all four sides, fixing dimensions of

    the box.

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Channels and switchboxes

    channel switchbox

    channel

    switchboxpins

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Block placement

    Blocks have:

    area;

    aspect ratio.

    Blocks may be placed at different rotations

    and reflections.

    Uniform size blocks are easier to

    interchange.

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Blocks and wiring

    Cannot ignore wiring during block

    placementlarge wiring areas may force

    rearrangement of blocks.

    Wiring plan must consider area and delay

    of critical signals.

    Blocks divide wiring area into routingchannels.

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Channel definition

    Channels end at block boundaries.

    Several alternate channel definitions are

    possible:

    A

    B C

    channel 1

    ch 2

    ch 1 ch 2

    ch 3

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Channel definition changes with

    block spacing

    Changing spacing changes relationship

    between block edges:

    A

    B C C

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Channel graph

    A BC

    D

    E

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Channel graph usage

    Nodes are channels, edges placed between

    two channels that touch.

    Channel graph shows paths between

    channels.

    Channel graph can be used to guide global

    routing.

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Channels must be routed in order

    Wire out of end of one channel creates pin on

    side of next channel:

    channel A

    channel B

    constraint

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Windmills

    Can create an unroutable combination of

    channels with circular constraints:

    A B

    CD

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Slicable floorplan

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Slicability property

    A slicable floorplan can be recursively cut

    in two without cutting any blocks.

    A slicable floorplan is guaranteed to haveno windmills, therefore guaranteed to have

    a feasible order of routing for the channels.

    Slicability is a desirable property forfloorplans.

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Global routing

    Goal: assign wires to paths through

    channels.

    Dont worry about exact routing of wireswithin channel.

    Can estimate channel height from global

    routing using congestion.

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Line probe routing

    Heuristic method for finding a short route.

    Works with arbitrary combination of

    obstacles.

    Does not explore all possible pathsnot

    optimal.

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    Line probe example

    A

    A

    line 1

    line 2

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Channel utilization

    Want to keep all channels about equally

    full to minimize wasted area.

    Important to route time-critical signalsfirst.

    Shortest path may not be best for global

    wiring.

    In general, may need to rip-up wires and

    reroute to improve the global routing.

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Switchbox routing

    Cant expand a switchbox to make room

    for more wiring.

    Switchbox may be defined by intersectionof channels.

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    Modern VLSI Design 4e: Chapter 7 Copyright 2008 Wayne Wolf

    Routing order and switchboxes

    Switchboxes frequently need more

    experimentation with wiring order because

    nets may block other nets:

    B

    A B

    A

    B blocks A