physics of advanced cmos vlsi
TRANSCRIPT
Dennis BussTexas Instruments, Inc.
Dallas, Texas USA
Physics of Advanced CMOS VLSIPhysics of Advanced CMOS VLSI
ConclusionsFor the past 35 years, transistors have been developed using “Electrical Engineering Physics”, which was codified in the early 60’s
As the industry approaches the “End of Roadmap”, Electrical Engineering Physics is no longer sufficient. Technology development increasingly requires– Sophisticated quantum physics– Non-equilibrium Boltzmann transport– Material science at the atomic and electron
orbital level
This has implications for– Physics education– Career opportunities for physicists in the
semiconductor industry
For the past 35 years, transistors have been developed using “Electrical Engineering Physics”, which was codified in the early 60’s
As the industry approaches the “End of Roadmap”, Electrical Engineering Physics is no longer sufficient. Technology development increasingly requires– Sophisticated quantum physics– Non-equilibrium Boltzmann transport– Material science at the atomic and electron
orbital level
This has implications for– Physics education– Career opportunities for physicists in the
semiconductor industry
Agenda
Introduction to CMOS VLSI Technology
Physics challenges to continued VLSI scaling
Conclusion
Introduction to CMOS VLSI Technology
Physics challenges to continued VLSI scaling
Conclusion
US Patent # 3,138,743 Filed Feb. 6, 1959
Integrated Circuit – 1958
SiO21200 A
Gate LengthOxide ThicknessGate MaterialJunction DepthInterconnectMask Levels
Gate LengthOxide ThicknessGate MaterialJunction DepthInterconnectMask Levels
MOS Scaling
Late 60's
Late 60'sLate 60's 2000200010 µm
120 nmAl
2.5 µmAl5
10 µm120 nm
Al2.5 µm
Al5
120 nm12 A
poly-Si25/70 nm
Cu25 - 35
120 nm12 A
poly-Si25/70 nm
Cu25 - 35
Metal Gate
10 µm
1200 A
2000
2.5 µm
Modern CMOSModern CMOS
Beginning ofSubmicron CMOS
Beginning ofSubmicron CMOS
Deep UV LithoDeep UV Litho
90 nm in 200490 nm in 2004
Presumed Limitto Scaling
Presumed Limitto Scaling
Moore's Law10 um
1 um
100 nm
10 nm
1 nm1970 1980 1990 2000 2010 2020
34 Years of Scaling History
Every generation– Feature size shrinks by 70%– Transistor density doubles– Wafer cost increases by 20%– Chip cost comes down by 40%
Generations occur regularly– On average every 2.9 years over
the past 34 years– Recently every 2 years
Feature SizeTransistor DensityChip SizeTransistors/ChipClock FrequencyPower DissipationFab CostWW IC RevenueWW Electronics
Revenue
Feature SizeTransistor DensityChip SizeTransistors/ChipClock FrequencyPower DissipationFab CostWW IC RevenueWW Electronics
Revenue
19701970 TodayToday
6 um
~10 mm2
1000100 kHz
~100 mW~$10 M$700 M$70 B
6 um
~10 mm2
1000100 kHz
~100 mW~$10 M$700 M$70 B
ChangeChange
34 Years of History
90 nm
~400 mm2
200 M> 1 GHz~100 W>$1 B$170 B$1.1 T
90 nm
~400 mm2
200 M> 1 GHz~100 W>$1 B$170 B$1.1 T
70x Reduction5000x Increase
40x Increase200,000x Increase>10,000x Increase
~1000x Increase>100x Increase
240x Increase16x Increase
70x Reduction5000x Increase
40x Increase200,000x Increase>10,000x Increase
~1000x Increase>100x Increase
240x Increase16x Increase
Electrical Engineering Physics
f(E) = f(E) = 1
e (E - E )/kT + 1F
p = Nv e – (F - E )/kTp = Nv e – (F - E )/kTp v
= = ( p - n + Nd - Na ) = = ( p - n + Nd - Na ) d2V(x)
dx2+ρ (x)
εq -
n = Nc e – (E - F )/kTn = Nc e – (E - F )/kTc n
Jn(x) = qµnn(x)ε(x) + qDnJn(x) = qµnn(x)ε(x) + qDndn(x)
dx
Jp(x) = qµp p(x)ε(x) - qDpJp(x) = qµp p(x)ε(x) - qDpdp(x)
dx
Eg
ElectronMass
ValenceBand
ConductionBand
HoleMass
ε
High Performance Processor@ 90nm
256 million transistors37nm gate lengthPNO gate: 10 nm EOTNiSi2/Poly gate8 levels Cu with low-k interlevel dielectric
0
20
40
60
80
100
2004 2006 2008 2010 2012 2014 2015
Heading for Change
Gate Length
(nm)
Heading for Change
Gate Length
(nm)
0
20
40
60
80
100
2004 2006 2008 2010 2012 2014 2015
ChallengesChallenges• Push CMOS as far as we can (to "end
of roadmap")• Invent next generation electronics
• Push CMOS as far as we can (to "end of roadmap")
• Invent next generation electronics
Lithography
Year of Production
Resolution (µm)
Lithography will not ultimately limit IC feature size!
32
1.51
0.4 0.350.25
0.180.13
0.090.065
0.045
0.50.6
0.01
0.1
1
10
1980 1990 2000 2010
AboveWavelength
NearWavelength
BelowWavelength
g-lineλ = 436nm i-line
λ = 365nm
DUVλ = 248nm 193
λ = 193nm 157λ = 157nm
0.032λ = EUV 13.5 nm
i-193λ‘ = 133nm
AgendaIntroduction to CMOS VLSI TechnologyPhysics Challenges to Continued VLSI Scaling– Gate insulator– Gate electrode– Carrier scattering– Quantum behavior of carriers in the
presence of stress– Non-equilibrium Boltzmann transport – Tunneling– Discrete positioning of dopant atoms– Electrostatics– Simulation
Conclusion
Introduction to CMOS VLSI TechnologyPhysics Challenges to Continued VLSI Scaling– Gate insulator– Gate electrode– Carrier scattering– Quantum behavior of carriers in the
presence of stress– Non-equilibrium Boltzmann transport – Tunneling– Discrete positioning of dopant atoms– Electrostatics– Simulation
Conclusion
Voltage Reduction Achieved by• Reduction in tox ≈ 10A in 2004• Increase in εox using Plasma
Nitrided Oxide (PNO)
Gate Insulator
Delay ~
Power ≈ 1/2 CV2Fc
CVIdrive
Inversion LayerChargeQinv ≈ Dox = εoxEox
≈ εoxVdd
tox
Gate Leakage Current
0.00001
0.0001
0.001
0.01
0.1
1
10
100
1000
5 10 15 20 25 30Equivalent Oxide Thickness (A)
nMO
S G
ate
Cur
rent
(A/c
m2) SiON
SiO2
Supply Voltage (Vdd)
1980 1990 2000
1 V
5 V
Clock Frequency (MHz)
1980 1990 2000
10
100
1,000
10,000
Gate InsulatorBad News
Dielectic Constant
Bre
akdo
wn
Stre
ngth
(MV/
cm)
TiO2 (k=60-95)
0.1
1
10
100
1 10 100 1000
SiO2 (k=3.9)
HfO2 (k=21), ZrO2 (k=29)
Si3N4 (k=7.5), Al2O3 (k=9)
Ta2O5 (k=19-26), La2O3 (k=27), Pr2O3 (k=31)
SrTiO3 (k=50-200)
Hi-k also degrades channel mobility
Good News
EOT (nm)0.5 1.0 1.5 2.0 2.5
10-6
10-5
10-4
10-3
10-2
10-1
100
102
103
HfSiO/TI SiSC'02HfSiON/TI HfSiON/Toshiba VLSI '03HfSiON/Toshiba IWGI '03SiO2 trendlineSiONNovel SiON/Toshiba VLSI '04
101
HfSiO/TI SiSC'02HfSiON/TI HfSiON/Toshiba VLSI '03HfSiON/Toshiba IWGI '03SiO2 trendlineSiONNovel SiON/Toshiba VLSI '04
Gat
e Le
akag
e
Work Function (eV)
Hf
Zr In
Ta
Cd AgAlNb VZn
SnCr WMo
RuTiOsRe
Rh
Ir
Pt
3.0
3.5
4.0
4.5
5.0
5.5
6.0
La
Metal Gate
Mid-Gap
Optimum for NMOS
Optimum for PMOS
Valence Band
Conduction Band
5.20
4.63
4.05
38A Oxide
10 nm
Ti Gate
Si
Electrons in Si
Modern CMOSVertical Field E ≈ 1.2 MV/cmStark Quantization results in
∆E ≈ 75 meV∆Vt ≈ 50 mV
Modern CMOSVertical Field E ≈ 1.2 MV/cmStark Quantization results in
∆E ≈ 75 meV∆Vt ≈ 50 mV
Stark Effect
E7
E2E1E0
∆2E21
E11
E01
E31
∆E=∆E10-∆E0
∆4
∆4
∆2
[001]
[010]
[100]
Effect of Strain
Bi-axial tensile strain of 1.3 GPa results in
∆Estrain ≈ 135 meVMobility increase ≈ 80%
Idrive increase ≈ 20%
Bi-axial tensile strain of 1.3 GPa results in
∆Estrain ≈ 135 meVMobility increase ≈ 80%
Idrive increase ≈ 20%
E7
E2E1E0
∆2
E21
E11
E01
E31
210 meV
∆4
Holes in [110] Uniaxially Compressed Si
Si
kx
ky
| px,py>
Unstrained Heavy Hole (HH)Unstrained Heavy Hole (HH)
[110]
kx
ky
Strained Heavy Hole (HHS)Strained Heavy Hole (HHS)
LH,HHHHS
LHS
| s,px,py ,pz>
Mobility ImprovesMobility Degrades
Discrete Channel Dopants Introduce IOFF Fluctuationsand IOFF Degradation
W =
40nm EC
Current Density Off-Current
Filament
IDS
VGS
DiscreteAverage
ContinuumChannel Doping
L = 20nm
5X
DiscreteDoping
Discrete Channel Dopants
Myth of the MOSFET Switch
Log
I off
VG
Vt
φs
In the Off State
ID ~ e
In the Off State
ID ~ e -q φskT
∆ log ID∆ VG
qkT
= Cox + CP
Coxlog10e
∂ φs∂VG
Sub-Threshold Slope 60 - 100 mV/decade
For Vt = 300mV 5 - 3 decades
Ion ≈ 1 mA/um
Ioff ≈ 10 nA/um - 1 uA/um
Sub-Threshold Slope 60 - 100 mV/decade
For Vt = 300mV 5 - 3 decades
Ion ≈ 1 mA/um
Ioff ≈ 10 nA/um - 1 uA/um
ElectrostaticsCritical Scaling ParametersL Wtox xjun xdep
Multi-Gate FETs show promise of extending scaling for several generations beyond planar CMOS
tox and xdep are encountering scaling limits. This results in ...
– Degraded sub-threshold slope– Increased drain induced
barrier lowering (DIBL)
kTq
Cox + CP
Cox
ConclusionScaling CMOS to the “End of Roadmap” will require sophisticated condensed matter physics.– Gate stack: Atomic and electron orbital understanding of
this complex material system– Quantum behavior of carriers
• High perpendicular E field• Stress
– Non-equilibrium Boltzmann transport– Tunneling: Gate insulator and Drain-to-Substrate– Simulation
Sophisticated condensed matter physics will also be required to invent and develop electronics beyond CMOS– Single Electron Transistor (SET)– Carbon Nano-tube (CNT)– Molecular Electronics– Spintronics– Quantum Computing
Scaling CMOS to the “End of Roadmap” will require sophisticated condensed matter physics.– Gate stack: Atomic and electron orbital understanding of
this complex material system– Quantum behavior of carriers
• High perpendicular E field• Stress
– Non-equilibrium Boltzmann transport– Tunneling: Gate insulator and Drain-to-Substrate– Simulation
Sophisticated condensed matter physics will also be required to invent and develop electronics beyond CMOS– Single Electron Transistor (SET)– Carbon Nano-tube (CNT)– Molecular Electronics– Spintronics– Quantum Computing