advanced rf and analog integrated circuits for fourth...

International Journal of Microwave Science and Technology

Advanced RF and Analog Integrated Circuits for Fourth Generation Wireless Communications and Beyond Guest Editors Ramesh Pokharel Leonid Belostotski Akira Tsuchiya Ahmed Allam and Mohammad S Hashmi

Advanced RF and Analog IntegratedCircuits for Fourth Generation WirelessCommunications and Beyond



Guest Editors Ramesh Pokharel Leonid BelostotskiAkira Tsuchiya Ahmed Allam and Mohammad S Hashmi

Copyright copy 2013 Hindawi Publishing Corporation All rights reserved

This is a special issue published in ldquoInternational Journal of Microwave Science and Technologyrdquo All articles are open access articlesdistributed under the Creative Commons Attribution License which permits unrestricted use distribution and reproduction in anymedium provided the original work is properly cited

Editorial Board

Iltcho M Angelov SwedenHerve Aubert FranceGiancarlo Bartolucci ItalyTanmay Basak IndiaEric Bergeault FrancePazhoor V Bijumon CanadaFabrizio Bonani ItalyMattia Borgarino ItalyMaurizio Bozzi ItalyNuno Borges Carvalho PortugalRobert H Caverly USAYinchao Chen USAWen-Shan Chen TaiwanCarlos E Christoffersen CanadaPaolo Colantonio ItalyCarlos Collado SpainAli Mohamed Darwish EgyptAfshin Daryoush USAWalter De Raedt BelgiumDidier J Decoster FranceQianqian Fang USAFabio Filicori ItalyManuel Freire SpainEdward Gebara USAGiovanni Ghione ItalyRamon Gonzalo SpainGian Luigi Gragnani ItalyYong Xin Guo SingaporeMridula Gupta IndiaWenlong He UK

Tzyy-Sheng Horng TaiwanYasushi Itoh JapanKenji Itoh JapanYong-Woong Jang KoreaHideki Kamitsuna JapanNemai Karmakar AustraliaDmitry Kholodnyak RussiaErik L Kollberg SwedenIgor A Kossyi RussiaSlawomir Koziel IcelandMiguel Laso SpainChang-Ho Lee USAErnesto Limiti ItalyFujiang Lin SingaporeYo Shen Lin TaiwanAlayn Loayssa SpainGiampiero Lovat ItalyBruno Maffei UKGianfranco F Manes ItalyJan-Erik Mueller GermanyKrishna Naishadham USAKenjiro Nishikawa JapanJuan M OrsquoCallaghan SpainAbbas Sayed Omar GermanyBeatriz Ortega SpainSergio Pacheco USAMassimiliano Pieraccini ItalySheila Prasad USAXianming Qing SingaporeRudiger Quay Germany

Mirco Raffetto ItalyAntonio Raffo ItalyMurilo A Romero BrazilLuca Roselli ItalyArye Rosen USAAnders Rydberg SwedenSafieddin Safavi-Naeini CanadaSalvador Sales Maicas SpainAlberto Santarelli ItalyJonathan B Scott New ZealandAlmudena Suarez SpainRiccardo Tascone ItalySmail Tedjini FranceIchihiko Toyoda JapanSamir Trabelsi USAChih Ming Tsai TaiwanGiorgio Vannini ItalyBorja Vidal SpainNakita Vodjdani FranceJan Vrba Czech RepublicHuei Wang TaiwanChien-Jen Wang TaiwanJean Pierre Wigneron FranceYong-Zhong Xiong SingaporeYansheng Xu CanadaM C E Yagoub CanadaKamya Yekeh Yazdandoost JapanNing Hua Zhu ChinaHerbert Zirath Sweden

Contents

Advanced RF and Analog Integrated Circuits for Fourth Generation Wireless Communications andBeyond Ramesh Pokharel Leonid Belostotski Akira Tsuchiya Ahmed Allam and Mohammad S HashmiVolume 2013 Article ID 272070 2 pages

Performance and Trends in Millimetre-Wave CMOS Oscillators for Emerging Wireless ApplicationsMarius Voicu Domenico Pepe and Domenico ZitoVolume 2013 Article ID 312618 6 pages

A Novel Reconfigurable MB-OFDM UWB LNA Using Programmable Current Reuse Ahmed RaghebGhazal Fahmy Iman Ashour and Abdel Hady AmmarVolume 2013 Article ID 924161 5 pages

Systematic Design Methodology of a Wideband Multibit Continuous-Time Delta-Sigma ModulatorAwinash Anand Nischal Koirala Ramesh K Pokharel Haruichi Kanaya and Keiji YoshidaVolume 2013 Article ID 275289 5 pages

An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90 nm CMOSSang-yeop Lee Hiroyuki Ito Shuhei Amakawa Noboru Ishihara and Kazuya MasuVolume 2013 Article ID 584341 11 pages

Hindawi Publishing CorporationInternational Journal of Microwave Science and TechnologyVolume 2013 Article ID 272070 2 pageshttpdxdoiorg1011552013272070

EditorialAdvanced RF and Analog Integrated Circuits for FourthGeneration Wireless Communications and Beyond

Ramesh Pokharel1 Leonid Belostotski2 Akira Tsuchiya3

Ahmed Allam4 and Mohammad S Hashmi5

1 Faculty of Information Science and Electrical Engineering Kyushu University Fukuoka 819-0395 Japan2Department of Electrical and Computer Engineering University of Calgary Calgary AB Canada T2N 1N43Department of Communications andComputer Engineering Graduate School of Informatics KyotoUniversity Kyoto 606-8501 Japan4Department of Electronics and Communication Engineering Egypt-Japan University of Science and TechnologyAlexandria 21934 Egypt

5 IIIT Delhi New Delhi 110020 India

Correspondence should be addressed to Ramesh Pokharel pokhareledkyushu-uacjp

Received 3 May 2013 Accepted 3 May 2013

Copyright copy 2013 Ramesh Pokharel et al This is an open access article distributed under the Creative Commons AttributionLicense which permits unrestricted use distribution and reproduction in any medium provided the original work is properlycited

Fourth generation wireless communications are approachingtomarket and recent innovations are at peak to come upwithRF and analog circuit solutions to provide low power andhigh speed tiny chips at very low cost This special issuepresents the researches and technical know-how suitable forcritical advanced researches in ICs development After rigor-ous review of numerous research and review articles this spe-cial issue finalizes one review article and three research arti-cles which address the recent developments in IC design andare suitable for publication in this peer journal

Oscillators are one of the most critical components oftransceiver and designing low phase noise oscillators oper-ating at several GHz is a challenging task To help researchersunderstand the design implementation and its performancewith different topologies and architectures the recent advan-ces in CMOS VCOs are discussed Recently innovations inCMOS oscillators have extended to higher end of millimeter-wave region maintaining their performance comparable tomicrowave oscillators

Present and future communication systems demand thatelectronic devices be suitable for a range of applications withdifferent bandwidth speed and accuracy This necessitatesthe need for reconfigurable devices and to cover this flavorinnovation in reconfigurable LNA for UWB receivers hasbeen addressed This LNA exploits the programmable circuitto control the mode of operation and with current reuse

improves the gain and flatnessThe designed LNA operates intwo subbands ofMB-OFDMUWBUWBmode-1 andmode-3 as a single or concurrent mode

Miniaturization is the key for CMOS technology andbulky inductors are the main hindrance Therefore circuittopology without a bulky inductor is highly desired and pro-moted Inductorless PLL with subharmonic pulse injectionlocking has been introduced A half-integral subharmoniclocking technique helped to improve phase noise characteris-tics

Although recent developments and scaling of CMOStechnology are pushing the signal processing into digitaldomain the hard truth is that the real world is analog andtherefore analog-to-digital converter is an integral part ofchip design Delta-sigma modulator is gaining more andmore attention and popularity because of its potential toachieve high resolution and high speed Continuous-timedelta-sigmamodulator helps to design low power modulatorand hence a systematic design methodology to design suchmodulator is presented

Acknowledgments

Wehope our readers can enrich their knowledge through ourvariety of papers and we would like to thank all our editors

2 International Journal of Microwave Science and Technology

reviewers and technical staffs who are directly or indirectlyinvolved in making this special issue concisely informativeand successful

Ramesh PokharelLeonid Belostotski

Akira TsuchiyaAhmed Allam

Mohammad S Hashmi


Research ArticleCMOS Ultra-Wideband Low Noise Amplifier Design

K Yousef1 H Jia2 R Pokharel3 A Allam1 M Ragab1 H Kanaya3 and K Yoshida3

1 Electronics and Communications Engineering Department Egypt-Japan University of Science and TechnologyNew Borg Al-Arab 21934 Alexandria Egypt

2 E-JUST Center Kyushu University Nishi-ku Fukuoka 819-0395 Japan3 Graduate School of ISSE Kyushu University Nishi-ku Fukuoka 819-0395 Japan

Correspondence should be addressed to K Yousef khalilyousefejustedueg

Received 29 November 2012 Accepted 26 March 2013

Academic Editor Mohammad S Hashmi

Copyright copy 2013 K Yousef et alThis is an open access article distributed under the Creative CommonsAttribution License whichpermits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

This paper presents the design of ultra-wideband low noise amplifier (UWB LNA) The proposed UWB LNA whose bandwidthextends from 25GHz to 16GHz is designed using a symmetric 3D RF integrated inductorThis UWB LNA has a gain of 11 plusmn 10 dBand aNF less than 33 dBGood input and output impedancematching and good isolation are achieved over the operating frequencybandThe proposed UWB LNA is driven from a 18 V supplyThe UWB LNA is designed and simulated in standard TSMC 018 120583mCMOS technology process

1 Introduction

CMOS technology is one of the most prevailing technologiesused for the implementation of radio frequency integratedcircuits (RFICs) due to its reduced cost and its compat-ibility with silicon-based system on chip [1] The use ofultra-wideband (UWB) frequency range (31ndash106GHz) forcommercial applications was approved in February 2002by the Federal Communications Commission Low costreduced power consumption and transmission of data athigh rates are the advantages of UWB technology UWBtechnology has many applications such as wireless sensorand personal area networks ground penetrating radars andmedical applications [2]

Low noise amplifier is considered the backbone of theUWB front-end RF receiver It is responsible for signalreception and amplification over the UWB frequency rangeLNA has many desired design specifications such as low andflat noise figure high and flat power gain good input andoutput wide impedancematching high reverse isolation andreduced DC power consumption [1 3]

Nowadays one of the most suitable configurationssuggested for LNA implementation is current reuse cascaded

amplifier This LNA configuration can attain low DC powerconsumption high flattened gain minimized NF and excel-lent reverse isolation while achieving wide input and outputimpedance matching [1ndash3]

Radio frequency integrated inductors play a significantrole in radio frequency integrated circuits (RFICs) imple-mentation Design development and performance improve-ment of RF integrated inductors represent a challengingwork Achieving high integration level and costminimizationof RFICs are obstructed because of the difficulties facingthe RF integrated inductors designers which are related toobtaining high quality factors [4ndash6]

In this paper the implementation of LNAs using 3Dintegrated inductors will be investigated A symmetric 3Dstructure is proposed as a new structure of integrated induc-tors for RFICs

This paper discusses the design procedure of currentreuse cascaded UWB LNA and its bandwidth expansionIn addition the employment of suggested symmetric 3DRF integrated inductor will be demonstrated This paperis organized as follows Section 2 introduces the suggestedUWB LNA circuit Section 3 gives simulation results anddiscussion Conclusion is driven in Section 4


2 Circuit Description

As shown in Figure 1 the proposed UWB LNA is a currentreuse cascaded core based on a common source topologywitha shunt resistive feedback technique implemented over theinput stage

This current reuse cascaded amplifier achieved goodwideband input impedance matching through the use ofsource degeneration input matching technique Figure 2shows the small signal equivalent circuit of this LNA inputstage The input port of this UWB LNA is desired tomatch source impedance 119877

119904at resonance frequency 120596

119900 This

matching circuit bandwidth is defined through the qualityfactors of source degeneration and gain-peaking inductors(119871119904and 119871

119892) where the input impedance is given by

119885in = 119895120596 (119871 119904 + 119871119892) +1

119895120596119862gs+ 120596119879119871119904

= 119895120596 (119871119904+ 119871119892) +

1

119895120596119862gs+ 119877119904

(1)

where 119885in is the UWB LNA input impedance and 120596119879is the

current-gain cut-off frequency where 120596119879= 119892119898119862gs and 119892119898

and119862gs are the input stage transconductance and gate-sourcecapacitance respectively 119881

119904represents the RF signal source

119877119904is the output impedance of 119881

119904

Although the shunt resistive feedback loop leads toLNA noise performance degradation [7] it is widely usedin recently proposed LNAs due to its superior widebandcharacteristics Shunt capacitive-resistive feedback techniqueis employed to widen the input-matching bandwidth andincrease the LNA stability

Shunt-peaked amplifiers are known to have wide gainbandwidth and high low frequency power gain [8] To havea high flattened gain of the proposed UWB LNA shunt-peaking technique is used In addition the gate-peaking tech-nique is used to enhance the LNA gain at high frequenciesBesides the shunt- and gate-peaking techniques the shuntresistive feedback loop is used in gain flattening [2 8] TheLNA approximate gain is given by

119860 cong

119881out119881119904

cong

11989211989811198921198982[119877119871 (1198771198892+ 1198781198711198892)] [119878119871

1198891]

2 sdot 119878119862gs1 [119878 (119871 1199041 + 1198711198921) + 1119878119862gs1]

(2)

Ultra-wideband applications require good noise perfor-mance in addition to high and flat gain Low noise designtechniques which are suitable for narrowband applicationscannot be used for wideband applicationsMain contributionof cascaded matched stages noise figure is due to first stage[9]The reduction of noise figure of input stagewill lead to thereduction of the overall noise figure of the proposed designOptimization and control of factors affecting the NF willimprove this UWB LNA noise performance An equivalentcircuit of the input stage for noise factor calculation is shownin Figure 3 [1]

An estimated value of the noise figure (NF = 10 log10119891)

of this topology is given in [1] where 119891 is the noise factor ofthe UWB LNAThe noise factor 119891 can be given by

119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+

12057512057212059621198622

gs1119877119904

51198921198981

+

119877FB ((1198711198921 + 119871 1199041) 119862gs1)2

119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900rfbn

119876rfbn) + 120596

2

119900rfbn

10038161003816100381610038161003816100381610038161003816

2

+

1205741198921198981(119877FB + 119877119904)

2((1198711198921+ 1198711199041) 119862gs1)

2

120572119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900dn

119876dn) + 120596

2

119900dn

10038161003816100381610038161003816100381610038161003816

2

(3)

119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+ 119891gn + 119891rfbn + 119891dn (4)

where

120596119900rfbn = radic

1 + 1198921198981119877119904

(1198711198921+ 1198711199041) 119862gs1

119876rfbn =1

119877119904+ 12059611987911198711199041

sdot radic

(1 + 1198921198981119877119904) (1198711198921+ 1198711199041)

119862gs1

120596119900rfbn = radic

1

(1198711198921+ 1198711199041) 119862gs1

119876dn =1

(119877119904|| 119877FB) + 1205961198791119871 1199041

sdot radic

(1198711198921+ 1198711199041)

119862gs1

(5)

where119891gn119891dn and119891rfbn are gate drain and feedback resistornoise factors respectively and 120572 120575 and 120574 are constants equalto 085 41 and 221 respectively

It is clear from (4) that to reduce the noise figure highquality factors of 119871

1199041and 119871

1198921are desired It can also be noted

that the noise factor is inversely proportional to feedbackresistor119877

119891 In otherwords weak feedback topology decreases

the noise factor value while strong feedback implementationdegrades the noise performance of the suggested UWB LNA

In addition the noise factor formula given by (4) statesthat the noise figure is also inversely proportional to thetransconductance of the input stage (119892

1198981) This goes along

with the known fact that noise performance trades off withpower consumption

For output matching the series resonance of the shuntpeaking technique is used to match the proposed UWB LNAto the load impedance119877

119871while the series drain resistance119877

1198892

is used to extend the output matching bandwidthThis proposedUWBLNA (LNA1) has an operating band-

width of 31ndash106GHzThe proposed LNA2 whose schematic

International Journal of Microwave Science and Technology 3

1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

119881out1198722

1198721

1198771198892

119877119871

Figure 1 Current reuse UWB LNA (LNA1)

119871119904

119871119892

119885in

119877119904

119881119904

119903119900119862 119892119898119881gs gs

Figure 2 Input stage small signal equivalent circuit

119877

1198942

1198902119904

119877119878

1198711198661 119877 1198902 1198902

1198942119892 119862 1119881 1

119877119904

1198902

1198711199041

119877

1198902

1198921198981119881 1 1198942119889 1198942119899out

119877

+

minus

FB

rfb

119892 rg

gs

rs

ls

lg lg

gs

ls

gs

Figure 3 Equivalent circuit of the fisrt stage for noise calculation[1]

1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

1198623

1198711199043

1198771198893119862out

119871out

119877out

119881out

1198722

1198721

1198723

1198811198663

Figure 4 Schematic circuit of LNA2

Metal 6

Port 2(Metal 6)

Metal 2

Port 1(Metal 6)

Metal 4

Figure 5 3D view of the symmetric 3D proposed structure

25 35 45 55 65 75 85 95 105 115Frequency (GHz)

200

180

160

140

120

100

80

60

40

20

00

Gai

n an

d N

F (d

B)

GainNoise figure

Figure 6 11987821(dB) and NF (dB) of LNA1


20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

150

100

50

0

minus50

minus100

Gai

n (d

B)

LNA2 (planar Ind)LNA2 (3D Ind)

Figure 7 11987821(dB) of LNA2

20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

60

50

40

30

20

10

00

Noi

se fi

gure

(dB)


119878-parameter response

Figure 8 NF (dB) of LNA2

circuit is shown in Figure 4 is an extended version of LNA1 Ithas a wider operating band of frequency which extends from25GHz to 16GHz

Input impedance match has a special importance andconsideration especially in wideband sensitive circuitsdesign Input impedance matching bandwidth is broadenedby the use of a weaker shunt capacitive-resistive feedbackloop which mainly leads to quality factor reduction of theinput matching circuit Weakness of shunt feedback strengthnot only reduces the input reflection coefficient over thiswide bandwidth but it also reduces the input side injectedthermal noise which decreases the proposed LNA2 noise

25 35 45 55 65 75 85 95 105 115Frequency (GHz)

0

minus50

minus100

minus150

minus200

minus250

minus300

minus350

Refle

ctio

n co

effici

ents

(dB)

11987811

11987822

Figure 9 11987811(dB) and 119878

22(dB) of LNA1

20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175


119878 11

(dB)


figure indicating the enhanced noise performance of thesuggested design

Shunt-peaking technique increases the low frequencygain and hence decreases the gain flatnesswhile having awideoperating bandwidth In spite of shunt-peaking drawbacks itmainly facilitates LNA output impedance to load matchingLNA2 bandwidth extension and gain flatness over its operat-ing band of frequency are achieved through the removal ofshunt peaking Moreover the control of gate peaking is usedto enhance the current reuse amplifier core gain

For wideband output impedance matching a unity com-mon gate (CG) matching topology in addition to series


20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175

minus200


119878 22

(dB)


resonance circuit consisting of capacitor 119862out and inductor119871out is used to match the LNA2 output impedance to its load(succeeding RF stage) The resistive termination 119877out is usedto control the load-output impedance match bandwidth

A planar RF on-chip spiral inductor (1198711198891) having an

inductance of 145 nH and a maximum quality factor of 80 isneeded as a load of the input CS stage to improve the currentreuse stages matching This RF integrated inductor occupiesan area of 428 120583m times 425 120583m which represents a considerablepart of the UWB LNA total die area

One of the well-known difficulties facing the develop-ment of RFICs is inductors large area relative to other passiveand active components This area problem becomes moresevere with the recent intensive shrinking of active devicesand competitive reduction of fabrication cost [10]

Inductors quality factor (119876) reduction is another limitingfactor of RFICs performance enhancement The reduction ofinductor119876 factor is due to ohmic and substrate losses Ohmiclosses can be decreased by using a high conductive metalfor inductor implementation On the other hand placing ahigh resistive layer underneath the inductor can minimizethe substrate losses Lately optimized 3D structures andimplementations of RF integrated inductors are suggestedto overcome all of these limitations and improve the RFintegrated inductors performance [4 5]

For LNA2 circuit area reduction and RF inductor char-acteristics improvement a symmetric 3D structure for RFintegrated inductor implementation is suggested to replacethe planar RF integrated inductor (119871

1198891) Similar to the design

of planar RF inductor 3D metallic structure layout shouldbe drawn on a substrate to design and test a 3D integratedinductor [11] 3D RF inductors structures are mainly consist-ing of serially connected different metal layers spirals havingthe same current flowdirectionThis 3D structure inductance

is dependent on these different spirals inductances and thepositive mutual coupling they have [11]

For 1P6M CMOS technology which has six differentmetal layers the proposed symmetric 3D RF integratedinductor has a complete spiral inductor on the highest metallayer (1198726) Half of the lower spiral is implemented usingfourth metal layer (1198724) to increase its inductance value dueto the increased mutual coupling The second metal layer(1198722)which is distant from the topmetal layer is employed toimplement the lower spiral other half to reduce the parasiticcomponents of that 3D metal structure and increase itsquality factor The suggested symmetric 3D inductor has aninductance of 145 nH a quality factor of 85 and an areaof 185 120583m times 165 120583m 80 of planar inductor area is savedthrough this symmetric 3D structure while achieving thesame inductance value and higher quality factor Figure 5shows a 3D view of the proposed symmetric RF integratedinductor

3 Simulation Results and Discussion

The proposed UWB LNA (LNA1 and LNA2) circuits aredesigned in TSMC CMOS 018 120583m technology process usingAgilent Advanced Design System (ADS) Electromagneticsimulation is verified by the post-layout simulation resultswhich are obtained using the Cadence design environmentThe suggested symmetric 3D structure is designed and testedusing Momentum simulation software and verified usingCadence design environment The LNAs simulation resultsare given below

31 Power Gain and Noise Figure LNA1 has a gain of 17 plusmn15 dB as shown in Figure 6 It also has a noise figure less than23 dB over its operating band of frequency (31ndash106GHz)11987821(dB) of LNA2 is higher than 10 dB with a maximum

value of 12 dB over the desired band of frequency (25ndash16GHz) This high and flat gain is due to the use of inductivegain-peaking technique in addition to the control of the unitygain current cut-off frequencies of LNA2 Figure 7 showsthat the proposed LNA2 employing the symmetric 3D RFintegrated inductor achieves a gain of 11 plusmn 10 dB

The proposed UWB LNA2 has an enhanced LNA noiseperformance LNA2 NF ranges from 25 dB to 33 dB overthe operating bandwidth (25ndash16GHz) This NF reduction isaccomplished due to the optimization of the LNAnoise factorgiven by (4) and the use of weak shunt capacitive-resistivefeedback implemented over the input stage LNA2 achievesa NF less than 33 dB over the operating band of frequency asshown in Figure 8

32 Input and Output Impedance Matching LNA1 input andoutput ports have good matching conditions to its sourceand load respectively Simulation results of input and outputreflection coefficients of LNA1 are shown in Figure 9 LNA1has 11987811and 11987822less than minus11 dB and minus10 dB respectively over

the UWB range of frequenciesThe proposed UWB LNA2 achieves good input im-

pedance matching as shown in Figure 10 Good impedance


Table 1 Proposed UWB LNA performance summery in compari-son to recently published UWB LNAs

Reference BW(GHz)

Gain(dB)

NF(dB)

11987811

(dB)11987822

(dB)This work (LNA2)lowast 25sim16 11 plusmn 10 lt33 ltminus7 ltminus725This work (LNA1)lowast 31sim106 17 plusmn 15 lt23 ltminus11 ltminus10LNA-1 [1] 17sim59 112 plusmn 23 lt47 ltminus118 ltminus127LNA-2 [1] 15sim117 122 plusmn 06 lt48 ltminus86 ltminus10[2] 3sim106 15 lt44 ltminus7 NA[12] 31sim106 108 plusmn 17 lt6 ltminus10 ltminus93[13] 1sim5 127 plusmn 02 lt35 ltminus8 NAlowastPost-layout simulation results

match between LNA2 and its source is obtained using theseries-resonant input matching technique The input returnloss (119878

11) is less thanminus70 dB over this wide range of frequency

(25ndash16GHz)Figure 11 shows that better output impedance matching is

obtained using the planar integrated inductor while simulat-ing LNA2 Good output impedance matching of LNA2 overits operating band of frequency (25ndash16GHz) is accomplisheddue to the optimization of the CG outputmatching stage withthe aid of the output LC resonant circuit 119877out termination isused to widen the matching bandwidth The output returnloss (119878

22) shown in Figure 11 is less than minus725 dB for LNA2

using the planar inductor while it is less than minus60 dB forLNA2 employing the proposed 3D inductor over the desiredfrequency band (25ndash16GHz)

33 DC Power Reverse Isolation and Stability LNA1 andLNA2 consume DC power of 128mW and 20mW respec-tively froma 18Vpower sourceThe increasedDCconsump-tion of LNA2 is due to having enough driving bias for the CGoutput match stage

Both of the proposed UWB LNA1 and LNA2 have areverse isolation factor (119878

12) less thanminus28 dBover each design

bandwidthThe proposed UWB LNAs (LNA1 and LNA2) areunconditionally stable over their bandwidths

Table 1 shows a summary of the proposed UWB LNAsperformance in comparison to other recently publishedUWBLNAs implemented in 018120583m CMOS technology

4 Conclusion

In this paper two different UWBLNAswere presented LNA1has high gain minimized noise figure and good impedancematch over the UWB range of frequencies LNA2 has awide range of operating frequency (25 GHzndash16GHz) UWBLNA2 consists of a current reuse cascaded amplifier withshunt resistive feedback followed by a CG output stage withresistive termination LNA2 input stage use series-resonantimpedancematching technique and employs a symmetric 3DRF integrated inductor as a load The post-layout simulationresults of LNA1 and LNA2 demonstrate the performanceimprovement achieved through theses designs The next step

is to implement these UWB LNAs to have a comparisonbetween post-layout simulation results andmeasured results

References

[1] Y S Lin C Z Chen H Y Yang et al ldquoAnalysis and designof a CMOS UWB LNA with dual-RLC-branch wideband inputmatching networkrdquo IEEE Transactions on Microwave Theoryand Techniques vol 58 no 2 pp 287ndash296 2010

[2] A I A Galal R K Pokharel H Kanay and K Yoshida ldquoUltra-wideband low noise amplifier with shunt resistive feedbackin 018 120583m CMOS processrdquo in Proceedings of the 10th TopicalMeeting on Silicon Monolithic Integrated Circuits in RF Systems(SiRF rsquo10) pp 33ndash36 January 2010

[3] K Yousef H Jia R Pokharel A Allam M Ragab and KYoshida ldquoA 2ndash16GHz CMOS current reuse cascaded ultra-wideband low noise amplifierrdquo in Proceedings of the Saudi Inter-national Electronics Communications and Photonics Conference(SIECPC rsquo11) April 2011

[4] K Yousef H Jia R Pokharel A Allam M Ragab andK Yoshida ldquoDesign of 3D Integrated Inductors for RFICsrdquoin Proceeding of 2012 Japan Egypt Conference on ElectronicsCommunications and Computers (JECECC rsquo12) pp 22ndash25

[5] X N Wang X L Zhao Y Zhou X H Dai and B C CaildquoFabrication and performance of novel RF spiral inductors onsiliconrdquo Microelectronics Journal vol 36 no 8 pp 737ndash7402005

[6] A M Niknejad and R G Meyer ldquoAnalysis design andoptimization of spiral inductors and transformers for Si RFICrsquosrdquo IEEE Journal of Solid-State Circuits vol 33 no 10 pp1470ndash1481 1998

[7] T H Lee The Design of CMOS Radio-Frequency IntegratedCircuits Cambridge University Press 2nd edition 2004

[8] S S Mohan M Del Mar Hershenson S P Boyd and T HLee ldquoBandwidth extension in CMOS with optimized on-chipinductorsrdquo IEEE Journal of Solid-State Circuits vol 35 no 3 pp346ndash355 2000

[9] H T Friis ldquoNoise figure of radio receiversrdquo Proceedings of theIRE vol 32 no 7 pp 419ndash422 1944

[10] H Y Tsui and J Lau ldquoExperimental results and die area efficientself-shielded on-chip vertical solenoid inductors for multi-GHzCMOS RFICrdquo in Proceedings of the IEEE Radio FrequencyIntegrated Circuits (RFIC) Symposium pp 243ndash246 June 2003

[11] H Garcia S Khemchndai R Puildo A Lturri and J Pino ldquoAWideband active feedback LNA with a Modified 3D inductorrdquoMicrowave andOptical Technology Letters vol 52 pp 1561ndash15672010

[12] P Sun Sh Liao H Lin Ch Yang and Y Hsiao ldquoDesign of 31 to106 GHz ultra-wideband low noise amplifier with current reusetechniques and low power consumptionrdquo in Proceedings of theProgress In Electromagnetics Research Symposium pp 901ndash905Beijing China March 2009

[13] A I A Galal R K Pokharel H Kanaya and K Yoshidaldquo1-5GHz wideband low noise amplifier using active inductorrdquoin 2010 IEEE International Conference on Ultra-WidebandICUWB2010 pp 193ndash196 chn September 2010


Review ArticlePerformance and Trends in Millimetre-Wave CMOS Oscillatorsfor Emerging Wireless Applications

Marius Voicu12 Domenico Pepe1 and Domenico Zito12

1 Tyndall National Institute Lee Maltings Dyke Parade Cork Ireland2Department of Electrical and Electronic Engineering University College Cork Cork Ireland

Correspondence should be addressed to Domenico Zito domenicozitotyndallie

Received 14 December 2012 Accepted 19 February 2013

Academic Editor Ramesh Pokharel

Copyright copy 2013 Marius Voicu et al This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

This paper reports the latest advances on millimeter-wave CMOS voltage-controlled oscillators (VCOs) Current state-of-the-artimplementations are reviewed and their performances are compared in terms of phase noise and figure of merit Low power andlow phase noise LC-VCO and ring oscillator designs are analyzed and discussed Design and performance trends over the lastdecade are provided and discussedThe paper shows how for the higher range of millimeter-waves (gt60GHz) the performances ofring oscillators become comparable with those of LC-VCOs

1 Introduction

In the last few years several standards have been or have beenplanned to soon be released regarding millimetre-waves(mm-waves ie 30ndash300GHz) systems for emerging wirelessapplications Some of the most attractive applications are60GHz unlicensed wireless data communication [1] 77-GHzautomotive radars [2] and 94GHz passive imaging [3] Keyenabler for high-volume and low-cost mass market imple-mentation of these systems is the significant improvementof device performance in the latest CMOS technology nodes(ie 130 nm and smaller) which offer a great potential forthe realization of millimeter-waves wireless transceivers ona single chip

One of the most important building blocks in a wirelesstransceiver is the frequency synthesizer Performance of thevoltage controlled oscillator (VCO) dictates the performanceof the frequency synthesizer and thus of the whole commu-nication system

The aim of the present paper is to provide a review ofthe state-of-the-art (SoA) ofmillimeter-wave (mm-wave 30ndash300GHz) VCOs in CMOS technology in order to identifythe trends over the last decade and derive some usefulobservations regarding the past and possible future evolutionof design and performance In particular the paper reports

a comparison of performances among SoA design solutionsand highlights the achievements and trends in terms of phasenoise (PN) and figure of merit (FOM)

The present paper is organized as follows Section 2 pro-vides an overviewof twoof themostwidespreadVCO topolo-gies LC-tank and ring oscillators and recalls briefly theirmain causes responsible for the phase noise In Section 3 SoAmillimeter-wave CMOS LC-VCO and ring oscillator designsolutions are reported and their performances are discussedand compared In Section 4 the conclusions are drawn

2 CMOS VCOs

The most widespread CMOS VCO topologies at mm-wavefrequencies are LC-tank and ring oscillators Section 21provides a brief overview of LC-VCOs and their PN contri-butions Section 31 provides a brief review of ring oscillatorsand their PN contributions

21 LC-Tank VCOs LC-VCOs consist of a resonant circuit(LC-tank) and an amplifier that provides adequate gain tocompensate the losses of the resonant circuit The amplifiercan be a single transistor in one of the known configurations(common-source common-gate or source follower) or thewidespread cross-coupled differential pair (see Figure 1(a))


Outminus

119881DD

Out+

(a) (b)

Figure 1 (a) LC-VCO (b) ring oscillator

The main causes of PN in LC-VCO are due to the lossesin the resonator and the amplifier noise For instance in thecase of cross-coupled differential pair LC-VCOs they are (i)resonator thermal noise (due to the loss conductance in theresonator) (ii) tail current noise (the switching action of thedifferential pair translates noise up and down in frequencyand so the noise enters the resonator) and (ii) differential pairnoise (due to the finite switching time of the pair) [4]

22 Ring Oscillators Ring oscillators (ROs) are composed ofa cascade of inverting amplifiers and the output of the lastelement is fed back to the input of the first (see Figure 1(b))These inverter stages can be implemented by differentialamplifiers CMOS inverters or even LC-VCOs

The main causes of PN in ring oscillators are (i) the ther-mal noise (due to MOSFET drain-source channel resistanceand load resistors) and (ii) flicker noise (in CMOS inverter-based ROs the pull-up and pull-down currents containflicker noise which varies slowly overmany transitions whilein differential ROs the flicker noise in the tail currentmodulates the propagation delay of the stages) [5]

3 State-of-the-Art of mm-Wave CMOS VCOs

In this Section a review of SoA mm-wave CMOS LC-VCOand RO design solutions is provided and their performancesare discussed and compared In Section 31 three SoA mm-waves CMOS LC-VCO implementations operating at 3060 and 140GHz respectively are reported In Section 32two SoA mm-wave RO designs (the first implemented at 50and 60GHz the second at 104 and 121 GHz) are reportedIn Section 33 performance trends over the last decade of

119876minus119881119866119881119866119868+ 119868minus 119876+

119881DD 119881DD

Figure 2 Schematic of the VCO presented in [6] The two trifilartransformers of 119868 and 119876 VCOs are highlighted in red and blueSpirals couplings are represented by the thin arrowed lines 119868 and119876 are VCO outputs

mm-wave CMOS LC-VCOs and ROs are provided and dis-cussed The performances of the SoA VCOs are summarizedin Tables 1 and 2 and their figure of merit ((FOM) see (1)) areevaluated

FOM = 119875119873 minus 20Log(1198910

Δ119891

) + 10Log(119875DC1mW) (1)

where 1198910is the oscillation frequency Δ119891 is the offset at which

the 119875119873 is evaluated and 119875119862is the power consumption

31 SoAmm-Wave CMOS LC-VCOs In [6] a 30GHz quadra-ture VCO (QVCO) implemented in 013 120583m CMOS technol-ogy is presented The circuit schematic is shown in Figure 2It exploits the use of a trifilar (1 1 1) transformer with ahigh quality factor (ie with respect to spiral inductors)


Table 1 SoA mm-wave CMOS LC-VCOs summary of performance

Reference Tech (nm) 1198910(GHz) 119881DD (V) 119875

119862(mW) Phase noise (dBcHz) FOM (dBcHz)

[6] 130 303 06 78 minus114 1MHz minus196[7] 90 576 06 72 minus102 1MHz minus188[9] 90 1398 12 96 minus75 1MHz minus178

Table 2 SoA mm-wave CMOS ROs summary of performance



[10] 130 503 08 35 minus104 1MHz minus1864[10] 130 585 08 34 minus95 1MHz minus1806[11] 130 104 15 28 minus933 1MHz minus180[11] 130 121 13 21 minus88 1MHz minus1765

119881119866

Buffer BufferOutminus119881119862

Tank 1

Tank 2

119881DD

Out+

Figure 3 Schematic of the 60GHz Colpitts LC-VCO presented in[7]

in order to improve the PN performance In fact withrespect to inductors transformers can provide higher qualityfactors due to the mutual coupling between the spiralsThe trifilar transformer couples two series cascaded cross-coupled VCO structures The transformer couples in-phaseand in-quadrature drain and source spirals allowing for areduction of device noise parasitic capacitances and powerconsumption The PN is minus114 dBcHz 1MHz from thecarrier frequency of 303GHz The power consumptionamounts to 78mW from a 06V supply voltage

In [7] a 60GHz Colpitts LC-VCO implemented in 90 nmCMOS technology is presented The circuit schematic isshown in Figure 3 Although Colpitts oscillators have goodPN performances they suffer from the Miller capacitanceeffects which cause an increase in the parasitic gate-draincapacitance of the MOSFET transistors This issue is solvedby combining a conventional Colpitts oscillator and a tuned-input tuned-output (TITO) oscillator [8] In this way start-upissues of the Colpitts oscillator have been solved and phasenoise performance improved (thanks to an extra LC-tank fornoise filtering) The circuit consumes 72mW from a 06Vsupply voltage The PN is minus102 dBcHz 1MHz offset fromthe carrier (576GHz)The tuning range is 53 GHz (from 558to 611 GHz)

In [9] a 140GHz cross-coupled LC-VCO implementedin 90 nm CMOS technology by UMC is presented The

OutminusOut+

119881DD

119881Bias

119881Tune

119881DD buffer 119881DD buffer

Figure 4 Schematic of the 140-GHz LC-VCO presented in [9]

circuit schematic is shown in Figure 4 A low parasitic cross-coupled transistor layout is developed in order to achievea high fundamental frequency The VCO core has beenbiased through a p-MOSFET in order to reduce the flickernoise contribution to the overall close-in PN Moreover tominimize the load capacitance connected to the LC-tank atwo-stage tapered buffer has been used to drive the 50Ω loadThe VCO core consumes 96mW from a 12 V voltage supplyThe buffers consume 72mWThe PN amounts to minus75 dBcHz 1MHz offset from the carrier frequency of 1398GHz

Table 1 summarizes the main characteristics and perfor-mances of the aforementioned LC-VCOs

32 SoA mm-Wave CMOS Ring Oscillators In [10] 50GHzand 60GHz ring oscillators implemented in 013120583m CMOSare presentedThe block diagram is shown in Figure 5(a) Aninterpolative-phase-tuning (IPT) technique is used to tunefrequency of multiphase mm-wave LC-based ROs withoutusing varactors (see Figure 5(b)) In order to vary the outputfrequency the delay of each stage of the ROs is variedby means of tunable phase shifters A fixed phase shift isused to introduce a delayed current 119894

1via 119872

3and 119872

4

1198941is interpolated with the undelayed current provided by1198721and 119872

2 The phase shift can be tuned from 0 to 120573 by

controlling the biasing dc current 1198680and 119868

1 Two output


119881DD 119881DD 119881DD

119866119898119866119898 119866119898middot middot middot

(a)

1198721 11987221198723 1198724120573

11986801198681

119881119873minus1minus

119881119873minus1+

119881119873minus 119881119873+

(b)

Figure 5 (a) Block diagram of the 50 and 60GHz ring oscillators presented in [10] (b) Schematic of Gm block of Figure 4(a) 120573 is a fixedphase shifter implemented by a LC-based differential stage

Buffer

Out

119881DD

Figure 6 Schematic of the 104 and 121 GHz ring oscillators pre-sented in [11]

current-controlled oscillators (CCOs) with 4 and 8 phasesare implemented using this techniqueThe 8-phase CCO canbe tuned from 486 to 52GHz and it consumes from 32 to48mW from a 08V voltage supply The 4-phase CCO canbe tuned from 56 to 613 GHz and consumes from 30 to37mWThe PN of the 8-phase CCO amounts to minus104 dBcHzat 1MHz offset from the carrier (503) The PN of the 4-phase CCO is minus95 dBcHz 1MHz offset from the carrier(585GHz)

In [11] two fundamental three-stage ROs implementedin a 013 120583m CMOS process and oscillating at 104GHz and121 GHz respectively are presented The circuit schematic isshown in Figure 6 A new design methodology for designinghigh-frequency oscillators has been developed This methodfinds the best topology to achieve frequencies close to the

20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010

Figure 7 Oscillator phase noise performances versus oscillationfrequency [6 7 9ndash11 13ndash20]

maximum frequency of oscillation of the transistors It isbased on the activity condition of the transistors A device iscalled active at a certain frequency if it can generate powerin the form of a single sinusoidal signal at that frequency[12] This method determines also the maximum frequencyof oscillation for a fixed circuit topology Each stage ofthe implemented ROs is implemented using a double gatetransistor with a substrate contact ring around the transistorand an inductive load The measured peak output powers ofthe two oscillators are minus35 dBm and minus27 dBm at 121 GHzand 104GHz respectively The DC power consumptionsincluding the output buffer is 21mW from a 128V supplyand 28mW from a 148V supply for the 121 GHz and 104GHzoscillators respectively The PN at 1MHz offset frequency isminus88 dBcHz and minus933 dBcHz for the 121 GHz and 104GHzoscillators respectively

The main figures of merit and performances of theaforementioned ring oscillators are presented in Table 2

33 Performance Trends in mm-Wave CMOS VCOs PNversus oscillation frequency of SoA mm-wave CMOS LC-VCOs and ROs published in the last 11 years are shown in


2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010

Figure 8 Oscillator phase noise performances versus publicationyear [6 7 9ndash11 13ndash20]

20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010

Figure 9 Oscillator FOM versus oscillation frequency [6 7 9ndash1113ndash24]

Figure 7 It can be observed that PN performances of ringoscillators are becoming closer to those of LC-VCOs whilemoving towards very high frequencies

Figure 8 shows PN versus publication year It can benoted that in the last couple of years while in the lowmm-wave range (30GHz) the PN of LC-VCOs is still better(minus114 dBcHz 1MHz offset from 30GHz [6]) at very highfrequencies PN of RO becomes comparable to that of LC-VCOs achieving a PNofminus88 dBcHz 1MHz at 121 GHz [11]

The FOM achieved by the state-of-the-art mm-waveCMOS LC-VCOs and ROs published in the last 11 years areshown in Figure 9 Also in this case as in Figure 7 relative toPN it can be noted that in the lower part of the mm-waverange (below 60GHz) LC-VCOs attain overall better FOM

minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010

Figure 10 Oscillator FOM versus publication year [6 7 9ndash11 13ndash24]

than ROs but for very high frequencies FOM of ROs becamecomparable to that of LC-VCOs

Figure 10 shows FOM versus publication year It can benoted that the trend in the last couple of years is that theFOM of LC-VCOs is still superior but it is achieved for lowerfrequencies [6 7] than theROs in [10 11] In fact the solutionsin [10 11] achieve FOM comparable to those of previousimplementations of LC-VCOs at lower frequencies

4 Conclusions

A review of the state-of-the-art of millimeter-wave CMOSVCOs has been presented State-of-the-art LC-VCOs andring oscillators have been presented and discussed and theirperformances have been compared The trends for VCOdesign and performance over the last decade have been tracedand discussed

From these evaluations it appears that while movingin the higher part of the mm-wave spectrum (gt60GHz)phase noise and FOM performance of ring oscillators tend tobecome closer and even comparable to those of LC-VCOswhich are dominant at lower frequencies Thus ring oscilla-tors appear to be a strong candidate for the implementation ofCMOS VCOs operating at the higher region of the mm-wavefrequency spectrum

References

[1] D Pepe and D Zito ldquoSystem-level simulations investigatingthe system-on-chip implementation of 60-GHz transceivers forwireless uncompressed HD videordquo in Applications of MATLABin Science and Engineering pp 181ndash196 InTech Publisher 2011

[2] M Schneider ldquoAutomotive radarmdashstatus and trendsrdquo in Pro-ceedings of the German Microwave Conference (GeMiC rsquo05)Ulm Germany April 2005

[3] L O Mereni D Pepe F Alimenti and D Zito ldquoFeasibility andchallenges of a 95-GHz SoC radiometer for W-band passive


imagingrdquo in Proceedings of the IET Irish Signals and SystemsConference pp 28ndash29 Maynooth Ireland June 2012

[4] J J Rael and A A Abidi ldquoPhysical processes of phase noise indifferential LC oscillatorsrdquo in Proceedings of the 22nd AnnualCustom Integrated Circuits Conference (CICC rsquo00) pp 569ndash572May 2000

[5] A A Abidi ldquoPhase noise and jitter in CMOS ring oscillatorsrdquoIEEE Journal of Solid-State Circuits vol 41 no 8 pp 1803ndash18162006

[6] J S Syu H L Lu and C Meng ldquoA 06V 30GHz CMOSquadrature VCO using microwave 1 1 1 trifilar transformerrdquoIEEE Microwave and Wireless Components Letters vol 22 no2 2012

[7] L Li P Reynaert and M Steyaert ldquoA colpitts LC VCO withMiller-capacitance gm enhancing and phase noise reductiontechniquesrdquo in Proceedings of the 37th European Solid-State Cir-cuits Conference (ESSCIRC rsquo11) pp 491ndash494 Helsinki Finland

[8] S Shekhar J S Walling S Aniruddhan and D J AllstotldquoCMOS VCO and LNA using tuned-input tuned-output cir-cuitsrdquo IEEE Journal of Solid-State Circuits vol 43 no 5 pp 1177ndash1186 2008

[9] C Cao E Seok and K O Kenneth ldquoMillimeter-wave CMOSvoltage-controlled oscillatorsrdquo in Proceedings of the IEEE Radioand Wireless Symposium (RWS rsquo07) pp 185ndash188 Long BeachCalif USA January 2007

[10] S Rong and H C Luong ldquoDesign and analysis of varactor-lessinterpolative-phase-tuningmillimeter-wave LC oscillators withmultiphase outputsrdquo IEEE Journal of Solid-State Circuits vol 46no 8 pp 1810ndash1819 2011

[11] OMomeni and E Afshari ldquoHigh power terahertz andmillime-ter-wave oscillator design a systematic approachrdquo IEEE Journalof Solid-State Circuits vol 46 no 3 pp 583ndash597 2011

[12] R Spence Linear Active Networks Wiley-Interscience NewYork NY USA 1970

[13] J O Plouchart J Kim N Zamdmer et al ldquoA 31GHz CMLring VCO with 54 ps delay in a 012-spl mum SOI CMOStechnology rdquo inProceedings of the 29th European Solid-State Cir-cuits Conference (ESSCIRC rsquo03) pp 357ndash3360 Estoril PortugalSeptember 2003

[14] A P Van der Wel S L J Gierkink R C Frye V Boccuzzi andB Nauta ldquoA robust 43-GHzVCO inCMOS forOC-768 SONETapplicationsrdquo IEEE Journal of Solid-State Circuits vol 39 no 7pp 1159ndash1163 2004

[15] HMWang ldquoA 50GHzVCO in 025 120583mCMOSrdquo inProceedingsof the IEEE International Solid-State Circuits Conference (ISSCCrsquo01) pp 372ndash3373 San Francisco Calif USA February 2001

[16] H-K Chen H J Chen D C Chang Y Z Juang and SS Lu ldquoA 06V 432mW 68GHz low phase-noise VCO withintrinsic-tuned technique in 013120583m CMOSrdquo IEEE Microwaveand Wireless Components Letters vol 18 no 7 pp 467ndash4692008

[17] D Huang W Hant N Y Wang et al ldquoA 60GHz CMOS VCOusing on-chip resonator with embedded artificial dielectricfor size loss and noise reductionrdquo in Proceedings of the IEEEInternational Solid-State Circuits Conference (ISSCC rsquo06) pp1218ndash1227 San Francisco Calif USA February 2006

[18] L Li P Raynaert and M Steyaert ldquoA low power mm-waveoscillator using power matching techniquesrdquo in Proceedings ofthe IEEE Radio Frequency Integrated Circuits Symposium (RFICrsquo09) pp 469ndash472 Boston Mass USA 2009

[19] C Cao and O K Kenneth ldquoA 90-GHz voltage-controlledoscillator with a 22-GHz tuning range in a 130-nm CMOStechnologyrdquo in Proceedings of the Symposium on VLSI Circuitspp 242ndash2243 Kyoto Japan June 2005

[20] C C Chen C C Li Bo-Jr Huang K Y Lin H W Tsao andH Wang ldquoRing-based triple-push VCO with wide continoustuning rangesrdquo IEEE Transactions on Microwave Theory andTechniques vol 57 no 9 pp 2173ndash2183 2009

[21] P C Huang R C Liu H Y Chang et al ldquoA 131-GHz push-push VCO in 90-nm CMOS technologyrdquo in Proceedings of theIEEE Radio Frequency Integrated Circuits (RFIC rsquo05) pp 613ndash616 June 2005

[22] P-C Huang M D Tsai G D Vendelin H Wang C H Chenand C S Chang ldquoA low-power 114-GHz push-push CMOSVCOusing LC source degenerationrdquo IEEE Journal of Solid-StateCircuits vol 42 no 6 pp 1230ndash1239 2007

[23] C W Tsou C C Chen and Y S Lin ldquoA 57-GHz CMOSVCO with 1853 tuning-range enhancement using tunableLC source-degenerationrdquo in Proceedings of the InternationalSymposium on VLSI Design Automation and Test (VLSI-DATrsquo09) pp 146ndash149 Hsinchu Taiwan 2009

[24] Z-M Tsai C-S Lin C F Huang J G J Chern and H WangldquoA fundamental 90-GHz CMOS VCO using new ring-coupledquadrdquo IEEEMicrowave andWireless Components Letters vol 17no 3 pp 226ndash228 2007


Research ArticleA Novel Reconfigurable MB-OFDM UWB LNA UsingProgrammable Current Reuse

Ahmed Ragheb1 Ghazal Fahmy1 Iman Ashour1 and Abdel Hady Ammar2

1 Electronics Department National Telecommunication Institute (NTI) Cairo 11768 Egypt2 Electrical Department Al Azhar University Cairo Egypt

Correspondence should be addressed to Ahmed Ragheb ahmedraghebntiscieg



Copyright copy 2013 Ahmed Ragheb et alThis is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

This paper presents a design of a reconfigurable low noise amplifier (LNA) for multiband orthogonal frequency divisionmultiplexing (MB-OFDM) ultra wideband (UWB) receivers The proposed design is divided into three stages the first one is acommon gate (CG) topology to provide the input matching over a widebandThe second stage is a programmable circuit to controlthe mode of operation The third stage is a current reuse topology to improve the gain flatness and consume lower power Theproposed LNA is designed using 018120583m CMOS technology This LNA has been designed to operate in two subbands of MB-OFDMUWB UWBmode-1 and mode-3 as a single or concurrent modeThe simulation results exhibit the power gain up to 173518 and 11 dB for mode-1 mode-3 and concurrent mode respectively The NF is 35 39 and 65 and the input return loss is betterthan minus12 minus1357 and minus11 dB over mode-1 mode-3 and concurrent mode respectively This design consumes 4mW supplied from12 V

1 Introduction

Ultra wideband (UWB) has many advantages over nar-rowband technology such as high data rate low powerlow complexity and low cost technology When The USFederal Communication Commission (FCC) recognized thepotential advantages of UWB it issued a report that allowsUWB use for commercial communication systems in 2002and its applications can operate in the unlicensed spectrumof31ndash106GHz [1] UWB supports carrierless baseband signalssuch as impulse-radio IR-UWB and it supports widebandwith carrier such asmultiband orthogonal frequency divisionmultiplexing MB-OFDM UWB [2] In MB-OFDM UWBsystems the spectrum from 31 to 106GHz is divided into 14subbands of 528MHz as shown in Figure 1 which supportsdata rates from 53 to 480Mbps [3 4]

In order to roam across different subbands devices thatsupport multinetwork applications are required There is astrong motivation on using single chip supports multibandand multiapplications due to it provides wireless access forusers anywhere and anytime In such reconfigurable devicesthe design of low noise amplifier (LNA) is a critical issue

because its has effects in the overall system and requirementsas high gain low noise figure (NF) and lower power con-sumption with good input and output matching over eachband of interest

Recently there are some schemes proposed to themultistandard LNAs like parallel concurrent widebandand reconfigurable LNA The first approach is the parallelarchitecture that emploies multiple architectures for eachband of interest [5] However this approach requires largearea different design for each band and more time Theconcurrent and wideband approaches provide multibandsimultaneously [6] by providing the input matching but thisapproaches pass the large interference the matching networktherefore increasing the linearity is required [7 8] Recentlythe reconfigurable approach presents to discrete band andorconcurrent bands [7] to solve the tradeoff between areapower and cost Many approaches present a continuoustuning like [8 9] it is good for narrowband applications butit is not applicable for widebands

This paper proposed a new reconfigurable MB-OFDMLNA forUWB systemsThe proposed LNA reconfigured overdual widebands and it works as a discrete band or concurrent


Band group 1 Band group 2 Band group 3 Band group 4 Band group 5

Band 1 Band 2 Band 3 Band 4 Band 5 Band 6 Band 7 Band 8 Band 9 Band 10 Band 11 Band 13 Band 14Band 12

3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891

Figure 1 Frequency spectrum of MB-OFDM UWB system

119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922

Figure 2 Current reuse architecture

based on the programmable part This design based on CGtopology to provide the input matching over wideband [1011] current reuse technique shown in Figure 2 used to providehigh and flat gain and low power consumption [12ndash14]and programmable circuit to select the band of operationThis paper is organized as follows the demonstration ofthe proposed circuit defect and solution of current reusetechnique will be presented in Section 2 Section 3 discussesthe simulation results of the proposed LNA Finally theconclusion is presented in Section 4

2 Circuit Design of the ProposedReconfigurable MB-OFDM UWB LNA

The proposed LNA was designed by a standard 018 120583mCMOS process Figure 3(a) shows the schematic of the LNAThis circuit consists of three stages distinguished by threedifferent blocks in Figure 3(a) The first one input matchingstage in block-1 in Figure 3(a) the CG topology used tocontrol the input matching over wideband [11 15] wherethe input impedance at 119871

119878resonated with the gate-to-source

parasitic capacitance of 1198621198921199041

of 1198721is 119885in = 11198921198981 where

1198921198981

is the transconductance of transistor1198721 Therefore the

matching bandwidth can be calculated by

119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)

Table 1 Look-up table of programmable circuit

11987211987811198721198782

BW (GHz) 1198910(GHz) Mode

0 0 mdash mdash mdash0 1 0528 3432 Single1 0 0528 4488 Single1 1 asymp14 396 Concurrent

hence by controlling 1198921198981

the input impedance can bematched to 50Ω at resonance

Second stage is the programmable switches in block-2in Figure 3(a) actually this stage is proposed to achieve twomain tasks The first task is used to select the branch thatwill provide the desired band consequently the selected banddepends on Table 1 where 119891

0is the center frequency of the

selected mode The other task is used to solve current reusedefect without using this stage the control of this circuit canbe made by transistor119872

2119886and119872

2119887 but when one of them

is OFF 1198991and 119899

2nodes will be shorted thereby the overall

circuit performance will be effectedTo solve this problem the programmable circuit is pro-

posed when transistor1198721198782is OFF as shown in Figure 3(b) 119899

1

and 1198992nodes will be disconnected

Finally the current reuse stage in block-3 in Figure 3(a)is used to achieve high and flat gain and lower powerconsumption This architecture was simplified in Figure 2and it consists of series inductor 119871

1and shunt capacitor

1198621connected to DC cascode transistors 119872

1and 119872

2 1198621is

used to resonate with gate-to-source parasitic capacitanceof 1198722 1198621198921199042

while 1198711is selected large in the desired band-

width to provide high impedance path to block RF signalFurthermore when the capacitance 119862

119900is selected large the

transistors 1198721and 119872

2act as two common source (CS)

cascaded stage at high frequency [12ndash14]

3 Simulation Results

Design of the proposed reconfigurable MB-OFDM UWBLNA was carried out using Spectre simulator from CadenceDesign Suite The proposed circuit consumes 332mA from12 V supply when it works in single mode but when it worksin concurrent mode it consumes 339mA The simulationresults for S-parameters andNF are illustrated in Figure 4 andFigure 5

Figure 4(a) shows the simulated input return loss 11987811

for different frequency bands based on Table 1 As noticed


1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)

Figure 3 Circuit design of the proposed reconfigurable MB-OFDMUWB LNA (a) schematic of proposed reconfigurable MB-OFDMUWBLNA and (b) operation of the proposed LNA when119872

1198781ON and119872

1198782OFF

11987811

is less than minus12 minus1357 and minus11 dB for UWB mode-1with center frequency 3432GHz UWB mode-3 with centerfrequency 4488GHz and concurrent mode with centerfrequency 396GHz respectively These results depict theinput matching network of the proposed LNA under minus10 dBthe reason behind this due to CG topology and selection ofappropriate value of 119871119904 to resonate with119862

1198921199041 so the proposed

design has a good input matchingFigure 4(b) presents the reverse isolation 119878

12between

output and input ports over bands of interest where it isless than minus505 minus442 and minus52 dB for mode-1 mode-3and concurrent mode respectively Also the better isolationcomes from CG topology where the input isolated from theoutput of this topology

Figure 4(c) illustrates the voltage gain 11987821of the proposed

LNA As depicted the proposed LNA achieves 1735 18 and 11dB for mode-1 mode-3 and concurrent mode respectivelyThe high gain of this LNA is due to current reuse wherethe overall transconductance of this design is 119892

119898= 11989211989811198921198982

However the gain of concurrent mode is lower than singlemode due to the parallel resistance of branches (outputresistance of 119872

2119886 1199031199002119886

series with output resistance of 1198721198781

and 1199031199001198781

are parallel with output resistance of 1198722119887 1199031199002119887

series with output resistance of 1198721198782 and 119903

1199001198782) Figure 4(d)

shows the output return loss 11987822

of the reconfigurable LNAwhere it is under minus149 minus96 and minus142 dB for all modes

The good output matching was achieved due to the selectionof appropriate values for output matching network (119872

2 1198711198922

1198711198892 119871out 119862out and 119862119900) The simulated NF versus bands of

interest is shown in Figure 5 As noticed NF of the proposedLNA achieves 349ndash353 39ndash393 and 629ndash68 dB for mode-1 mode-3 and concurrent mode respectively The high NFof concurrent mode is due to the number of transistors thatare used in this mode

The performance of the proposed LNA and a comparisonwith existing architectures are summarized in Table 2 Asshown in this table the proposed LNA provides discretetuning and concurrent while the existing techniques eitherprovide discrete concurrent or continuous tuning Thevoltage gain 119878

21for the proposed architecture is lower than

[8 9 16] because they use the cascode and cascade topologiesfor that they consume higher power when compared with theproposed reconfigurable LNA

4 Conclusion

A reconfigurable LNA for MB-OFDM UWB receivers isproposedThis LNAworks in threemodes of operation basedon programmable current reuse technique The detailedoperation of the proposed reconfigurable LNA includinginput matching topology (CG) programmable switches cir-cuit high gain and low power technique (current reuse)


3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)

Figure 4 S-Parameter results of reconfigurable LNA over multibands (a) input reflection coefficient 11987811 (b) reverse isolation 119878

12 (c) voltage

gain 11987821 and (d) output reflection coefficient 119878

22

Table 2 The performance of the proposed LNA and comparison with existing architecture

Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878

21(dB) NF (dB) Power (mW) Topology

[7] 01328 33 46

12ltminus18 mdash 142ndash16 17ndash37

64Slowast

205 565 ltminus86 mdash 149 4ndash48 Clowastlowast

43ndash108 mdash 3ndash156 4ndash53 UWB[8] 013 19ndash24 12 ltminus13 mdash 14ndash10 32ndash37 17 Conlowastlowastlowast

[9]013 34ndash36 12 ltminus18 ltminus153 209ndash213 lt18 16 S

42ndash48 12 ltminus15 ltminus145 192ndash207 lt23[15] 018 09 15 24 18 ltminus10 mdash 15ndash19 19ndash45 30 C[16] 013 18ndash24 12 ltminus12 mdash 26ndash28 32ndash34 96

This work 0183168ndash3696

12ltminus1204 ltminus149 158ndash1735 349ndash353

4S

4224ndash4752 ltminus1357 ltminus96 16ndash18 39ndash393 S3432ndash4488 ltminus11 ltminus142 1025ndash11 628ndash68 C

lowastS Single mode lowastlowastC Concurrent mode lowastlowastlowastCon continuous


3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

Figure 5 Noise figure NF

and the noise performance of this circuit was presentedThe proposed LNA operates by 12 V supply and consumes332mA for single mode (UWB mode-1 or mode-3) and339mA for concurrent mode Finally it has been designedby 018 120583m CMOS process

References

[1] Federal Communications Commission (FCC) ldquoFirst Reportand Order inThe Matter of Revision of Part 15 of the Commis-sionrsquos Rules Regarding Ultra wideband Transmission SystemsrdquoET-Docket 98-153 FCC 02-48 2002

[2] M Di Benedetto T Kaiser A F Molisch I OppermannC Politano and D Porcino UWB Communication Systems aComprehensive Overview Hindawi Publishing Co 2006

[3] C Vennila G Lakshminarayanan and S Tungala ldquoDesignof reconfigurable UWB transmitter to implement multi-rateMB-OFDM UWB wireless systemrdquo in Proceedings of theInternational Conference on Advances in Computing Controland Telecommunication Technologies (ACT rsquo09) pp 411ndash413December 2009

[4] T Gao F Zhou W Li N Li and J Ren ldquoA 62ndash95 GHzUWB receiver for WiMedia MB-OFDMrdquo in Proceedings of the10th IEEE International Conference on Solid-State and IntegratedCircuit Technology pp 782ndash784 November 2010

[5] M A T Sanduleanu and M Vidojkovic ldquoRF transceiverconcepts for reconfigurable and multi-standard radiordquo in Pro-ceedings of the 1st European Wireless Technology Conference(EuWiT rsquo08) pp 29ndash32 October 2008

[6] S Datta A Dutta K Datta and T K Bhattacharyya ldquoPseudoconcurrent quad-band LNAoperating in 900MHz18 GHz and900MHz24GHz bands for multi-standard wireless receiverrdquoin Proceedings of the 24th International Conference on VLSIDesign pp 124ndash129 January 2011

[7] X Yu and N M Neihart ldquoA 2ndash11 GHz reconfigurable multi-mode LNA in 013 120583mCMOSrdquo in Proceedings of the IEEE Radio

Frequency Integrated Circuits Symposium pp 475ndash478 IEEE2012

[8] M El-Nozahi E Sanchez-Sinencio and K Entesari ldquoA CMOSlow-noise amplifier with reconfigurable input matching net-workrdquo IEEE Transactions on MicrowaveTheory and Techniquesvol 57 no 5 pp 1054ndash1062 2009

[9] Y Wang F Huang and T Li ldquoAnalysis and design of afully integrated IMTmdashadvancedUWB dual-band LNArdquo inProceedings of the International Symposium on Signals Systemsand Electronics (ISSSE rsquo10) vol 1 pp 83ndash86 September 2010

[10] J F Chang and Y S Lin ldquo099mW 3ndash10GHz common-gateCMOS UWB LNA using T-match input network and self-bodybias techniquerdquo Electronics Letters vol 47 no 11 pp 658ndash659 2011

[11] J F Chang and Y S Lin ldquoA 276mW 310GHz ultra-widebandLNA using 018120583m CMOS technologyrdquo in Proceedings of theInternational Symposium on VLSI Design Automation and Test(VLSI-DAT rsquo11) pp 188ndash191 April 2011

[12] A N Ragheb G A Fahmy I Ashour and A Ammar ldquoA 31ndash106GHz low power high gain UWB LNA Using current reusetechniquerdquo in Proceedings of the 4th International Conference onIntelligent and Advanced Systems (ICIAS rsquo12) vol 2 pp 741ndash7442012

[13] QWan and CWang ldquoA design of 31ndash106GHz ultra-widebandCMOS low noise amplifier with current-reused techniquerdquoInternational Journal of Electronics and Communication vol 65no 12 2011

[14] C P Liang P Z Rao T J Huang and S J Chung ldquoAnalysisand design of two low-power ultra-wideband CMOS low-noise amplifiers with out-band rejectionrdquo IEEE Transactions onMicrowave Theory and Techniques vol 58 no 2 pp 277ndash2862010

[15] Z Liu and J Wang ldquoA 018 120583m CMOS reconfigurable multi-band multi-gain low noise amplifierrdquo in Proceedings of theInternational Conference on Electric Information and ControlEngineering (ICEICE rsquo11) pp 961ndash964 April 2011

[16] A Slimane M T Belaroussi F Haddad S Bourdel and HBarthelemy ldquoA reconfigurable inductor-less CMOS low noiseamplifier for multi-standard applicationsrdquo in Proceedings of theIEEE 10th International Conference on New Circuits and SystemsConference (NEWCAS rsquo12) pp 57ndash60 2012


Research ArticleSystematic Design Methodology of a Wideband MultibitContinuous-Time Delta-Sigma Modulator

Awinash Anand1 Nischal Koirala1 Ramesh K Pokharel2

Haruichi Kanaya1 and Keiji Yoshida1

1 Graduate School of Information Science and Electrical Engineering Kyushu University 744 Motooka Fukuoka 819-0315 Japan2 E-JUST Center Kyushu University 744 Motooka Fukuoka 819-0315 Japan

Correspondence should be addressed to Awinash Anand awinashanandgmailcom

Received 14 November 2012 Accepted 5 February 2013

Academic Editor Ahmed Allam

Copyright copy 2013 Awinash Anand et al This is an open access article distributed under the Creative Commons AttributionLicense which permits unrestricted use distribution and reproduction in any medium provided the original work is properlycited

Systematic design of a low power wideband and multi-bit continuous-time delta-sigma modulator (CTDSM) is presented Thedesign methodology is illustrated with a 640MSs 20MHz signal bandwidth 4th order 2-bit CTDMS implemented in 018 120583mCMOS technologyThe implemented design achieves a peak SNDR of 657 dB and a high dynamic range of 70 dB while consumingonly 197mW from 18V supply The design achieves a FoM of 031 pJconv Direct path compensation is employed for oneclock excess loop delay compensation In the feedforward topology capacitive summation using the last opamp eliminates extrasummation opamp

1 Introduction

Delta-sigma modulators embed low-resolution analog-to-digital converter in a feedback loop The use of feedbackand high oversampling pushes the quantization noise out ofthe band of interest and thereby provides a high in-bandresolution Delta-sigma modulator is well suitable for a high-resolution data conversion because a moderate accuracy ofpassive components is required Recently continuous-timedelta-sigma modulator has brought tremendous attentionbecause of its exceptional features such as inherent antialias-ing filter (AAF) relaxed gain-bandwidth requirement onactive elements resulting in a low-power consumption com-pared to its counterpart discrete-time delta-sigmamodulator[1 2] Low-power consumption is the key for a CTDSM

In [3] the design methodology for a multibit modulatorwith two-step quantizer is presented However the optimiza-tion of the peak SNR and the maximum stable amplitudeis not taken into consideration Also excess loop delaycompensation is for more than one clock where to achievehigher resolution higher bit quantizer should be used These

all increase the design methodology complexity and are notsimple to adopt for designers To keep the design simpleand the insight intact we implement one-step quantizer withexcess loop delay compensation for one clock In [4] theoptimal design methodology of a higher-order continuous-timewideband delta-sigmamodulator is presentedHoweverthis methodology requires summation amplifier and henceconsumes higher power In our approach the summationamplifier is eliminated by using capacitive summation withlast integratorrsquos amplifier and this makes design simpler andsaves significant power Also in [4] SNR and phase marginare optimized which could be replaced to simpler way tooptimize the peak SNR and the maximum stable amplitudewhich are more obvious parameters

Recent development in wireless communication standarddemands a wideband and high-resolution data convertersTo achieve a high SNR over a wideband a higher clockrate that is a higher oversampling ratio (OSR) is desiredHowever OSR is limited by the clock rate due to technologylimitations and power consumption Fortunately the SNR


SpecificationsBW SNDR DR

Choice of topology andarchitecture

Order OSR quantizerbits OBG

NTF synthesis

Coefficients generation Circuit simulation andresult verification

Macromodel simulationto predict peak SNR

Determining circuitparameters

Coefficients scaling

Figure 1 Flow chart of the design methodology

degradation due to lower OSR can be compensated by amulti-bit quantizer

We present a systematic methodology to design a wide-band and high-resolution modulator at low power cost Toillustrate the methodology we aim to design a continuous-time delta-sigma modulator which has signal bandwidth of20MHz and requires 10-11-bit resolution suitable for WLANSection 2 discusses the high-level synthesis In Section 3we present simple circuit implementation of the modulatorSection 4 presents the results and discussion and finallySection 5 concludes the paper

2 High-Level Synthesis

In this section we describe the design methodology inaccordance with the flow chart in Figure 1 to synthesize ahigh-level wideband multi-bit continuous-time delta-sigmamodulator in MATLAB to meet the specification for WLAN

21 Choice of Topology and Architecture A single-loop topol-ogy is preferred to a MASH topology to reduce the circuitcomplexity To implement the loop filter a feedforward (FF)topology is preferred to a feedback (FB) A FF topology hasseveral advantages over a FB topology Firstly FF uses onlyone feedback DAC (without any compensation for excessloop delay (ELD)) in the main loop which results in smallersilicon area and better matching of coefficients Howeverin the case of FB multiple DACs equal to the order ofthe modulator are needed which increase the chip area andmismatch is a major concern [5] Secondly the integratingresistor in both the FF and the FB topologies is determinedby the noise and distortion requirement However in a FFtopology the second and further resistors can bemade largerIn a FF topology the first opamp is the fastest while in a FBtopology the first opamp is the slowest Thus the capacitorsize can be reduced in the second and higher integratorswith increased resistor value which significantly reduces thesilicon area [6] Also the necessity for scaling and also therequirements on integrator dynamics are much more relaxedwhich results in increase in power efficiency of FF topology

compared to that of FB topology [1] However in general FFtopology requires extra summation amplifier which could beeliminated by implementing capacitive as shown in Figure 4and explained in Section 23 [7] Thus a single-loop FF DSMis the most suitable choice for a high dynamic range and alow-power design

22 Noise Transfer Function (NTF) Synthesis Noise trans-fer function synthesis is critical for delta-sigma modulatordesign as it guides the overall performance and the stabilityof modulator Before NTF can be synthesized order of themodulator oversampling ratio quantizerrsquos bit and out-of-band gain must be determined

221 Oversampling Ratio (OSR) Among all these oversam-pling is the most important driving factor as it is directed bythe technology node and power consumption In principleincreasing OSR by 2 times results in a 15 dB improvementin SNR However OSR or clock rate is limited by CMOStechnology and the power consumption To design a wide-bandmodulator with 20MHz signal bandwidth anOSR of 16results in a clock rate (119891

119904) of 640MSswhich is high enough to

design analog circuits in 018 um CMOS technologyThus weneed to design a comparator which can perform comparisonat 640MSs and opamp which can have GBW higher than640MHz for integration to support sampling at 640MSsSince these are pretty high-performance components welimit the oversampling ratio to 16

222 Modulatorrsquos Order Higher-order modulator improvesthe SNR however it increases the circuit complexity anddeteriorates the stability Since we target a wide-signal bandof 20MHz a higher-order modulator is essential and there-fore we simulate the modulator for third fourth and fifthorder From simulation we find that a good choice of themodulator order is 4 for a wide bandwidth (20MHz) andideally produces a SNDR of 70 dB which is approximately8 dB higher than the required 62 dB for 10-bit resolutionThis 8 dB margin is kept to counter the loss due to circuitnonidealities This is why 4th-order modulator is chosen forimplementation

223 Quantizerrsquos Bit A multi-bit quantizer has severaladvantages over a single-bit quantizer [1 2] and compensateswell the SNR limitation due to lower OSR Firstly a multibitquantizer reduces in-band quantization noise by 6 dB andallows more aggressive NTF with higher out-of-band gain(OBG) resulting in further significant drop in in-band quan-tization noise Secondly the amplitude of the noise in amulti-bit quantizer is much lower compared to that in a single-bitquantizer Hence the slew rate requirement on the loop filteropamp is greatly relaxed to allow low-power opamp designThirdly a multi-bit feedback DAC is less sensitive to clockjitter [8] For low power reduced circuit complexity and tokeep peak SNR well above 60 dB a 2-bit quantizer is chosen

224 Out-of-Band Gain (OBG) As a rule of thumb theOBG for a single bit quantizer is 15 to ensure the stability


0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA

Figure 2 SNR and MSA versus the out-of-band gain (OBG) of theNTF for 4th-order 2-bit DSM

[9] However in case of a multi-bit quantizer the OBGcan be increased to reduce the in-band noise and therebyimprove the SNR A 4th-order 2-bit modulator is extensivelysimulated for various OBG to determine the maximum SNRand the maximum stable amplitude (MSA) Consideringthe tradeoff between the SNDR and the maximum stableamplitude (MSA) as depicted in Figure 2 the optimumOBGis chosen to be 2

Now with all parameters in hand the NTF is determinedusing the function synthesizeNTF from [10] A 4th-order 2-bit modulator with OSR of 16 results in a peak SNDR of 70 dBover a signal bandwidth of 20MHz

225 Excess Loop Delay (ELD) Compensation The finiteregenerative time of a flash converter and the digital logicdelay time in the feedback add extra delay called excess loopdelay (ELD) in the loop and effectively increase the orderof the modulator For a modulator of order 2 or above itneeds to be compensated to ensure the stability and maintaina high SNR One of the efficient methods to compensate ELDis coefficient tuning by adding a direct path between the DACoutput and the flash input [1]Though the compensation timecould be any from the circuit design and operation point ofview it is better to compensate for half a clock or integralmultiple of half a clock To use a single clock one clock delaycompensation is used which helps to relax the requirementon analog building blocks opamp and comparator

23 Coefficients Generation and RC Parameters The functionsynthesizeNTF returns discrete-time (DT) coefficients of amodulator which must be translated into continuous-time(CT) coefficients To reduce the clock jitter sensitivity NRZDACpulse is preferred to otherDACpulse shapesWithNRZDAC and one clock compensation for excess loop delay thediscrete-time coefficients are converted into the continuoustime using the function realizeNTF ct available in [10] Theobtained coefficients result in integratorrsquos output which havemuch higher swing for modern low supply voltage like 18 Vand direct implementation would result in large clipping andhence large distortion Also the output of one integrator isinput to the next integrator and therefore large swing willdemand high-input swing for opampwhich costs high power

Table 1 Scaled coefficients

a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029

Therefore the scaling is done to ensure that the output swingsof all integrators are well below themaximumallowed voltage(in our case 18 V) such that they accommodate the saturationvoltage of the output stages of opamps and they do not distortthe signals The resulting coefficients are tabulated in Table 1for the modulator block diagram in Figure 3

Figure 4 shows the block diagram of the loop filter Forsimplicity the diagram is shown single-ended however theactual circuit implementation is done fully differential Thefourth integrator is used to integrate with 119877

41198624and opamp

and the same opamp is used to sum all the feedforwardvoltages with 119886

01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]

The coefficients 1198861 1198862 and 119886

3are realized with the capacitive

sum while the coefficient 1198864is embedded in the integration

with 11987741198624This helps to completely eliminate the summation

opamp and thereby saves a significant amount of powerDelta-sigma

1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)

modulator is a thermal-noise-limited system and the resistorat the input of an active RC integrator contributes themajority of noise So in a thermal-noise-limited modulatorthe resistance value is calculated using (1) [1] Here 119877

1is

the resistance at the input of the first integrator 119881in isthe input signal voltage 119896 is Boltzmann constant 119879 is thetemperature 119891

119861is the frequency bandwidth and 119861 is the

effective number of bits The determined coefficients aretranslated into ldquo119877rdquo and ldquo119862rdquo values with the thermal noiseconstraint as per (1) and keeping the capacitor values suchthat the feedforward capacitors values are not too large asit loads the last integrating opamp The determined firstresistance value is only 1093 kΩ and the capacitance is178 pF The stability and performance of a continuous-timedelta-sigma modulator are strongly dependent on processvariation as it changes the coefficients drastically To mitigatethe effect coefficient tuning is desirable Since resistors areconnected either between input and input to the first opampor between output of one opamp and input of next opamp it isimperative that tuning using capacitance will be much easier


119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC

minusminusminus minus

NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884

Figure 3 The block diagram of a 4th-order FF modulator with direct path for excess loop delay compensation

1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922

Figure 4 The block diagram of a 4th-order CIFF with direct path for excess loop delay compensation

and effective to implement Therefore to combat processvariation capacitive tuning (119862

1to 1198624) is implemented

To predict the SNR the behavioral simulation of themodulator is donewithmacromodel of building blocks usingthe components from analogLib and ahdlLib of cadence Toinclude all the noises thermal and circuit transient noiseis enabled while simulating the design A 16384-point Hannwindow PSD predicts a SNDR of 697 dB for a tone at10547MHz

3 Circuit Implementation

In this section we describe the transistor level circuit designsof the building blocks used in the modulator

31 Opamp A generic two-stagemiller-compensated opampis used for a high-speed and a wide output swing To mitigateinput-referred flicker noise long length input transistors areused To keep the design simple and power consumption lowonly one common mode feedback (CMFB) loop is used tomaintain the output at 119881cm The opamp draws a total current

of 22 mA including the CMFB and biasing from a supply of18 V The designed opamp has GBW of 156119891

119904

32 Comparator A preamp stage with a gain of 10 is used asinput stage A regenerative circuit follows the preamp stageand finally SR-latch is used to output the decision Separatereferences for differential input are used to avoid the couplingbetween the two differential inputsThe comparator settles itsoutput within 120 ps

33 Feedback DAC Feedback DAC is designed in two partsFirst part is a d-flip-flop [11]which is used to retime the outputof the quantizer In the second part a current steering DAC isused for fast response This DFF and the quantizer effectivelyintroduce a delay of one clock between the input of the flashconverter and the output of the feedback DAC The cascadecurrent source in the DAC cell is used to achieve a high-output resistance The output impedance of the current DACis 70 kΩ


0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)

SNDR = 657dBENOB = 106 bitsOSR = 16

Figure 5 Output Spectrum of the modulator

0

10

20

30

40

50

60

70

SND

R

minus10minus80 minus70 minus60 minus50 minus40 minus30 minus20 minus10 0

Amplitude (dBFS)

DR cong 70dB

Figure 6 Amplitude versus SNDR of the modulator

4 Results and Discussion

To illustrate the design methodology a 4th-order 2-bitcontinuous-time delta-sigma modulator is designed in018 120583m CMOS technology The implemented modulator istested with a single tone at 10547MHz A 16384-point Hannwindow PSD is produced to ensure the sufficient accuracyThe resulted spectrum is shown in Figure 5 From Figure 5it is determined that the peak SNDR is 657 dB over abandwidth of 20MHz Figure 6 has the plot of SNR versusamplitude which gives a high dynamic range of 70 dB Thedesign consumes overall power of 197mW to achieve a figureof merit (FoM) of 031 pJconv

5 Conclusion

A systematic designmethodology of a continuous-time delta-sigma modulator is described A 640MSs 20MHz sig-nal bandwidth 4th-order 2-bit continuous-time delta-sigmamodulator is implemented in 018 120583m CMOS technology toillustrate the design methodology The CT coefficients aresystematically computed compensating for excess loop delayThe designed modulator has a high SNDR of 657 dB and ahigh dynamic range of 70 dB for a signal band of 20MHzThis modulator is well suited for WLAN applications The

modulator consumes 197mW power from a 18 V supply toachieve FoM of 031 pJconv

Acknowledgments

This work was partly supported by a grant of the RegionalInnovation Cluster Program (Global Type 2nd Stage) fromtheMinistry of Education Culture Sports Science and Tech-nology (MEXT) and a Grant-in-Aid for Scientific Research(B) from JSPS KAKENHI (Grant no 23360159) This workwas also partly supported by a grant of the KnowledgeClusterInitiative implemented by Ministry of Education CultureSports Science and Technology (MEXT) KAKENHI (B)and KIBAN (B) and the VLSI Design and Education Center(VDEC) The University of Tokyo in collaboration withCADENCE Corporation and Agilent Corporation

References

[1] M Ortmanns and F Gerfers Continuous-Time Sigma-DeltaAD Conversion Fundamentals Performance Limits and RobustImplementations Springer Berlin Germany 2006

[2] J A Cherry andWM SnelgroveContinuous-TimeDelta-SigmaModulators for High Speed AD ConversionTheory Practice andFundamental Performance Limits Kluwer Academic NewYorkNY USA 2002

[3] S Balagopal R M R Koppula and V Saxena ldquoSystematicdesign of multi-bit continuous-time delta-sigma modulatorsusing two-step quantizerrdquo in Proceedings of the IEEE 54thInternational Midwest Symposium on Circuits and Systems(MWSCAS rsquo11) pp 1ndash4 August 2011

[4] Y Ke S Radiom H R Rezaee G Vandenbosch J Craninckxand G Gielen ldquoOptimal design methodology for high-ordercontinuous-time wideband Delta-Sigma convertersrdquo in Pro-ceedings of the 14th IEEE International Conference on ElectronicsCircuits and Systems (ICECS rsquo07) pp 743ndash746 MarrakechMorocco December 2007

[5] R Schreier and G Temes Understanding Delta-Sigma DataConverters IEEE Press Piscataway NJ USA 2005

[6] S Pavan N Krishnapura R Pandarinathan and P Sankar ldquoApower optimized continuous-time ΔΣ ADC for audio applica-tionsrdquo IEEE Journal of Solid-State Circuits vol 43 no 2 pp 351ndash360 2008

[7] S Pavan ldquoExcess loop delay compensation in continuous-timedelta-sigma modulatorsrdquo IEEE Transactions on Circuits andSystems II vol 55 no 11 pp 1119ndash1123 2008

[8] J A Cherry and W M Snelgrove ldquoClock jitter and quan-tizermetastability in continuous-time delta-sigmamodulatorsrdquoIEEE Transactions on Circuits and Systems II vol 46 no 6 pp661ndash676 1999

[9] W Lee A novel higher-order interpolative modulator topologyfor high resolution oversampling AD converters [MS thesis]Massachusetts Institute of Technology Cambridge Mass USA1987

[10] R Schreier ldquoThe Delta-Sigma Toolbox Version 7 1rdquo httpwwwmathworkscommatlabcentralfileexchange19

[11] M J Park A 4th order continuous-time ΔΣ ADC with VCO-based integrator and quantizer [PhD thesis] MassachusettsInstitute of Technology Cambridge Mass USA 2009


Research ArticleAn Inductorless Cascaded Phase-Locked Loop with PulseInjection Locking Technique in 90 nm CMOS

Sang-yeop Lee Hiroyuki Ito Shuhei Amakawa Noboru Ishihara and Kazuya Masu

Solutions Research Laboratory Tokyo Institute of Technology 4259-S2-14 Nagatsuta Midori-ku Yokohama 226-8503 Japan

Correspondence should be addressed to Sang-yeop Lee leesafmtitechacjp

Received 1 December 2012 Accepted 21 January 2013

Academic Editor Leonid Belostotski

Copyright copy 2013 Sang-yeop Lee et al This is an open access article distributed under the Creative Commons Attribution Licensewhich permits unrestricted use distribution and reproduction in any medium provided the original work is properly cited

An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area 011mm2) by adopting 90 nmSi CMOS technology The proposed circuit is configured with two cascaded PLLs one of them is a reference PLL that generatesreference signals to the other one from low-frequency external reference signals The other is a main PLL that generates high-frequency output signals A high-frequency half-integral subharmonic locking technique was used to decrease the phase noisecharacteristics For a 50 MHz input reference signal without injection locking the 1 MHz offset phase noise was minus88 dBcHz at aPLL output frequency of 72GHz (= 144 times 50MHz) with injection locking the noise was minus101 dBcHz (spur level minus31 dBc powerconsumption from a 10 V power supply 25mW)

1 Introduction

Conventional multistandard wireless mobile terminals con-tain multiple RFICs To reduce production costs one-chipwideband RF LSI systems are desired A great effort is beingmade to develop wideband andor multiband RF solutionsusing highly scaled advanced CMOS processes The use ofsuch processes is beneficial to 119860119863 and 119863119860 convertersand digital baseband circuits However it is very difficultto reduce the scale of RFanalog circuit blocks especiallypower amplifiers and oscillator circuits including voltage-controlled oscillators (VCOs) and phase-locked loops (PLLs)because of the presence of inductors that do not scale withadvancements in technology

In designing VCOs which generate signals in RF systemsring-type VCOs (ring VCOs) are more attractive than LC-resonant-type VCOs (LC VCOs) in terms of their small areaand wide frequency tuning range since they do not use largepassive devices However they have poor phase noise withrelatively high power consumption Nevertheless low-phase-noise ring VCO is still a possibility if some noise-suppressionmechanism is applied One of available options would beinjection locking

In the early days Adler [1] and many other authorsstudied the behavior of VCOs with injection locking Also

there are numerous papers published in reference to VCOswith injection locking in order to achieve phase lockingand high performances Moreover recently PLLs with aninjection-locked frequency divider and frequency multiplierand a clock and data recovery circuit (CDR) were presented

This paper describes a study on a ring-VCO-based PLLwith pulse injection locking as a potential solution to realizea scalable inductorless PLL which can generate widebandfrequency signal with low supply voltage Usually the fre-quency range utilized consumer RF applications such aswireless LAN abgn Bluetooth and digital TV (DTV) isvery wide and spreading from 400MHz to 6GHz Table 1shows target performance of the proposed PLL Generallyin RF systems using high transmitting power a frequencysynthesizer should generate higher-frequency signals up to12GHz to avoid injection pulling from a power amplifierThen some methods such as using frequency dividers andmixers are applied to widen frequency range [2 3]

In addition the proposed PLL is augmented with high-frequency half-integral subharmonic locking in order toimprove its phase-noise performance In Section 2 brieffeatures of the proposed PLL are explained In Section 21high-frequency half-integral subharmonic locking is shownas a method of reducing phase noise Also the proposed


Table 1 Target performance

VCO RingFrequency range 6ndash12GHzPhase noise at 1MHz offset minus100 dBcHzCMOS process 90 nmSupply voltage 10 V

RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref

Figure 1 Injection-locked PLL with pulse injection

cascaded PLL (CPLL) that can achieve injection locking athigh frequencies from low-frequency reference is presentedDetailed circuit designs such as a VCO and a charge pumpwhich are able to realize wide-band operation and themeasurement results obtained from an implementation in90 nm CMOS process are presented in Sections 3 and 4respectively Finally we conclude this work in Section 5

2 Injection Locking in Frequency Synthesizers

Figure 1 shows an injection-locked PLL (ILPLL) The PLL isbased on a ring VCO that is able to generate high-frequencyoutputs across wide frequency range as well as 119868119876 outputsThe PLL also consists of a phase frequency detector (PFD)a charge pump (CP) a loop filter (LF) a variable delay unit(Δ119879) and a pulser

PLLs that use ring type VCOs are required to have a wideloop bandwidth of the phase-locked loop for lowering theirpoor phase noise characteristics However there is a trade-off between the loop bandwidth and the stability of PLLs Ingeneral the loop bandwidth (120596

minus3 dB) must be narrower than120596ref20sim120596ref10 where 120596ref is the reference-signal frequency[4] Consequently there is a limitation on lowering the phasenoise in ring-VCO-based charge-pump PLLs (CP PLLs)Figure 2 shows phase noise characteristics of the PLL In thiscase the charge-pump noise of the PLL is assumed to besmall enough and can be neglected In Figure 2 phase noiseis suppressed up to the loop bandwidth (120596

minus3 dB) by the noisefiltering of the loop On the other hand pulse injection lock-ing is effective to reduce phase noise of ring VCOs since ringVCOshave awider lock rangewith injection locking than thatof LC VCOs because of their low quality factors In designingsubharmonically injection-locked oscillators (ILOs)119873 timesfrequency-multiplied signals as to the reference frequency

Injection-lockedoscillator

Free-runningoscillator

Phase-noise reduction

Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )

120596minus3 dB 120596minus3 dB

1205960 minus 120596119871 1205960 1205960 + 120596119871

Figure 2 Phase-noise reduction with a charge-pump PLL andinjection locking

can be achieved The lock range is decided by the power of119873th superharmonics of the reference signal as follows [1 5]

120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)

where119876 represents the open-loop quality factor of an oscilla-tor (calculated by using the open-loop transfer function of theoscillator [6]) 120596out is the output frequency of the oscillatorunder injection locked condition 119875inj119873 is the119873th harmonicpower of the reference signal and 119875

0is the free-running

output power of the oscillator 119875inj119873 is approximately givenby

119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)

where 119860 is the pulse amplitude 119863 is the duty cycle of pulses(119863 = Δ119879119879 Δ119879 pulse width 119879 period of pulses) From (1)and (2) the lock range 120596

119871can be rewritten as follows

120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)

where 120596inj (= 1205960119873) is the injection-signal frequency [7]The overall ILO output phase noise is obtained by adding

the noise contributions in an ILO Assuming that 119878ILO(120596)119878REF(120596) and 119878VCO(120596) are phase noise power functions of aninjection-locked VCO a reference signal and a free-runningVCO respectively the phase noise of an ILO 119878ILO(120596) simplycan be expressed as

119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)

where 119878REF119872 is the normalized phase noise power functionwith respect to the output frequency of 119891out and 119872 meansthe ratio between the output frequency (119891out) and the inputfrequency (119891inj) 119867LPF(119895120596) and 119867HPF(119895120596) are low-pass and


Phase corrections by injection signals

119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)

Figure 3 Voltage and current waveforms at differential outputnodes of a VCO (a) integral subharmonic locking (119891

0= 119891inj) (b)

half-integral subharmonic locking (1198910= 15119891inj)

high-pass transfer functions respectively [8] Supposed that119867HPF(119895120596) and 119867LPF(119895120596) have the first-order transfer func-tions and they have the same cutoff frequency of 120596

119871 the

simple equation of (4) would be achieved [5 9 10]In the proposed PLL there are two kinds of phase

locking mechanism one is a phase-locked loop and theother is pulse injection locking In general either of them isenough for phase locking However those two mechanismsare combined to get a wide frequency range operation with alow-phase-noise performanceThe phase-locked loop whichuses a charge pump for controlling the oscillation frequencyis implemented to ensure correct frequency locking over theentire VCO tuning range The final phase locking is done byinjection locking to reference signal [11ndash13]

21 High-FrequencyHalf-Integral Subharmonic Locking Topol-ogy for Noise Reduction A paper on half-integral subhar-monic injection locking based on the use of a ring VCOhas been presented [8] A differential VCO can be easilydesigned to lock to half-integral subharmonics by givingits necessary symmetry properties Suppose that a VCOconsists of differential circuits and has a certain symmetryAs a method to achieve injection locking a direct injectiontechnique is applied which uses nMOS switches that shortthe differential outputs for phase corrections Figure 3 showsdifferential waveforms (119881d1 119881d2) of the VCO in the caseof both integral (119891

0= 119891inj) and half-integral subharmonic

locking (1198910= 15119891inj) The two output nodes are shorted

when the injection signal (119881inj1119881inj2) is input into the nMOSswitches Phase corrections may occur at the time and thejitter is reduced Generally there are two points of timeduring the period of the output signal when two output nodescan be shorted because of topological symmetry as shownin Figure 3 Consequently the differential VCO is capable ofboth integral and also half-integral subharmonic locking

One advantage of using half-integral subharmonic lock-ing is to be able to use high-frequency reference signal andcan make the locking range of injection locking 120596

119871wide

as shown in (1) Figure 2 and Equation (4) also show that

VCO1 VCO2

119891inj 119878REF 119891out1 119878ILO1 119891out2 119878ILO2

119881b1 119881b2

Figure 4 Concept of the cascaded ILOs

the phase noise of the reference signal mainly affects theoutput phase noise at lowoffset frequencies and that the phasenoise of the PLL becomes dominant as the offset frequencyapproaches the edge of the locking range [11]Therefore it willimprove phase noise characteristics to the edge of the lockingrange to use high-frequency reference signals

22 High-Frequency Signal Generation with Cascaded ILOsAs shown in (3) the lock range is proportional to the inputfrequency of 120596inj However narrower pulses are required toachieve smaller 119863 with increasing the multiplication ratio(119873) Unfortunately it is difficult to achieve sufficiently narrowpulses even with the use of nm-scale CMOS processes sincethe reference inputs also have certain jitter and parasiticcomponents of the pulser limit the pulse width In otherwords there is limitation to generate high-frequency (over5GHz) injection-locked signalswith low-frequency referencesuch as XTALs

One solution is to employ cascaded oscillators [11] whichmake each multiplication ratio (119873) smaller by using twomultiplication processes Figure 4 shows the concept of thecascaded ILOs Firstly the input signal which has sufficientlyhigh-power superharmonics is injected intoVCO1Then119872

1

multiplied frequency signal (119891out1 = 1198721 sdot119891inj) of the referencefrequency can be achieved by tuning the VCO1 oscillationfrequency properly In this case the output phase noise ofVCO1 with injection locking can be expressed as follows

119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711

is the lock range that is proportional to the inputfrequency (119891inj) and can be calculated from (3)

The output signal of VCO1 is injected into VCO2 andlocked to the output of VCO2with the same process occurredinVCO1 Also the output phase noise of VCO2with injectionlocking can be expressed as follows

119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734

Figure 5 Proposed cascaded injection-locked PLL (CPLL) with pulse injection

Table 2 Dividers ratio in Figure 5

1198731

1198732

1198733

1198734

32 24 36 1 8 4 8

where1198722is the ratio between the output frequency of VCO2

(119891out2) and input frequency (119891out1) and 1205961198712 is the lock rangeof VCO2 When the offset frequency of 120596 is sufficientlylower than 120596

1198712(ie 120596 ≪ 120596

1198712) (7) is held In other words

sufficiently wide lock range makes it possible to neglect thesecondary VCO phase noise up to the lock range in cascadedILOs

3 Proposed Injection-Locked PLL Topology

Figure 5 shows the configuration of the proposed PLL thatenables the use of half-integral subharmonic locking whichwas proposed in our previous work [13] The proposedPLL consists of two injection-locked PLLs A referencePLL namely RPLL generates reference signals to a mainPLL namely MPLL from low-frequency external referencesignals In this topology when we choose divider ratios(Table 2) respectively as 119873

2= 36 119873

3= 1 and 119873

4=

8 the ratio between the reference signal to MPLL and theoutput frequency of MPLL may be 45 and high-frequencyhalf-integral subharmonic locking can be applied Variabletime delay cells Δ119879s are implemented to control the timewhen injection signals are input because phase correctionscan occur easily when differential output nodes are shortedin the direct injection locking scheme (Figure 3)

31 Main PLL Figure 6(a) shows the topology of the pro-posed delay cell that composes a ring VCO [13] The delaycell contains an inverter latch as a negative conductancecircuit that generates delay by positive feedback in orderto satisfy the oscillation condition [14] To tune the VCOoutput frequency widely variable pMOS resistive loads areused However in the commonly used delay cells with pMOSresistive loads the range of control voltage is limited from0V to the pMOS threshold voltage In the proposed delaycell a pMOS transistor is added into which the subcontrolvoltage (119881bn) is input in order to make the range of sensitivevoltages identical to the rail-to-rail voltage range (0V to119881DD) For this purpose the bias level shifted by about 119881DD2119881bn is input to the added pMOS transistor As a result

119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)

Bias-level-shift circuit119881b

119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)

Figure 6 (a) Proposed differential delay cell (b) two-stage differ-ential VCO of MPLL with a bias-level-shift circuit

the total equivalent resistance of the two pMOS transistorsin parallel changes almost linearly versus the main controlvoltage 119881b Consequently the VCO output frequency can betuned linearly across thewide tuning range [12 13] An nMOSswitches are connected at the nodes between the differentialnodes to achieve injection locking [15]

The proposed ring VCO is shown in Figure 6(b) It isbased on a two-stage pseudodifferential ring oscillator Pulseswhich are generated by the on-chip pulser are injected intothe left delay cell in the form of rail-to-rail pulses for injectionlocking To maintain topological symmetry an nMOS switchbiased to 0V is also applied in the right-side delay cellWe achieved the VCO tuning range of 602GHz to 111 GHzacross the rail-to-rail control voltage from the postlayoutsimulation of the VCO core with output buffers (90 nmCMOS process 119881DD = 10V)

A tristate phasefrequency detector (PFD) is imple-mented which consists of twoD-flip flops delay-path invert-ers and an AND logicThe PFD detects phase and frequencydifference between the reference signal and the divided VCOoutput and generates output pulses of119881UP and119881DN which areinput into the charge pump to reduce the difference


M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn

Figure 7 Sooch cascode current mirror circuit

119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622

Figure 8 Proposed charge-pump (CP) circuit and loop filter (LF)

Figure 7 shows an implemented current mirror circuitto generate stable constant current from the charge pumpUsually stacked current mirrors design can obtain better DCheadroom and linearity with longer channel lengths as shownin the left side of Figure 7 In this case DC headroom of theoutput voltage (119881out) is expressed as 2(Δ ov + 119881thn) whereΔ ov is the overdrive voltage of MOS transistors (M3 M4)and 119881thn is an nMOS threshold voltage In the case of Soochcascode current mirror as shown in the right side of Figure 7the MOS transistor M5 is forced to operate in the trioderegionTheDCheadroom can be reduced as 2Δ ov sinceMOStransistors operate in the saturation region except forM5 [16]Consequently low voltage operation can be achieved

Proposed current switching charge pump (CP) thatemploys Sooch cascode current mirror is shown in Figure 8Dummy switches are also implemented to maintain thebalance between PFD outputs Two external current sourcesranged from 10 120583A to 150 120583A are used

Figure 9 shows postlayout simulation results of theproposed charge pump when 119868CP = 20 120583A (90 nm CMOSprocess 10 V supply) It shows that the charge pump cangenerate quite constant output current across the wide range

0 025 05 075 1

0

10

20

Control voltage (119881b) (V)

Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20

Figure 9 Charge-pump output current versus the control voltage(119881b) when 119868CP = 20 120583A

of the output voltage (119881b) When 119881UP = 1V and 119881DN = 0Vthe result shows current mismatch between the up and downoutput currents as a function of the output voltage (119881b) Thepercentage mismatch error for 048119881 le 119881b le 081V is less


Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)

Figure 10 Chip micrographs (a) proposed VCO and (b) proposed PLL

than 2 and increases to less than 5 for 021119881 le 119881b le

085VA second-order lag-lead filter that consists of a register

and two capacitors is implemented as a loop filter (LF) of theloop to suppress the charge-pump ripple (119877 = 16 kΩ 119862

1=

41 pF1198622= 12 pF) In this case on-chipMIM capacitors were

usedThe frequency divider consists of differential pseudo-

nMOS latches to minimize chip area and achieve low powerconsumption [17] The frequency divider chain consists ofthree divide-by-2 circuits and one divide-by-23 circuit Asa result it can divide by 24 and 36 in the loop (ie dividerratio119873

1= 24 36)

The loop dynamic characteristics are designed to havethe unity-gain bandwidth of 28MHz and phase margin of16∘ (VCO gain 5GHzV 119868CP = 20 120583A divider ratio 119873

1=

24) When the divider ratio 1198731equals to 36 the unity-gain

bandwidth of 22MHz and phase margin of 19∘ are achievedThe PLL has poor phase margin that is related to the lowdamping factor and the slow settling time because final phaselocking is done not only by the phase-locked loop but alsoby injection locking Injection locking that is applied into aphase-locked loop helps the phase margin to be improved[21] In this case large capacitance of 119862

2is required to

suppress the reference spur level due to the control voltageripple A loop bandwidth of the PLL is designed to be smallenough compared to the lock range of injection locking toavoid the interference between two phase locking but can stillachieve frequency locking

To achieve subharmonic locking an AND-based pulseris used which is able to tune the pulse width below 40 psby the analog control Also a variable time-delay unit (Δ119879)which consists of inverters and tristate inverters was appliedtomatch the zero-crossing points of differential VCO outputsto the pulses for effective injection locking

32 Reference PLL The proposed ring VCO used in RPLLis based on a four-stage pseudo differential ring oscillatorThe same delay cell shown in MPLL (Figure 6(a)) is appliedto widen frequency tuning range linearly Also long-gatechannel MOS transistors are equipped in the delay cell todecreaseVCOoscillation frequencies and reduce flicker noise

characteristics as a reference signal into MPLL Pulses whichare generated by the on-chip pulser are injected into theleft delay cell in the form of rail-to-rail pulses for injectionlocking To maintain topological symmetry an nMOS switchbiased to 0V is also applied in the other delay cells Weachieved the VCO tuning range of 0805GHz to 285GHzacross the rail-to-rail control voltage from the postlayoutsimulation of the VCO core with output buffers (90 nmCMOS process 119881DD = 10V)

The tristate PFD and CP presented in Figure 8 areimplemented in RPLL With postlayout simulation results ofthe charge pump (90 nm CMOS process 10 V supply) thepercentage mismatch error (119868CP = 100 120583A) for 032 119881 le 119881b le070V is less than 2 and increases to less than 5 for 024119881 le 119881b le 076V (119881UP = 1V 119881DN = 0V)

As a loop filter (LF) a second-order lag-lead filter isimplemented The filter consists of a register (119877 = 16 kΩ)and two on-chip capacitors (119862

1= 41 pF 119862

2= 1 pF) The

frequency divider chain in RPLL consists of five divide-by-2 circuits As a result it can divide by 32 (ie divider ratio1198732= 32) Finally the AND-based pulser and the variable

time-delay unit (Δ119879)were implemented for effective injectionlocking In RPLL an injection frequency of 119891inj1 is same to areference frequency of 119891ref

4 Measurement Results

41 Main PLL (MPLL) Figures 10(a) and 10(b) show chipmicrograph of the differential ring VCO and a PLL respec-tively To clear the effectiveness of the proposed PLL theVCOcell used in the PLL was also fabricatedThey were fabricatedby a 90 nm Si CMOS process The area of the ring VCO coreis 0030 times 0045mm2 including the bias-level-shift circuitand the pulser The PLL circuit occupies an area of 038 times021mm2 They were measured in 10 V supply conditionAlso the PLL circuit was measured using 20120583A-current-sources (119868CP) into the charge pump

During free-running operation the frequency tuningrange of the VCOwas from 635GHz to 115 GHz as shown inFigure 11 It was measured by using an Agilent TechnologiesE5052B signal source analyzer It also shows that the VCO


0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)

Figure 11 Measured frequency tuning range of the VCO

Offset frequency (Hz)

Free-running VCO

300-MHz reference

PLL wo injPLL wi injVCO wi inj

Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107

Figure 12 Measured phase noise characteristics at 72 GHz from theVCO and PLL output without and with injection locking

output frequency could be tuned quite linearly versus the rail-to-rail control voltage (119881b) due to the bias-level-shift circuitWhen the VCO output frequency (119891

0) is 718GHz the total

power consumption of the VCO (with the bias-level-shiftcircuit and pulser) was 84mW

Phase noise characteristics of the VCO and PLL at 1198910≃

119891out = 72GHz without and with injection locking are shownin Figure 12 as measured by the signal source analyzer Inaddition to them phase noise characteristics of the 300MHzreference signal are shown in Figures 12 and 14 A 1MHz-offset phase noise of minus758 dBcHz was generated in the free-running VCO With injection locking a 1MHz offset phasenoise of minus108 dBcHz was generated which was improved by32 dB compared to the former On the other hand a 1MHz-offset phase noise of minus913 dBcHz was generated in the PLLwhen the PLL was only locked by the phase-locked loop Dueto the poor phasemargin gain peaking at the offset frequencyof about 3MHz was observed With injection locking a1MHz offset phase noise of minus107 dBcHz was generatedwhich was improved by 16 dB compared to the former

Figure 13 shows calculated phase noise characteristicsby using (4) and the measurement phase noise of the free-running VCO and the reference signal as shown in Figure 12

VCO wi inj (mea)

119891L = 20MHz (cal)119891L = 40MHz (cal)119891L = 60MHz (cal)


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107

Figure 13 Calculated phase noise by using (4) and measure phasenoise characteristics as shown in Figure 12

Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160

Figure 14 Measured phase noise characteristics at 108GHz fromthe VCO and PLL output without injection locking

The results show that wider lock range makes lower phasenoise characteristics within the lock range From the calcu-lated result of 119891

119871= 1205961198712120587 = 40MHz (4) is well matched to

the measurement results except the offset-frequency regionup to about 30 kHz It is because that flicker noise model asexpressed in [5] is not included for simplicity and certainspurs occurred at the offset frequency of about 10 KHz weremeasured


119891out = 108GHz are shown in Figure 14 A 1MHzoffset phasenoise of minus795 dBcHz and minus837 dBcHz were generated inthe free-running VCO and the PLL respectively Phase noisereduction with injection locking could not be achieved sinceit was difficult to generate effective injection pulses withsufficient power for achieving the injection-locked conditionat that high output frequency

42 Cascaded PLL Figure 15 shows a chip micrograph ofthe proposed CPLL It was fabricated by a 90 nm Si CMOSprocess It includes both RPLL and MPLL that occupy anarea of 011mm2 It was measured in 10 V supply conditionAlso the PLL circuit was measured using 100 120583A current


RPLL

MPLL

021

mm

026

mm

012 mm

038 mm

Figure 15 A chip micrograph of the proposed cascaded PLL

Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference

Offset frequency (Hz)103 104 105 106 107

minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80

Figure 16 Measured phase noise characteristics of RPLL output at16 GHz

sources into RPLL charge pump and 20 120583A current-sourcesinto MPLL charge pump RPLL was locked to referencesignals of 50MHz which were generated by the pulse patterngenerator

Figure 16 shows the phase noise characteristics at 119891rout =16GHz (= 32 times 50MHz) as measured by an Agilent Tech-nologies E5052A signal source analyzer Without injectionlocking a 1MHz-offset phase noise of minus100 dBcHz wasgenerated in RPLL Due to the poor phase margin gainpeaking at the offset frequency of about 4MHzwas observedWith injection locking the measured phase noise wasminus116 dBcHz at an offset of 1MHz It shows a 16-dB phase-noise reduction with injection locking Also phase noisecharacteristics of the external reference signal are shownFigure 16 At 10 KHz and 1MHz offset the phase noise of thereference signal were minus117 and minus155 dBcHz respectively

Figure 17 shows the phase noise characteristics at 119891mout =72GHz (= 144 times 50MHz) 02 GHz injection signals wereinjected when 119873

2 1198733 and 119873

4are corresponding to 36

8 and 8 respectively Also 16 GHz injection signals wereinjected when 119873

2 1198733 and 119873

4are corresponding to 36 1

and 8 respectively Without injection into MPLL a 1MHzoffset phase noise of minus88 dBcHz was generated in the PLLWith integral subharmonic injection locking (119891mout = 36 times

Table 3 Performance summary at 119891out = 72GHz

This work MPLLVCO MPLL CPLL

119891out [GHz] 72119891ref [MHz] mdash 300 50119891inj [MHz] 300 300 200 1600119891out119891inj 24 24 36 45119871(Δ119891)|

Δ119891=1MHz [dBcHz] minus108 minus107 minus99 minus101

Power consumption [mW] 84 14 25Area [mm2] 00014 0080 011

Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107

Figure 17 Measured phase noise characteristics of CPLL output at72 GHz

119891inj2 119891inj2 = 02GHz) the measured phase noise wasminus99 dBcHz at an offset of 1MHz With high-frequency half-integral subharmonic locking (119891mout = 45 times 119891inj2 119891inj2 =16GHz) we successfully achieved 2 dB lower phase noise at1MHz offset than the former A 4MHz offset phase noisewas improved by 4 dB in the latter case compared withthe former The results show that high-frequency referenceinjections can widen the injection lock range However therewas a spur around the offset frequency of 25MHz owingto the RPLL spur level and the spur limited the lock rangewidening with high-frequency signal injections

Usually spurs are induced by periodic phase shift due toinjection locking The spur level can be expressed as follows

radic

119875spur120596inj

1198750

asymp

1205960

2119876120596injsdot radic

119875inj119873

119875osc=

120596119871

120596inj (8)

where 119875spur120596inj represents the spur levels occurred by thereference signal at 119891

0plusmn 119891inj and 1198750 is the injection-locked

output power of the oscillator [22] As shown in this equationthe spur level would be reduced lowering the lock range withthe same reference frequency however which is undesirableto reduce phase noise characteristics

Calculated phase noise characteristics by using (6) andmeasure phase noise characteristics as shown in Figures 12and 16 are shown in Figure 18 In this case the lock rangewas supposed to be proportional to the input frequency andthe coefficient was 014 which was expected in Figure 13 In


Table 4 Performance comparison of PLLs

Reference CMOS Technology 1198910[GHz] 119873 = 119891

0119891ref 119871 in-band [dBcHz] 119871

lowast

normalized [dBcHz2] Power [mW] Area [mm2] VCO

This work 90 nm16 32 minus116 minus223 11 (sim) 0031

Ring72 144 minus101 minus221 25 01196 192 minus93 minus216 27

[11] 90 nm 20 20 minus113 minus229 38 046 LC[18] 90 nm 924 35 minus97 minus212 56 009 Ring[19] 018 120583m 898 17 minus110 minus222 58 077 LC[20] 018 120583m 845 32 minus98 minus212 117 55 LClowastNormalized in-band phase noise = 119871 in-band ndash 20log119873 ndash 10log119891ref

16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)


Figure 18 Calculated phase noise by using (6) andmeasuring phasenoise characteristics as shown in Figures 12 and 16

the results phase noise characteristics especially at the offsetfrequency of 500 kHz 700 kHz and lower than 5 kHz due tothe secondaryVCO (VCO2)would be reduced by using high-frequency injection signals (119891inj = 16GHz 119891

119871= 224MHz)

In Figure 18 measured phase noise characteristics from theoffset frequency of 30 kHz to 1MHzwere degraded comparedwith calculated results due to induced noise from the MPLLloop

Figure 19 shows the phase noise characteristics at 119891mout =96GHz (= 192 times 50MHz) In these cases119873

21198733 and119873

4are

corresponding to 24 8 and 8 respectively Without injectioninto MPLL a 1MHz offset phase noise of minus85 dBcHz wasgenerated in the PLL With integral subharmonic injectionlocking (119891mout = 48 times 119891inj2 119891inj2 = 02GHz) the measuredphase noise was minus93 dBcHz at an offset of 1MHz InFigure 19 spur levels around the offset frequency of 25MHzwere decreased because the phase-locking effect of injectionlocking was decreased

The PLL generated reference spurs of lower than minus31 dBcat the output frequency of 72GHz with 16GHz injectionsas shown in Figure 20(a) At the output frequency of96GHz with 02GHz injections reference spurs of lowerthan minus27 dBc were measured as shown in Figure 20(b)

Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107

Figure 19 Measured phase noise characteristics of CPLL output at96GHz

A performance summary at the output frequency of72GHz of the fabricated chips are given in Table 3when injection locking was established It shows that high-frequency injections are effective to reduce the phase noisebecause a wide injection lock range can be achieved

A performance comparison of the PLL with other PLLsthat were designed using various kinds of phase-lockingmethods is given in Table 4 Unfortunately the proposedPLL cannot cover wide frequency range from 6GHz to12GHz as shown in Table 1 due to the VCO tuning rangeand limitation of tunable divider ratio To make a fair in-band phase noise comparison between various kinds of PLLdesigns the dependency of in-band phase noise on 119891ref and119873 should be normalized out [23] Therefore normalized in-band phase noise 119871normalized was applied for comparisonTheproposed PLL shows a relatively good 119871normalized value Alsoits area and power consumption are small and comparable tothat of other circuits

5 Conclusion

An inductorless PLL architecture using the combinationof a phase-locked loop and injection locking with a ringVCO was proposed The proposed CPLL that consists oftwo PLLs was designed in order to generate high-frequencyoutput signals with low-frequency external reference signalsHigh-frequency half-integral subharmonic injection locking


Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)

96 10191Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)

Figure 20 Measured frequency spectra of CPLL output (a) at 72 GHz and (b) at 96GHz

to improve the phase noise characteristics of the inductorlessPLL was implemented

The injection-locked PLL was fabricated by adopting90 nm Si CMOS technology A 1MHz-offset phase noiseof minus101 dBcHz was achieved at an output frequency of72GHz which was improved by 25 dB compared with that ofthe free-running VCOThe area of this inductorless PLL wasas small as 011mm2 with low power consumption of 25mW

Acknowledgments

This work was partly supported by STARC KAKENHIMICSCOPE and VDEC in collaboration with Agilent Tech-nologies Japan Ltd Cadence Design Systems Inc andMentor Graphics Inc The authors also acknowledge theJSPS Research Fellowship for Young Scientists from the JapanSociety for the Promotion of Sciences

References

[1] RAdler ldquoA study of locking phenomena in oscillatorsrdquoProceed-ings of the IRE vol 34 pp 351ndash357 1946

[2] Y Ito H Sugawara K Okada and K Masu ldquoA 098 to 66GHztunable wideband VCO in a 180 nm CMOS technology forreconfigurable radio transceiverrdquo in Proceedings of the IEEEAsian Solid-State Circuits Conference (ASSCC rsquo06) pp 359ndash362November 2006

[3] B Razavi ldquoCognitive radio design challenges and techniquesrdquoThe IEEE Journal of Solid-State Circuits vol 45 no 8 pp 1542ndash1553 2010

[4] F M Gardner ldquoCharge-pump phase-lock loopsrdquo IEEE Transac-tions on Communications vol 28 no 11 pp 1849ndash1858 1980

[5] X Zhang X Zhou and A S Daryoush ldquoA theoretical andexperimental study of the noise behavior of subharmoni-cally injection locked local oscillatorsrdquo IEEE Transactions onMicrowave Theory and Techniques vol 40 no 5 pp 895ndash9021992

[6] B Razavi ldquoA study of phase noise in CMOS oscillatorsrdquo IEEEJournal of Solid-State Circuits vol 31 no 3 pp 331ndash343 1996

[7] S Lee N Kanemaru S Ikeda et al ldquoA ring-VCO-based injec-tion-locked frequency multiplier with novel pulse generationtechnique in 65 nm CMOSrdquo IEICE Transactions on Electronicsvol 95 no 10 pp 1589ndash1597 2012

[8] Y Kobayashi S Amakawa N Ishihara and K Masu ldquoA low-phase-noise injection-locked differential ring-VCO with half-integral subharmonic locking in 018120583mCMOSrdquo in Proceedingsof the 35th European Solid-State Circuits Conference (ESSCIRCrsquo09) pp 440ndash443 September 2009

[9] T Sugiura and S Sugimoto ldquoFMnoise reduction of Gunn-effectoscillators by injection lockingrdquo Proceedings of the IEEE vol 57no 1 pp 77ndash78 1969

[10] M C Chen and C Y Wu ldquoDesign and analysis of CMOS sub-harmonic injection-locked frequency triplersrdquo IEEE Transac-tions on Microwave Theory and Techniques vol 56 no 8 pp1869ndash1878 2008

[11] J Lee andHWang ldquoStudy of subharmonically injection-lockedPLLsrdquoThe IEEE Journal of Solid-State Circuits vol 44 no 5 pp1539ndash1553 2009

[12] S Y Lee S Amakawa N Ishihara and K Masu ldquoLow-phase-noise wide-frequency-range ring-VCO-based scalable PLLwithsubharmonic injection locking in 018 120583m CMOSrdquo in Proceed-ings of the IEEE MTT-S International Microwave SymposiumDigest (MTT rsquo10) pp 1178ndash1181 May 2010

[13] S Y Lee S Amakawa N Ishihara and K Masu ldquoHigh-frequency half-integral subharmonic locked ring-VCO-basedscalable PLL in 90 nm CMOSrdquo in Proceedings of the IEEEAsia-Pacific Microwave Conference (APMC rsquo10) pp 586ndash589December 2010

[14] B RazaviDesign of Analog CMOS Integrated Circuits McGraw-Hill New York NY USA 2001

[15] M Tiebout ldquoA CMOS direct injection-locked oscillator topol-ogy as high-frequency low-power frequency dividerrdquo IEEEJournal of Solid-State Circuits vol 39 no 7 pp 1170ndash1174 2004

[16] P R Gray P J Hurst S H Lewis and R GMeyerAnalysis andDesign of Analog Integrated Circuits John Wiley amp Sons NewYork NY USA 4th edition 2001

[17] T Sekiguchi S Amakawa N Ishihara and KMasu ldquoInductor-less 89mW 25Gbs 14 DEMUX and 4mW 13Gbs 41 MUXin 90 nm CMOSrdquo Journal of Semiconductor Technology andScience vol 10 no 3 pp 176ndash184 2010


[18] H Kodama H Okada H Ishikawa and A Tanaka ldquoWidelock-range low phase-noise PLL using interpolative ring-VCOwith coarse frequency tuning and frequency linearizationrdquo inProceedings of the IEEE Custom Integrated Circuits Conference(CICC rsquo07) pp 349ndash352 September 2007

[19] G Y Tak S B Hyun T Y Kang B G Choi and S S ParkldquoA 63ndash9GHz CMOS fast settling PLL for MB-OFDM UWBapplicationsrdquo IEEE Journal of Solid-State Circuits vol 40 no8 pp 1671ndash1679 2005

[20] T Y Lu and W Z Chen ldquoA 3-to-10GHz 14-band CMOSfrequency synthesizer with spurs reduction for MB-OFDMUWB systemrdquo in Proceedings of the IEEE International Solid-State Circuits ConferencemdashDigest of Technical Papers (ISSCCrsquo08) pp 126ndash601 February 2008

[21] S Ye L Jansson and I Galton ldquoAmultiple-crystal interface PLLwith VCO realignment to reduce phase noiserdquo IEEE Journal ofSolid-State Circuits vol 37 no 12 pp 1795ndash1803 2002

[22] M M Izad and C Heng ldquoA pulse shaping technique for spursuppression in injection-locked synthesizersrdquoThe IEEE Journalof Solid-State Circuits vol 47 no 3 pp 652ndash664 2012

[23] X Gao E A M Klumperink M Bohsali and B Nauta ldquoA22GHz 76mW sub-sampling PLL with minus126 dBcHz in-bandphase noise and 015 psrms jitter in 018120583mCMOSrdquo in Proceed-ings of the IEEE International Solid-State Circuits ConferencemdashDigest of Technical Papers (ISSCC rsquo09) pp 392ndash393 393aFebruary 2009







Editorial Board




Contents





















Acknowledgments






Mohammad S Hashmi











1 Introduction













119900 This



119885in = 119895120596 (119871 119904 + 119871119892) +1

119895120596119862gs+ 120596119879119871119904

= 119895120596 (119871119904+ 119871119892) +

1

119895120596119862gs+ 119877119904

(1)






119904



119860 cong

119881out119881119904

cong

11989211989811198921198982[119877119871 (1198771198892+ 1198781198711198892)] [119878119871

1198891]

2 sdot 119878119862gs1 [119878 (119871 1199041 + 1198711198921) + 1119878119862gs1]

(2)




119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+

12057512057212059621198622

gs1119877119904

51198921198981

+

119877FB ((1198711198921 + 119871 1199041) 119862gs1)2

119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900rfbn

119876rfbn) + 120596

2

119900rfbn

10038161003816100381610038161003816100381610038161003816

2

+

1205741198921198981(119877FB + 119877119904)

2((1198711198921+ 1198711199041) 119862gs1)

2

120572119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900dn

119876dn) + 120596

2

119900dn

10038161003816100381610038161003816100381610038161003816

2

(3)

119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+ 119891gn + 119891rfbn + 119891dn (4)

where

120596119900rfbn = radic

1 + 1198921198981119877119904

(1198711198921+ 1198711199041) 119862gs1

119876rfbn =1

119877119904+ 12059611987911198711199041

sdot radic

(1 + 1198921198981119877119904) (1198711198921+ 1198711199041)

119862gs1

120596119900rfbn = radic

1

(1198711198921+ 1198711199041) 119862gs1

119876dn =1

(119877119904|| 119877FB) + 1205961198791119871 1199041

sdot radic

(1198711198921+ 1198711199041)

119862gs1

(5)



1199041and 119871










1198892




1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

119881out1198722

1198721

1198771198892

119877119871


119871119904

119871119892

119885in

119877119904

119881119904

119903119900119862 119892119898119881gs gs


119877

1198942

1198902119904

119877119878

1198711198661 119877 1198902 1198902

1198942119892 119862 1119881 1

119877119904

1198902

1198711199041

119877

1198902

1198921198981119881 1 1198942119889 1198942119899out

119877

+

minus

FB

rfb

119892 rg

gs

rs

ls

lg lg

gs

ls

gs


1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

1198623

1198711199043

1198771198893119862out

119871out

119877out

119881out

1198722

1198721

1198723

1198811198663


Metal 6

Port 2(Metal 6)

Metal 2

Port 1(Metal 6)

Metal 4


25 35 45 55 65 75 85 95 105 115Frequency (GHz)

200

180

160

140

120

100

80

60

40

20

00

Gai

n an

d N

F (d

B)

GainNoise figure



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

150

100

50

0

minus50

minus100

Gai

n (d

B)



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

60

50

40

30

20

10

00

Noi

se fi

gure

(dB)






25 35 45 55 65 75 85 95 105 115Frequency (GHz)

0

minus50

minus100

minus150

minus200

minus250

minus300

minus350

Refle

ctio

n co

effici

ents

(dB)

11987811

11987822

Figure 9 11987811(dB) and 119878

22(dB) of LNA1

20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175


119878 11

(dB)






20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175

minus200


119878 22

(dB)






















Reference BW(GHz)

Gain(dB)

NF(dB)

11987811

(dB)11987822













4 Conclusion



References























1 Introduction






2 CMOS VCOs




Outminus

119881DD

Out+

(a) (b)







119876minus119881119866119881119866119868+ 119868minus 119876+

119881DD 119881DD



FOM = 119875119873 minus 20Log(1198910

Δ119891

) + 10Log(119875DC1mW) (1)













119881119866


Tank 1

Tank 2

119881DD

Out+





OutminusOut+

119881DD

119881Bias

119881Tune






1via 119872

3and 119872

4




1 Two output


119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References

























Contents





















Acknowledgments






Mohammad S Hashmi











1 Introduction













119900 This



119885in = 119895120596 (119871 119904 + 119871119892) +1

119895120596119862gs+ 120596119879119871119904

= 119895120596 (119871119904+ 119871119892) +

1

119895120596119862gs+ 119877119904

(1)






119904



119860 cong

119881out119881119904

cong

11989211989811198921198982[119877119871 (1198771198892+ 1198781198711198892)] [119878119871

1198891]

2 sdot 119878119862gs1 [119878 (119871 1199041 + 1198711198921) + 1119878119862gs1]

(2)




119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+

12057512057212059621198622

gs1119877119904

51198921198981

+

119877FB ((1198711198921 + 119871 1199041) 119862gs1)2

119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900rfbn

119876rfbn) + 120596

2

119900rfbn

10038161003816100381610038161003816100381610038161003816

2

+

1205741198921198981(119877FB + 119877119904)

2((1198711198921+ 1198711199041) 119862gs1)

2

120572119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900dn

119876dn) + 120596

2

119900dn

10038161003816100381610038161003816100381610038161003816

2

(3)

119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+ 119891gn + 119891rfbn + 119891dn (4)

where

120596119900rfbn = radic

1 + 1198921198981119877119904

(1198711198921+ 1198711199041) 119862gs1

119876rfbn =1

119877119904+ 12059611987911198711199041

sdot radic

(1 + 1198921198981119877119904) (1198711198921+ 1198711199041)

119862gs1

120596119900rfbn = radic

1

(1198711198921+ 1198711199041) 119862gs1

119876dn =1

(119877119904|| 119877FB) + 1205961198791119871 1199041

sdot radic

(1198711198921+ 1198711199041)

119862gs1

(5)



1199041and 119871










1198892




1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

119881out1198722

1198721

1198771198892

119877119871


119871119904

119871119892

119885in

119877119904

119881119904

119903119900119862 119892119898119881gs gs


119877

1198942

1198902119904

119877119878

1198711198661 119877 1198902 1198902

1198942119892 119862 1119881 1

119877119904

1198902

1198711199041

119877

1198902

1198921198981119881 1 1198942119889 1198942119899out

119877

+

minus

FB

rfb

119892 rg

gs

rs

ls

lg lg

gs

ls

gs


1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

1198623

1198711199043

1198771198893119862out

119871out

119877out

119881out

1198722

1198721

1198723

1198811198663


Metal 6

Port 2(Metal 6)

Metal 2

Port 1(Metal 6)

Metal 4


25 35 45 55 65 75 85 95 105 115Frequency (GHz)

200

180

160

140

120

100

80

60

40

20

00

Gai

n an

d N

F (d

B)

GainNoise figure



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

150

100

50

0

minus50

minus100

Gai

n (d

B)



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

60

50

40

30

20

10

00

Noi

se fi

gure

(dB)






25 35 45 55 65 75 85 95 105 115Frequency (GHz)

0

minus50

minus100

minus150

minus200

minus250

minus300

minus350

Refle

ctio

n co

effici

ents

(dB)

11987811

11987822

Figure 9 11987811(dB) and 119878

22(dB) of LNA1

20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175


119878 11

(dB)






20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175

minus200


119878 22

(dB)






















Reference BW(GHz)

Gain(dB)

NF(dB)

11987811

(dB)11987822













4 Conclusion



References























1 Introduction






2 CMOS VCOs




Outminus

119881DD

Out+

(a) (b)







119876minus119881119866119881119866119868+ 119868minus 119876+

119881DD 119881DD



FOM = 119875119873 minus 20Log(1198910

Δ119891

) + 10Log(119875DC1mW) (1)













119881119866


Tank 1

Tank 2

119881DD

Out+





OutminusOut+

119881DD

119881Bias

119881Tune






1via 119872

3and 119872

4




1 Two output


119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References








































Acknowledgments






Mohammad S Hashmi











1 Introduction













119900 This



119885in = 119895120596 (119871 119904 + 119871119892) +1

119895120596119862gs+ 120596119879119871119904

= 119895120596 (119871119904+ 119871119892) +

1

119895120596119862gs+ 119877119904

(1)






119904



119860 cong

119881out119881119904

cong

11989211989811198921198982[119877119871 (1198771198892+ 1198781198711198892)] [119878119871

1198891]

2 sdot 119878119862gs1 [119878 (119871 1199041 + 1198711198921) + 1119878119862gs1]

(2)




119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+

12057512057212059621198622

gs1119877119904

51198921198981

+

119877FB ((1198711198921 + 119871 1199041) 119862gs1)2

119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900rfbn

119876rfbn) + 120596

2

119900rfbn

10038161003816100381610038161003816100381610038161003816

2

+

1205741198921198981(119877FB + 119877119904)

2((1198711198921+ 1198711199041) 119862gs1)

2

120572119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900dn

119876dn) + 120596

2

119900dn

10038161003816100381610038161003816100381610038161003816

2

(3)

119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+ 119891gn + 119891rfbn + 119891dn (4)

where

120596119900rfbn = radic

1 + 1198921198981119877119904

(1198711198921+ 1198711199041) 119862gs1

119876rfbn =1

119877119904+ 12059611987911198711199041

sdot radic

(1 + 1198921198981119877119904) (1198711198921+ 1198711199041)

119862gs1

120596119900rfbn = radic

1

(1198711198921+ 1198711199041) 119862gs1

119876dn =1

(119877119904|| 119877FB) + 1205961198791119871 1199041

sdot radic

(1198711198921+ 1198711199041)

119862gs1

(5)



1199041and 119871










1198892




1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

119881out1198722

1198721

1198771198892

119877119871


119871119904

119871119892

119885in

119877119904

119881119904

119903119900119862 119892119898119881gs gs


119877

1198942

1198902119904

119877119878

1198711198661 119877 1198902 1198902

1198942119892 119862 1119881 1

119877119904

1198902

1198711199041

119877

1198902

1198921198981119881 1 1198942119889 1198942119899out

119877

+

minus

FB

rfb

119892 rg

gs

rs

ls

lg lg

gs

ls

gs


1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

1198623

1198711199043

1198771198893119862out

119871out

119877out

119881out

1198722

1198721

1198723

1198811198663


Metal 6

Port 2(Metal 6)

Metal 2

Port 1(Metal 6)

Metal 4


25 35 45 55 65 75 85 95 105 115Frequency (GHz)

200

180

160

140

120

100

80

60

40

20

00

Gai

n an

d N

F (d

B)

GainNoise figure



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

150

100

50

0

minus50

minus100

Gai

n (d

B)



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

60

50

40

30

20

10

00

Noi

se fi

gure

(dB)






25 35 45 55 65 75 85 95 105 115Frequency (GHz)

0

minus50

minus100

minus150

minus200

minus250

minus300

minus350

Refle

ctio

n co

effici

ents

(dB)

11987811

11987822

Figure 9 11987811(dB) and 119878

22(dB) of LNA1

20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175


119878 11

(dB)






20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175

minus200


119878 22

(dB)






















Reference BW(GHz)

Gain(dB)

NF(dB)

11987811

(dB)11987822













4 Conclusion



References























1 Introduction






2 CMOS VCOs




Outminus

119881DD

Out+

(a) (b)







119876minus119881119866119881119866119868+ 119868minus 119876+

119881DD 119881DD



FOM = 119875119873 minus 20Log(1198910

Δ119891

) + 10Log(119875DC1mW) (1)













119881119866


Tank 1

Tank 2

119881DD

Out+





OutminusOut+

119881DD

119881Bias

119881Tune






1via 119872

3and 119872

4




1 Two output


119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References





























Mohammad S Hashmi











1 Introduction













119900 This



119885in = 119895120596 (119871 119904 + 119871119892) +1

119895120596119862gs+ 120596119879119871119904

= 119895120596 (119871119904+ 119871119892) +

1

119895120596119862gs+ 119877119904

(1)






119904



119860 cong

119881out119881119904

cong

11989211989811198921198982[119877119871 (1198771198892+ 1198781198711198892)] [119878119871

1198891]

2 sdot 119878119862gs1 [119878 (119871 1199041 + 1198711198921) + 1119878119862gs1]

(2)




119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+

12057512057212059621198622

gs1119877119904

51198921198981

+

119877FB ((1198711198921 + 119871 1199041) 119862gs1)2

119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900rfbn

119876rfbn) + 120596

2

119900rfbn

10038161003816100381610038161003816100381610038161003816

2

+

1205741198921198981(119877FB + 119877119904)

2((1198711198921+ 1198711199041) 119862gs1)

2

120572119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900dn

119876dn) + 120596

2

119900dn

10038161003816100381610038161003816100381610038161003816

2

(3)

119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+ 119891gn + 119891rfbn + 119891dn (4)

where

120596119900rfbn = radic

1 + 1198921198981119877119904

(1198711198921+ 1198711199041) 119862gs1

119876rfbn =1

119877119904+ 12059611987911198711199041

sdot radic

(1 + 1198921198981119877119904) (1198711198921+ 1198711199041)

119862gs1

120596119900rfbn = radic

1

(1198711198921+ 1198711199041) 119862gs1

119876dn =1

(119877119904|| 119877FB) + 1205961198791119871 1199041

sdot radic

(1198711198921+ 1198711199041)

119862gs1

(5)



1199041and 119871










1198892




1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

119881out1198722

1198721

1198771198892

119877119871


119871119904

119871119892

119885in

119877119904

119881119904

119903119900119862 119892119898119881gs gs


119877

1198942

1198902119904

119877119878

1198711198661 119877 1198902 1198902

1198942119892 119862 1119881 1

119877119904

1198902

1198711199041

119877

1198902

1198921198981119881 1 1198942119889 1198942119899out

119877

+

minus

FB

rfb

119892 rg

gs

rs

ls

lg lg

gs

ls

gs


1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

1198623

1198711199043

1198771198893119862out

119871out

119877out

119881out

1198722

1198721

1198723

1198811198663


Metal 6

Port 2(Metal 6)

Metal 2

Port 1(Metal 6)

Metal 4


25 35 45 55 65 75 85 95 105 115Frequency (GHz)

200

180

160

140

120

100

80

60

40

20

00

Gai

n an

d N

F (d

B)

GainNoise figure



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

150

100

50

0

minus50

minus100

Gai

n (d

B)



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

60

50

40

30

20

10

00

Noi

se fi

gure

(dB)






25 35 45 55 65 75 85 95 105 115Frequency (GHz)

0

minus50

minus100

minus150

minus200

minus250

minus300

minus350

Refle

ctio

n co

effici

ents

(dB)

11987811

11987822

Figure 9 11987811(dB) and 119878

22(dB) of LNA1

20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175


119878 11

(dB)






20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175

minus200


119878 22

(dB)






















Reference BW(GHz)

Gain(dB)

NF(dB)

11987811

(dB)11987822













4 Conclusion



References























1 Introduction






2 CMOS VCOs




Outminus

119881DD

Out+

(a) (b)







119876minus119881119866119881119866119868+ 119868minus 119876+

119881DD 119881DD



FOM = 119875119873 minus 20Log(1198910

Δ119891

) + 10Log(119875DC1mW) (1)













119881119866


Tank 1

Tank 2

119881DD

Out+





OutminusOut+

119881DD

119881Bias

119881Tune






1via 119872

3and 119872

4




1 Two output


119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References



































1 Introduction













119900 This



119885in = 119895120596 (119871 119904 + 119871119892) +1

119895120596119862gs+ 120596119879119871119904

= 119895120596 (119871119904+ 119871119892) +

1

119895120596119862gs+ 119877119904

(1)






119904



119860 cong

119881out119881119904

cong

11989211989811198921198982[119877119871 (1198771198892+ 1198781198711198892)] [119878119871

1198891]

2 sdot 119878119862gs1 [119878 (119871 1199041 + 1198711198921) + 1119878119862gs1]

(2)




119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+

12057512057212059621198622

gs1119877119904

51198921198981

+

119877FB ((1198711198921 + 119871 1199041) 119862gs1)2

119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900rfbn

119876rfbn) + 120596

2

119900rfbn

10038161003816100381610038161003816100381610038161003816

2

+

1205741198921198981(119877FB + 119877119904)

2((1198711198921+ 1198711199041) 119862gs1)

2

120572119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900dn

119876dn) + 120596

2

119900dn

10038161003816100381610038161003816100381610038161003816

2

(3)

119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+ 119891gn + 119891rfbn + 119891dn (4)

where

120596119900rfbn = radic

1 + 1198921198981119877119904

(1198711198921+ 1198711199041) 119862gs1

119876rfbn =1

119877119904+ 12059611987911198711199041

sdot radic

(1 + 1198921198981119877119904) (1198711198921+ 1198711199041)

119862gs1

120596119900rfbn = radic

1

(1198711198921+ 1198711199041) 119862gs1

119876dn =1

(119877119904|| 119877FB) + 1205961198791119871 1199041

sdot radic

(1198711198921+ 1198711199041)

119862gs1

(5)



1199041and 119871










1198892




1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

119881out1198722

1198721

1198771198892

119877119871


119871119904

119871119892

119885in

119877119904

119881119904

119903119900119862 119892119898119881gs gs


119877

1198942

1198902119904

119877119878

1198711198661 119877 1198902 1198902

1198942119892 119862 1119881 1

119877119904

1198902

1198711199041

119877

1198902

1198921198981119881 1 1198942119889 1198942119899out

119877

+

minus

FB

rfb

119892 rg

gs

rs

ls

lg lg

gs

ls

gs


1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

1198623

1198711199043

1198771198893119862out

119871out

119877out

119881out

1198722

1198721

1198723

1198811198663


Metal 6

Port 2(Metal 6)

Metal 2

Port 1(Metal 6)

Metal 4


25 35 45 55 65 75 85 95 105 115Frequency (GHz)

200

180

160

140

120

100

80

60

40

20

00

Gai

n an

d N

F (d

B)

GainNoise figure



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

150

100

50

0

minus50

minus100

Gai

n (d

B)



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

60

50

40

30

20

10

00

Noi

se fi

gure

(dB)






25 35 45 55 65 75 85 95 105 115Frequency (GHz)

0

minus50

minus100

minus150

minus200

minus250

minus300

minus350

Refle

ctio

n co

effici

ents

(dB)

11987811

11987822

Figure 9 11987811(dB) and 119878

22(dB) of LNA1

20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175


119878 11

(dB)






20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175

minus200


119878 22

(dB)






















Reference BW(GHz)

Gain(dB)

NF(dB)

11987811

(dB)11987822













4 Conclusion



References























1 Introduction






2 CMOS VCOs




Outminus

119881DD

Out+

(a) (b)







119876minus119881119866119881119866119868+ 119868minus 119876+

119881DD 119881DD



FOM = 119875119873 minus 20Log(1198910

Δ119891

) + 10Log(119875DC1mW) (1)













119881119866


Tank 1

Tank 2

119881DD

Out+





OutminusOut+

119881DD

119881Bias

119881Tune






1via 119872

3and 119872

4




1 Two output


119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References






























119900 This



119885in = 119895120596 (119871 119904 + 119871119892) +1

119895120596119862gs+ 120596119879119871119904

= 119895120596 (119871119904+ 119871119892) +

1

119895120596119862gs+ 119877119904

(1)






119904



119860 cong

119881out119881119904

cong

11989211989811198921198982[119877119871 (1198771198892+ 1198781198711198892)] [119878119871

1198891]

2 sdot 119878119862gs1 [119878 (119871 1199041 + 1198711198921) + 1119878119862gs1]

(2)




119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+

12057512057212059621198622

gs1119877119904

51198921198981

+

119877FB ((1198711198921 + 119871 1199041) 119862gs1)2

119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900rfbn

119876rfbn) + 120596

2

119900rfbn

10038161003816100381610038161003816100381610038161003816

2

+

1205741198921198981(119877FB + 119877119904)

2((1198711198921+ 1198711199041) 119862gs1)

2

120572119877119904(1198921198981119877FB minus 1)

2

sdot

10038161003816100381610038161003816100381610038161003816

1199042+ 119904 (

120596119900dn

119876dn) + 120596

2

119900dn

10038161003816100381610038161003816100381610038161003816

2

(3)

119891 = 1 +

119877119892+ 119877lg + 119877ss + 119877ls

119877119904

+ 119891gn + 119891rfbn + 119891dn (4)

where

120596119900rfbn = radic

1 + 1198921198981119877119904

(1198711198921+ 1198711199041) 119862gs1

119876rfbn =1

119877119904+ 12059611987911198711199041

sdot radic

(1 + 1198921198981119877119904) (1198711198921+ 1198711199041)

119862gs1

120596119900rfbn = radic

1

(1198711198921+ 1198711199041) 119862gs1

119876dn =1

(119877119904|| 119877FB) + 1205961198791119871 1199041

sdot radic

(1198711198921+ 1198711199041)

119862gs1

(5)



1199041and 119871










1198892




1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

119881out1198722

1198721

1198771198892

119877119871


119871119904

119871119892

119885in

119877119904

119881119904

119903119900119862 119892119898119881gs gs


119877

1198942

1198902119904

119877119878

1198711198661 119877 1198902 1198902

1198942119892 119862 1119881 1

119877119904

1198902

1198711199041

119877

1198902

1198921198981119881 1 1198942119889 1198942119899out

119877

+

minus

FB

rfb

119892 rg

gs

rs

ls

lg lg

gs

ls

gs


1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

1198623

1198711199043

1198771198893119862out

119871out

119877out

119881out

1198722

1198721

1198723

1198811198663


Metal 6

Port 2(Metal 6)

Metal 2

Port 1(Metal 6)

Metal 4


25 35 45 55 65 75 85 95 105 115Frequency (GHz)

200

180

160

140

120

100

80

60

40

20

00

Gai

n an

d N

F (d

B)

GainNoise figure



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

150

100

50

0

minus50

minus100

Gai

n (d

B)



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

60

50

40

30

20

10

00

Noi

se fi

gure

(dB)






25 35 45 55 65 75 85 95 105 115Frequency (GHz)

0

minus50

minus100

minus150

minus200

minus250

minus300

minus350

Refle

ctio

n co

effici

ents

(dB)

11987811

11987822

Figure 9 11987811(dB) and 119878

22(dB) of LNA1

20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175


119878 11

(dB)






20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175

minus200


119878 22

(dB)






















Reference BW(GHz)

Gain(dB)

NF(dB)

11987811

(dB)11987822













4 Conclusion



References























1 Introduction






2 CMOS VCOs




Outminus

119881DD

Out+

(a) (b)







119876minus119881119866119881119866119868+ 119868minus 119876+

119881DD 119881DD



FOM = 119875119873 minus 20Log(1198910

Δ119891

) + 10Log(119875DC1mW) (1)













119881119866


Tank 1

Tank 2

119881DD

Out+





OutminusOut+

119881DD

119881Bias

119881Tune






1via 119872

3and 119872

4




1 Two output


119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

119881out1198722

1198721

1198771198892

119877119871


119871119904

119871119892

119885in

119877119904

119881119904

119903119900119862 119892119898119881gs gs


119877

1198942

1198902119904

119877119878

1198711198661 119877 1198902 1198902

1198942119892 119862 1119881 1

119877119904

1198902

1198711199041

119877

1198902

1198921198981119881 1 1198942119889 1198942119899out

119877

+

minus

FB

rfb

119892 rg

gs

rs

ls

lg lg

gs

ls

gs


1198711199041

1198711198891

1198711198892

1198711198921

1198711198922

11986211198622

119877119891119862119891

1198771198662

119881in

1198771198661

1198811198661

119881119889119889

1198623

1198711199043

1198771198893119862out

119871out

119877out

119881out

1198722

1198721

1198723

1198811198663


Metal 6

Port 2(Metal 6)

Metal 2

Port 1(Metal 6)

Metal 4


25 35 45 55 65 75 85 95 105 115Frequency (GHz)

200

180

160

140

120

100

80

60

40

20

00

Gai

n an

d N

F (d

B)

GainNoise figure



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

150

100

50

0

minus50

minus100

Gai

n (d

B)



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

60

50

40

30

20

10

00

Noi

se fi

gure

(dB)






25 35 45 55 65 75 85 95 105 115Frequency (GHz)

0

minus50

minus100

minus150

minus200

minus250

minus300

minus350

Refle

ctio

n co

effici

ents

(dB)

11987811

11987822

Figure 9 11987811(dB) and 119878

22(dB) of LNA1

20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175


119878 11

(dB)






20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175

minus200


119878 22

(dB)






















Reference BW(GHz)

Gain(dB)

NF(dB)

11987811

(dB)11987822













4 Conclusion



References























1 Introduction






2 CMOS VCOs




Outminus

119881DD

Out+

(a) (b)







119876minus119881119866119881119866119868+ 119868minus 119876+

119881DD 119881DD



FOM = 119875119873 minus 20Log(1198910

Δ119891

) + 10Log(119875DC1mW) (1)













119881119866


Tank 1

Tank 2

119881DD

Out+





OutminusOut+

119881DD

119881Bias

119881Tune






1via 119872

3and 119872

4




1 Two output


119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

150

100

50

0

minus50

minus100

Gai

n (d

B)



20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

60

50

40

30

20

10

00

Noi

se fi

gure

(dB)






25 35 45 55 65 75 85 95 105 115Frequency (GHz)

0

minus50

minus100

minus150

minus200

minus250

minus300

minus350

Refle

ctio

n co

effici

ents

(dB)

11987811

11987822

Figure 9 11987811(dB) and 119878

22(dB) of LNA1

20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175


119878 11

(dB)






20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175

minus200


119878 22

(dB)






















Reference BW(GHz)

Gain(dB)

NF(dB)

11987811

(dB)11987822













4 Conclusion



References























1 Introduction






2 CMOS VCOs




Outminus

119881DD

Out+

(a) (b)







119876minus119881119866119881119866119868+ 119868minus 119876+

119881DD 119881DD



FOM = 119875119873 minus 20Log(1198910

Δ119891

) + 10Log(119875DC1mW) (1)













119881119866


Tank 1

Tank 2

119881DD

Out+





OutminusOut+

119881DD

119881Bias

119881Tune






1via 119872

3and 119872

4




1 Two output


119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























20 35 50 65 80 95 110 125 140 155 170Frequency (GHz)

0

minus25

minus50

minus75

minus100

minus125

minus150

minus175

minus200


119878 22

(dB)






















Reference BW(GHz)

Gain(dB)

NF(dB)

11987811

(dB)11987822













4 Conclusion



References























1 Introduction






2 CMOS VCOs




Outminus

119881DD

Out+

(a) (b)







119876minus119881119866119881119866119868+ 119868minus 119876+

119881DD 119881DD



FOM = 119875119873 minus 20Log(1198910

Δ119891

) + 10Log(119875DC1mW) (1)













119881119866


Tank 1

Tank 2

119881DD

Out+





OutminusOut+

119881DD

119881Bias

119881Tune






1via 119872

3and 119872

4




1 Two output


119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References



























Reference BW(GHz)

Gain(dB)

NF(dB)

11987811

(dB)11987822













4 Conclusion



References























1 Introduction






2 CMOS VCOs




Outminus

119881DD

Out+

(a) (b)







119876minus119881119866119881119866119868+ 119868minus 119876+

119881DD 119881DD



FOM = 119875119873 minus 20Log(1198910

Δ119891

) + 10Log(119875DC1mW) (1)













119881119866


Tank 1

Tank 2

119881DD

Out+





OutminusOut+

119881DD

119881Bias

119881Tune






1via 119872

3and 119872

4




1 Two output


119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


































1 Introduction






2 CMOS VCOs




Outminus

119881DD

Out+

(a) (b)







119876minus119881119866119881119866119868+ 119868minus 119876+

119881DD 119881DD



FOM = 119875119873 minus 20Log(1198910

Δ119891

) + 10Log(119875DC1mW) (1)













119881119866


Tank 1

Tank 2

119881DD

Out+





OutminusOut+

119881DD

119881Bias

119881Tune






1via 119872

3and 119872

4




1 Two output


119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























Outminus

119881DD

Out+

(a) (b)







119876minus119881119866119881119866119868+ 119868minus 119876+

119881DD 119881DD



FOM = 119875119873 minus 20Log(1198910

Δ119891

) + 10Log(119875DC1mW) (1)













119881119866


Tank 1

Tank 2

119881DD

Out+





OutminusOut+

119881DD

119881Bias

119881Tune






1via 119872

3and 119872

4




1 Two output


119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


































119881119866


Tank 1

Tank 2

119881DD

Out+





OutminusOut+

119881DD

119881Bias

119881Tune






1via 119872

3and 119872

4




1 Two output


119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























119881DD 119881DD 119881DD


(a)

1198721 11987221198723 1198724120573

11986801198681


119881119873minus1+

119881119873minus 119881119873+

(b)


Buffer

Out

119881DD




20 40 60 80 100 120 140

Frequency (GHz)

minus70

minus80

minus90

minus100

minus110

minus120

[20]

[20][13]

[14]

[10][15]

[10]

[6]

[7][17]

[16][18]

[11][11]

[19]

[9]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010






2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























2000 2002 2004 2006 2008 2010 2012minus120

minus110

minus100

minus90

minus80

minus70140 [9]

34 [20]

65 [20]

30[6]

50 [10]57[7]

60 [10]104 [11]121 [11]

64 [18]

68 [16]60 [17]

90 [19]

43 [14]

50 [15]

Year

31 [13]

PN

1 M

Hz o

ffset

(dBc

Hz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010


20 40 60 80 100 120 140minus200

minus190

minus180

minus170

minus160

minus150

minus140

[9]

[21][11]

[11]

[22]

[19]

[24]

[17][7]

[6]

[16][18][10]

[10][15]

[23]

[14]

[13]

[20]

[20]

FOM

(dBc

Hz)

Frequency (GHz)

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010





minus200

minus190

minus180

minus170

minus160

minus150

minus140

FOM

(dBc

Hz)

Year2000 2002 2004 2006 2008 2010 2012

64 [18]

68 [16]90 [24]

60 [17][6]

57 [7]50[10]60[10]104 [11]121 [11]

65[20][23]

34 [20]

114

[22]114

[9]

131[21]

43 [14]

31 [13]

50 [15]

30

57

90 [19]

LC 2011-2012RO 2011-2012RO 2001ndash2010

LC 2001ndash2010




4 Conclusions



References




































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References

























































1 Introduction









3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References




























3432 3960 4488 5016 5544 6072 6600 7128 7656 8184 8712 9240 9768 10296(MHz)

119891


119862119900

1198621

1198722

1198711

1198771198922

1198721

1198811198872

RFin

1198711198922







of 1198721is 119885in = 11198921198981 where

1198921198981



119891BW =1

21205871198621198921199041(11198921198981)

=

1198921198981

21205871198621198921199041

(1)


11987211987811198721198782








2119886and119872


is OFF 1198991and 119899




1





1and 119872

2 1198621is













1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























1198721

1198721198782 1198721198781

11986211198871198621119886

1198722119887 11987221198861198711198922119887 1198711198922119886

1198811198872

11988111987811198811198782

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

Block-1

Block-2

Block-3

1198771198892

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

119881119863119863

(a)

1198721

1198721198782 1198721198781

1198621119887 1198621119886

11987221198871198722119886

1198711198922119887 1198711198922119886

1198811198872

1198811198871

RFin

119871119878

11987111988811198711198882

11987711989221198861198771198922119887

1198811198872

11989911198992

1198711198892

119871out119862out

RFout

119862119900119886119862119900119887

1198811198782 = 0 1198811198781 = 1

119868119889

1198771198892

119881119863119863

(b)


1198781ON and119872

1198782OFF

11987811




12between




119898= 11989211989811198921198982


2119886 1199031199002119886


and 1199031199001198781



1199001198782) Figure 4(d)




2 1198711198922






4 Conclusion



3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























3 35 4 45 5 55 6minus16

minus15

minus14

minus13

minus12

minus11

minus10

Frequency (GHz)

119878 11

(dB)

(a)

minus70

minus65

minus60

minus55

minus50

minus45

minus40

3 35 4 45 5 55 6Frequency (GHz)

119878 12

(dB)

(b)

4

6

8

10

12

14

16

18

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 21

(dB)

(c)

minus40

minus35

minus30

minus25

minus20

minus15

minus10

minus5

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)

119878 22

(dB)

(d)


12 (c) voltage


22


Tech CMOS BW (GHz) 119881119889119889

(V) 11987811(dB) 119878

22(dB) 119878


[7] 01328 33 46


64Slowast







4S




3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























3

35

4

45

5

55

6

65

7

NF

(dB)

1198721199041 ON1198721199042 ON1198721199041 and1198721199042 ON

3 35 4 45 5 55 6Frequency (GHz)



References




























1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References



































1 Introduction









NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References





























NTF synthesis




















0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























0

minus1

minus2

minus3

minus4

minus5

MSA

(dB)

14 16 18 2 22 24 26 28OBG

Optimal region

100

90

80

70

60

50

Max

SN

R (d

B)

SNR

MSA







a0 134a1 425a2 492a3 339a4 276b1 04c1 04c2 04c3 04c4 011198921

0111198922

029



41198624and opamp


01198624 11988611198624 11988621198624 and 119886

31198624along with 119862

4[7]






1198771=

1198812

in2

32119896119879119891119861lowast 3lowast2

2119861minus1(1)


1is





119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























119881in 1198871

1198921 1198922 1198860

1198861

1198862

1198863

1198864

DAC


NRZ

5-levelquantizer

119881[119896]+ ++

1

119904119879119904

1

119904119879119904

1

119904119879119904

1

119904119879119904

1198881

1198882 1198883 1198884


1198771

DAC1 DAC2

119881119870 119881119870

1198772

11986211198622

1198623

11987731198774

1198624

Toquantizer

minusminus

++

minus

+

minus

+

11988611198624

11988601198624

11988621198624

11988631198624

minus1minus1

minus1

minus1119881in

1198771198921 1198771198922









119904




0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























0minus20

minus40

minus60

minus80

minus100

minus120

minus140

minus160

minus180

minus200

(dBF

S)

105 106 107 108

Frequency (Hz)



0

10

20

30

40

50

60

70

SND

R


Amplitude (dBFS)

DR cong 70dB




5 Conclusion



Acknowledgments


References





















1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


































1 Introduction










RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References




























RingVCO

PFD

Divider

CP

LF

Pulser

1119873

119891inj (= 119891ref )

Δ119879

119891ref











Out

put p

ower

Charge-pump PLL

(1205960 = 119873 middot 120596inj )


1205960 minus 120596119871 1205960 1205960 + 120596119871



120596119871=

120596out2119876

sdot radic

119875inj119873

1198750

(1)




119875inj119873 prop 119860 sdot 119863

sin (120587119863 sdot 119873)

120587119863 sdot 119873

2

(2)



120596119871prop

120596inj

2119876

sdot|sin (120587119863 sdot 119873)|

radic1198750

(3)



119878ILO (120596)

= 119878REF119872 (120596) sdot1003816100381610038161003816119867LPF (119895120596)

1003816100381610038161003816

2+ 119878VCO (120596) sdot

1003816100381610038161003816119867HPF (119895120596)

1003816100381610038161003816

2

=1198722sdot 119878REF (120596) sdot

1

1+(120596120596119871)2+119878VCO (120596) sdot

(120596120596119871)2

1+(120596120596119871)2

(4)




119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References



























119881max

119881min

119879pw

119879inj1 119881inj1

1198790119881d1

119881d2

(a)

119881max

119881min

1198790119881d1

119881d2

119881inj2119879inj2

(b)


0= 119891inj) (b)



119871 the








119871wide


VCO1 VCO2


119881b1 119881b2





1


119878ILO1 (120596)

= 1198722

1sdot 119878REF (120596) sdot

1

1 + (1205961205961198711)2

+ 119878VCO1 (120596) sdot(1205961205961198711)2

1 + (1205961205961198711)2

(5)

where 1205961198711



119878ILO2 (120596)

= 1198722

2sdot 119878ILO1 (120596) sdot

1

1 + (1205961205961198712)2

+ 119878VCO2 (120596) sdot(1205961205961198712)2

1 + (1205961205961198712)2

(6)

asymp 1198722

2sdot

1

1 + (1205961205961198712)2sdot 119878ILO1 (120596) (7)


RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























RingVCO2

PFD

Divider2

CP

LF2Pulser

RingVCO1

PFD

Divider1

CP

LF1Pulser

RPLL MPLL

11198732

119891inj2Δ119879

11198731

119891ref

119891inj1(= 119891ref )Δ11987911198733

11198734



1198731

1198732

1198733

1198734

32 24 36 1 8 4 8



1198712(ie 120596 ≪ 120596





2= 36 119873

3= 1 and 119873

4=



119881inj

119881in

119881inb

119881outb

119881out

119881DD

119881b 119881bn

119881in

119881outb

(a)


119881b 119881bn 119881b 119881b119881b

119881b

119881bn

119881bn

119881bn

+

minus +

minus +

minus +

minus

119881DD0

119881inj

1198811 1198812

1198811b 1198812b

(b)






M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























M1

M2M3

M4 M6

M5M9

M10M8

M7

119881DD 119881DD 119881DD

119881out 119881out

Δ ov

Δ ov

Δ ov + 119881thn

Δ ov + 119881thn

Δ ov + 119881thn

2Δ ov + 119881thn


119881DN

119881DD119881DD119881DD119881DD

119881DD

119881DD

119881DD

119881DD

119868CP119868CP119881b

119868b

119881UP

119881UP

119881DN

119877

11986211198622





0 025 05 075 1

0

10

20


Out

put c

urre

nt (119868

b) (120583

A)

119881UP = 1V 119881DN = 0V119881UP = 0V 119881DN = 1V

119881UP = 1V 119881DN = 1V

119881UP = 0V 119881DN = 0V

minus10

minus20




Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























Ring VCO

004

5 mm

003 mm

(a)

MPLL

021

mm

038 mm

(b)





1=




1= 24 36)


1=



2is required to







1= 41 pF 119862

2= 1 pF) The







0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























0 02 04 06 08 16

7

8

9

10

11

12

Control voltage (V)

Out

put f

requ

ency

(GH

z)



Free-running VCO

300-MHz reference


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus1604 times 107








VCO wi inj (mea)



Phas

e noi

se (d

BcH

z)

103 104 105 106 107

minus40

minus80

minus120

minus140

minus60

minus100

4 times 107


Free-running VCO

300-MHz reference

PLL wo inj

4 times 107


Phas

e noi

se (d

BcH

z)

103 104 105 106 107

40

0

minus40

minus80

minus120

minus160









RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























RPLL

MPLL

021

mm

026

mm

012 mm

038 mm


Phas

e noi

se (d

BcH

z)

Wi inj

Wo inj

50-MHz reference


minus160

minus150

minus140

minus130

minus120

minus110

minus100

minus90

minus80





2 1198733 and 119873



2 1198733 and 119873








Wi 02-GHz inj

Wo inj

Wi 16-GHz inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




radic

119875spur120596inj

1198750

asymp

1205960


119875inj119873

119875osc=

120596119871

120596inj (8)








0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References




























0119891ref 119871 in-band [dBcHz] 119871

lowast





16-GHz inj (mea)

minus110

minus90

minus70

minus50

119891L = 28MHz (cal)119891L = 224MHz (cal)

Phas

e noi

se (d

BcH

z)




119871= 224MHz)



21198733 and119873

4are



Wi 200-MHz inj

Wo inj

minus60

minus70

minus80

minus90

minus100

minus110

minus120


Phas

e noi

se (d

BcH

z)

103 104 105 106 107 4 times 107




5 Conclusion



Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References


























Frequency (GHz)

Mea

sure

d sp

ectr

um (d

Bm)

0

72 7767

minus20

minus40

minus60

minus80

minus100

minus31 dBc

1R

1

(a)


Mea

sure

d sp

ectr

um (d

Bm)

0

minus20

minus40

minus60

minus80

minus100

minus27 dBc1

1R

(b)




Acknowledgments


References

























advanced rf and analog integrated circuits for fourth...

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