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ADVANCED DIGITAL IC ADVANCED DIGITAL IC DESIGN(SESSION 14)

ASIC Design Flow (I)

(General Concepts –

Layout Floorplanning –

Layout Clock Insertion)

The ASIC ApproachThe ASIC Approach2

Top Level ASIC Digital Design FlowTop Level ASIC Digital Design Flow3

RTL Design

Design Inception

RTL Design

Synthesis Macro Development

Place + Route

Physical Verification

Design Complete

RTL DesignRTL Design4

Design Function Digital ToolDesign Function Digital Tool

RTL Design Cadence NC VerilogM t G hi M d lSi

Design Inception Design Inception

RTL Design

Lint Checking(users discression)

Mentor Graphis ModelSim

Cadence Hal

FPGA Verification(users discression)

Code Coverage(users discression)

Xilinx ISE

Cadence ICT

Testbench Developement

Mixed Mode Simulation

Cadence NC VerilogMentor Graphics ModelSim

Cadence AMS Designer

Formal Verification

Agilent ADSMatlabSynthesisSystem Interface Simulation

Cadence Conformal

y

Synthesis + Macro Development

Synthesis + Macro Development

Synthesis + Macro DevelopmentSynthesis + Macro Development5

Design Function Digital ToolDesign Function Digital Tool

RTL RTL

Synthesis Synopsys DC Cadence RCMacro Generation Artisan

DFT Synopsys DFT CompilerCadence RCMacro Verification Mentor Graphics Calibre

Static Timing Analysis

Logical Equivalency

Synopsys PrimeTime

Cadence Conformal

Macro Rules Generation / Library Generation

Artisan/Cadence DFII

Verification Verification

Gate-Level Simulation Cadence NC VerilogMentor Graphics Modelsim

Place + Route Place + Route

Place + RoutePlace + Route6

Design Function Digital Tool

Floorplan

Design Function Digital Tool

Synthesis Synthesis

p

Macro Placement / Std Cell Placement

Placement-Based O ti i ti

Cadence Encounter

Optimization

Clock Tree Synthesis

Route

Static Timing

AnalysisSynopsys

Prime-Time

Route Cadence NanoRoute

ATPG Mentor Graphics FastScan

Spare Cells / Decoupling Cap Filler Cells Cadence Encounter

RC Extraction

Signal Integrity

Cadence Fire&Ice QX

Cadence CeltIC / Voltage Storm

Verification Verification

Cadence EncounterMetal Fill

Physical VerificationPhysical Verification7

Design Function Digital ToolDesign Function Digital Tool

Placed + Routed Design

Placed + Routed Design

GDSII Preparation / Schematic Preparation

Simulation Preparation Cadence DFII Cadence DFII

DRC

Back Annotated SimulationLayout Chip Finishing Cadence NC VerilogCadence Virtuoso

LVS Mentor Graphics Calibre

ERC

Top-Level Simulation Synopsys NanosimCadence AMS Designer

Design Complete Design Complete

Cadence AMS Designer

ASIC LayoutASIC Layout8

With a clean and optimized netlist, the user is ready to transfer the design to its physical form, using the layout tool.Although, layout is a complex process, it can be g , y p p ,condensed to three basic steps:

FloorplanningFloorplanningClock tree insertionRo ting the databaseRouting the database

FloorplanningFloorplanning9

Thi i id d t b th t iti l t ithi th ti l t This is considered to be the most critical step within the entire layout process. Primarily a design is floorplanned in order to achieve minimum possible area, while still meeting timing requirements. Also, floorplanning is performed to divide the design into manageable blocks.In a broad sense, floorplanning consists of placement of cells and macros (e.g., RAMs and ROMs or sub-blocks) in their proper locations. The objective is to reduce net RC delays and routing capacitances, there by producing faster designs. Placing cells and macros in proper locations also helps produce minimum area and decrease routing macros in proper locations also helps produce minimum area and decrease routing congestion.Almost all designs undergo the floorplanning phase, and time should be spent trying to find the correct placement location of the cells. Optimal placement improves the

ll lit f th d i It l h l i d d th i l t it tioverall quality of the design. It also helps in reduced synthesis-layout iterations.For small and/or slow designs the floorplanning may not be as important, as that for large and/or timing critical designs consisting of thousands of gates (>150K). For these designs, it is recommended that a hierarchical placement and routing of the these designs, it is recommended that a hierarchical placement and routing of the design be performed. For example, a sub-block has been placed and routed, meeting all timing and area requirements. The sub-block is subsequently brought in as a fixed macro inside the full design, to be routed with the rest of the cells or macros.macros.

Clock Tree InsertionClock Tree Insertion10

It i ti l t t l th l k l t d k Alth h d i It is essential to control the clock latency and skew. Although, some designs may actually take advantage of the positive skew to reduce power, most designs however, require minimal clock skew and clock latency. Larger values of clock skew cause race conditions that increase the chance of wrong data being clocked in the fl C t lli th k d l t i l t f ff t d f i htflops. Controlling the skew and latency requires a lot of effort and foresight.The layout tool performs the clock tree synthesis. The CTS is performed immediately after the placement of the cells, and before routing these cells. With input from the designer, the layout tool determines the best placement and style of the clock tree.designer, the layout tool determines the best placement and style of the clock tree.Generally, designers are asked for the number of levels along with the types of buffers used for each level of the clock tree. Obviously, the number of levels is dependent on the fanout of the clock signal. In a broad sense, the number of levels f th l k t i i l ti l t th d i t th f th t d i of the clock tree is inversely proportional to the drive strength of the gates used in

the clock tree. In other words, you will need more levels, if low drive strength gates are used, while the number of levels is reduced if high drive strength gates are used.

Clock DomainsClock Domains11

Most large scale ASICs, and systems built with these ASICs, have several synchronous clock domains connected by asynchronous communication channelsclock domains connected by asynchronous communication channels.

We’ll focus on a single synchronous clock domain.

Clock DistributionClock Distribution12

C ’ ll d b l k ll flCan’t really distribute clock at same instant to all flip-flops on chip

Clock GridsClock Grids13

O h f l k i t i l t l l k id One approach for low skew is to use a single metal clock grid across whole chip.Low skew but very high power, no clock gating y g p , g g

H-TreesH Trees14

R i tt t di t ib t i l if l ith l d l Recursive pattern to distribute signals uniformly with equal delay over area.Uses much less power than grid, but has more skew In practice, an approximate H-tree is used at the top level (has to route around functional blocks), with local clock buffers driving regions

Skew SourcesSkew Sources15

Skew Sources and CuresSkew Sources and Cures16

S i k d f i i i Systematic skew due to manufacturing variation can be mostly trimmed out with adaptive deskewingcircuitrycircuitry

cross chip skews of <10ps reported Main sources of remaining skew are temperature g pchanges (low-frequency) and power supply noise (high frequency) P l i ff l k b ff d l d Power supply noise affects clock buffer delay and also frequency of PLL

often power for PLL is provided through separate pins often power for PLL is provided through separate pins clock buffers given large amounts of local on-chip decoupling capacitance

Skew versus JitterSkew versus Jitter17

Skew is spatial variation in clock arrival timesvariation in when the same clock edge is seen by two different flip-flops

Jitter is temporal variation in clock arrival timesvariation in when two successive clock edges are seen by the same flip-flop

Power supply noise is main source of jitterUse “skew” as shorthand for un-trimmable timing Use skew as shorthand for un trimmable timing uncertainty

Analog Circuit in a Digital IC:Clock Frequency Multiplication (Phase Locked Clock Frequency Multiplication (Phase Locked Loop)18