adaptive mirror control system

Midterm PresentationPerformed by: Boris Goychman & Eyal TsinInstructor: Tsachi Martsiano

Adaptive Mirror Control System

Semestrial project, Winter 2012

Background

*Joint project with physics faculty, deals with an adaptive mirror*The mirror changes Convexity in order to

correct distortions of light originated in the atmosphere*Such mirrors are used with telescopes

Projects Goals*Building a system that interface with a PC from one

end and control an adaptive mirror on the other end.*Adaptive Mirror – contains 126 capacitors to control the shape of the mirror

*Learn an approach for practical engineering.

*Get familiar with FPGA, Logic Design and board design basics.

Functional description

Sample & hold FPGA D/A USB

150 ns per channel

*non relevant50Mhz

460ns per channel (200%

margin)12Mbps

Data transfer rates

Up to 300V 3.3V 5V 3.3V Supply voltage

240mW 217mW 3mW 165mWPower consumption

D/AAdaptive Mirror

USBD/A

Sample & HoldFPGA

PC HostFPGA Interfaces

Scope

1. Simulation - modelsim

2. Emulation for each external

component

1. Emulation2. scope

1. Write to and read from initialization

registers (signal tap)2. Write to and read from RAM (memory

editor)

Test requirements

Specifications

System RatesFrom PC TO USB:128 8 1024

1024 8512transfer

bits

t SecM

From FPGA to D2A :126 channels (8 bit each)

126 460 sec 58 sectransfert n

From D2A TO Sample and Hold :Pipelined in the same time D/A works

From USB controller to FPGA's internal RAM :128 (16 bit parallel transfer)

64 1.2850transfer

bits

t SecM

85 1.28 57.96 144.42

144.42 1

Sec

Total Sec mSec

Development alternatives*Microprocessor*Philips provide software and drivers, easy to implement*Need to buy one + external RAM*Board design

*FPGA design*Predesigned board*Difficult to test and design with VHDL

*Choosing alternative USB control - FTDI*Simple interface*Slower rate (1Mbps)

Devised solutions*VHDL implementation*At least 5 FSM’s (1 ready 4 in work)

*D/A chip connected (works)*Only 1 Due to area, cost saving reasons

*FPGA implementation selected*Due to availability

*ISP1362 – USB controller*Used as a device*Initialized with PIO (only way)*Memory data transfer with DMA mode (faster way)

System usage & possible expansions*Control a 126 capacitor adaptive mirror*256 voltage values for each capacitor

*Same controller can be used to control any other system with the same requirements*126 inputs or less*256 values per input*1ms refresh rate

*The output of the D2A will pass through*a SAMPLE & HOLD (not in the scope of our project)*and then to the mirror (not in the scope of our project)

Philips USB

controller

Main State Machine

FPGA

D/Acontroller Memory

USBcontroller

DE2

General Block Diagram

GUI

USB

PC

D/A

( Sample and Hold )

General Block Diagram

FPGA

D/A

S&H

DE2PC

USB

GUI

[0..15]D

16

RD

WR

CS

0A

1A

2DACK

2DREQ

OTGMODE

ID

ISP

8

DATA

Control7

S&HS&HS&H

4DATA

Control6

FPGA

USB Controller D/A ControllerRAM

MAIN

D/A Controller

CSWR[7..0]DB0, 1A A

GAIN

LDACCLR

D/A Manager

FINISH

START

_ 2 _CLR DE DA

_ 2 _DATA DE DA

_ 2 _GAIN DE DA

_ 2 _ADDRESS DE DA

D/A Control BlockFPGA

State 0

State 1 State 2

State 3

State 5

State 6

State 4

WR_NOT<='1';CS_NOT<='1';LDAC_NOT<='1';

FINISH<='1';

CLR_NOT<='1';ENABLE<='0';

WR_NOT<='1';

CS_NOT<='0';

LDAC_NOT<='1';FINISH<='0';CLR_NOT<='1';ENABLE<='1';

WR_NOT<='0';

CS_NOT<='0';LDAC_NOT<='1';FINISH<='0';CLR_NOT<='1';ENABLE<='1';

WR_NOT<='0';CS_NOT<='0';

LDAC_NOT<='0';

FINISH<='0';CLR_NOT<='1';ENABLE<='1';

WR_NOT<='1';

CS_NOT<='0';LDAC_NOT<='0';FINISH<='0';CLR_NOT<='1';ENABLE<='1';

WR_NOT<='1';

CS_NOT<='1';LDAC_NOT<='1';

FINISH<='0';CLR_NOT<='1';ENABLE<='1';

WR_NOT<='1';CS_NOT<='1';LDAC_NOT<='1';FINISH<='0';CLR_NOT<='0';ENABLE<='0';

start

1t

6t

3 4 7 14max{ , , , }t t t t2 5 8 15max{ , , , }t t t t

13t

12t

_ 2 _ CLR DE DA OR RESET

State 7WR_NOT<='1';CS_NOT<='1';LDAC_NOT<='1';FINISH<='0';CLR_NOT<='0';ENABLE<='1';

1

6

12

13

3 4 7 14

2 5 8 15

:

6065 8080110 120

max{ , , , } 80max{ , , , } 65 80

The times

t nst ns nst nst ns ns

t t t t nst t t t ns ns






D/A state machine

State 00 '00001'

_ _ '1'_ '0 '_ "00000000"

_ "00"_ '0 '

_ '0 '

LEDreset tb notstart tbdata tbaddress tbgain tbclr tb

State 1a1 '00010 '

_ _ '1'_ '0 '_ "00000000"

_ "00"_ '0 '

_ '1'

LEDreset tb notstart tbdata tbaddress tbgain tb

clr tb

State 11 '00011'_ _ '1'_ '0 '_ "00000000"

_ "00"_ '0 '

_ '0 '

LEDreset tb notstart tbdata tbaddress tbgain tb

clr tb

State 2a2 '00100 '

_ _ '1'

_ '1'

_ "00110011"

_ "01"

_ '1'

_ '0 '

LEDreset tb not

start tb

data tb

address tb

gain tb

clr tb

State 22 '00101'

_ _ '1'

_ '0 '

_ "00110011"_ "01"

_ '1'_ '0 '

LEDreset tb not

start tb

data tbaddress tbgain tbclr tb

State 3a3 '01000 '_ _ '1'

_ '1'

_ "01010001"

_ "10"

_ '1'

_ '0 '

LEDreset tb not

start tb

data tb

address tb

gain tb

clr tb

State 33 '01001'_ _ '1'

_ '0 '

_ "01010001"_ "10"

_ '1'_ '0 '

LEDreset tb not

start tb


State 4a4 '10000 '_ _ '1'

_ '1'

_ "1001000"

_ "11"

_ '0 '

_ '0 '

LEDreset tb not

start tb

data tb

address tb

gain tb

clr tb

State 44 '10001'_ _ '1'

_ '0 '

_ "10010000"_ "11"

_ '0 '_ '0 '

LEDreset tb not

start tb


State R'11111'

_ _ '0 '

_ '0 '_ "00000000"

_ "00"_ '0 '

_ '0 '

LED

reset tb not

start tbdata tbaddress tbgain tbclr tb

KEY2

KEY0

KEY3

KEY1

SW0

FINISH

FINISHFINISH

FINISH

SW0

SW0

SW0

SW0SW0

SW0

SW0SW0

SW0

D/A emulation state machine

D/A Outputs – Theory VS Real Values

0 50 100 150 200 250 3000

1

2

3

4

5

6

f(x) = 0.0192251210330743 x − 0.0111559347440116R² = 0.999956139023875f(x) = 0.01953125 xR² = 1

Expected Vs. Acual Vout (Gain=0,Vref=5v)

Expected Vout(analog) [V] Linear (Expected Vout(analog) [V]) Actual Vout(analog) [V] Linear (Actual Vout(analog) [V])

Vin(dec)

Vout

(ana

log)

[v]

2out ref N

DV V Gain

Bin = 00110011Þ Dec = 51

Vth = (5*51*1)/256 = 0.996vVr = 0.977v

Bin = 0101001Þ Dec = 81

Vth = (5*81*1)/256 = 1.582vVr = 1.572v

Bin = 10010000Þ Dec = 144

Vth = (5*144*1)/256 = 2.812vVr = 2.796v

:5 , 8

2 /1 , dec(bin)ref

ConstV v N

Gain D

RESET

[0..15]D

16

RD

WR

CS

0A

1A

2DACK

2DREQ

OTGMODE

ID_MEM W

_ [11..0]MEM ADD

ISP 1363USB CONTROLLER

RAM

[0..15]Data

16

FINISH

START

MANAGER(main program)

USB controller Block Diagram

FPGA

I/O write/read single cycle

state machine

DMA write/read burst state machine

Look Up Table for

initialization process

Main USB controller – state machine

I/O counterDMA counter

Main counter

USB controller state machine

1

1[15..0]

1

10

_ :FINISH

RDDATA TBD

WR

CSA TBD

STATE idle

A Single Write Cycle A Single Write Cycle

0

1

[15..0] _ [15..0]

1

0

0

_ 1:FINISH

RD

DATA D IN

WR

CS

A ADDRESS

STATE W

_W START

0

1

[15..0] _ [15..0]

1

0

0

_ 3:FINISH

RD

DATA D IN

WR

CS

A ADDRESS

STATE W

AVWLt

max{ , }WLWH DVWHt t

max{ , , }WHAX WHSH WHDZt t t0

1[15..0]

1

10

_ 4 :FINISH

RDDATA TBD

WR

CSA TBD

STATE W

SHWLt

0

1

_ [15..0] [15..0]

1

0

0

_ 1:FINISH

RD

D OUT DATA

WR

CS

A ADDRESS

STATE R

0

0

_ [15..0] [15..0]

1

0

0

_ 2:FINISH

RD

D OUT DATA

WR

CS

A ADDRESS

STATE R

0

1

_ [15..0] [15..0]

1

0

0

_ 3:FINISH

RD

D OUT DATA

WR

CS

A ADDRESS

STATE R

0

1[15..0]

1

10

_ 4:FINISH

RDDATA TBD

WR

CSA TBD

STATE R

_R START

SHRLt

AVRLt

max{ , }RLDV RLRHt t

max{ , , }RHAX SHDZ RHSHt t t

Remarks : 1. A0 = ADDRESS = 1 / 02. A1 = 13. DATA = D = Address /

Data to be written / read

0

1[15..0] _ [15..0]

0

00

_ 2:FINISH

RDDATA D IN

WR

CSA ADDRESS

STATE W

A Single Initialization Cycle – PIO style

DcEndpointConfiguration

[15..0] [21]

0 1

D HEX

A


[15..0] [F3]

0 0

D HEX

A


[15..0] [22]

0 1

D HEX

A


[15..0] [24]

0 1

D HEX

A


[15..0] [F0]

0 0

D HEX

A


[15..0] [23]

0 1

D HEX

A


[15..0] [FF]

0 0

D HEX

A


[15..0] [F0]

0 0

D HEX

A


[15..0] [25]

0 1

D HEX

A


[15..0] [F0]

0 0

D HEX

A


[15..0] [26]

0 1

D HEX

A


[15..0] [F0]

0 0

D HEX

A


[15..0] [27]

0 1

D HEX

A


[15..0] [29]

0 1

D HEX

A


[15..0] [28]

0 1

D HEX

A


[15..0] [F0]

0 0

D HEX

A


[15..0] [F0]

0 0

D HEX

A


[15..0] [F0]

0 0

D HEX

A


[15..0] [2 ]

0 1

D HEX A

A


[15..0] [F0]

0 0

D HEX

A


[15..0] [2 ]

0 1

D HEX B

A


[15..0] [F0]

0 0

D HEX

A



[15..0] [20]

0 1

D HEX

A


[15..0] [ 3]

0 0

D HEX F

A

A Single Initialization Cycle – PIO style – Page2


[15..0] [2C]

0 1

D HEX

A


[15..0] [ 0]

0 0

D HEX F

A


[15..0] [2D]

0 1

D HEX

A


[15..0] [ 0]

0 0

D HEX F

A


[15..0] [2E]

0 1

D HEX

A


[15..0] [ 0]

0 0

D HEX F

A


[15..0] [2F]

0 1

D HEX

A


[15..0] [ 0]

0 0

D HEX F

A

DcAddress

DcAddress

[15..0] [ 6]

0 1

D HEX B

A

DcAddress

[15..0] [81]

0 0

D HEX

A

DcMode

DcMode

[15..0] [ 8]

0 1

D HEX B

A

DcMode

[15..0] [81]

0 0

D HEX

A

DcHardwareConfiguration


[15..0] [ ]

0 1

D HEX BA

A


[15..0] [3041]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

DcDMAConfiguration

[15..0] [C02B]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

[15..0] [C03B]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

[15..0] [C04B]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

[15..0] [C05B]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

A Single Initialization Cycle – PIO style – Page3

DcDMAConfiguration

[15..0] [C05B]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

[15..0] [C06B]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

[15..0] [C07B]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

[15..0] [C08B]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

[15..0] [C09B]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

[15..0] [C0AB]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

[15..0] [C0BB]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

[15..0] [C0CB]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

[15..0] [C0DB]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

[15..0] [C0EB]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMAConfiguration

[15..0] [C0FB]

0 0

D HEX

A

DcDMAConfiguration

[15..0] [ 0]

0 1

D HEX F

A

DcDMACounter

DcDMACunter

[15..0] [ 2]

0 0

D HEX F

A

DcDcDMACunter

[15..0] [4EC]

0 1

D HEX

A

√ Designed the entire system√ Connected the D\A component to the DE2√ Encoded the D\A controller and Simulated it in Quartus√ Emulated the D\A controller√ Read About the USB in general and about the ISP1362

In Particular√ Designed the USB’s FSMs√ Started to work on the encoding of the USB controller√ Started to work on the GUI

What we have done so far

Schedule

adaptive mirror control system

Documents

da state machine state

adaptive mirrorthe mirror

capacitorsame controller

usb controllerram

single write cyclea

less256 values

logic design

througha sample hold