AMC – Adaptive Mirror Controller

AMC – Adaptive Mirror Controller

Project supervised by: Project supervised by: Mony Orbach Mony Orbach

Project performed by:Project performed by:Koren Erez, Turgeman Tomer Koren Erez, Turgeman Tomer

Project supervised by: Project supervised by: Mony Orbach Mony Orbach

Project performed by:Project performed by:Koren Erez, Turgeman Tomer Koren Erez, Turgeman Tomer

Project duration – 1 yearProject duration – 1 year

IntroductionIntroductionIntroductionIntroduction

The project is a collaboration between The project is a collaboration between the Physic’s Adaptive Optics Labthe Physic’s Adaptive Optics Lab and and HS DSL.HS DSL.

Developing a system that controls Developing a system that controls adaptive mirrors, by changing the voltage adaptive mirrors, by changing the voltage of their capacitors (up to 124 capacitors).of their capacitors (up to 124 capacitors).

The Optical SystemThe Optical System

Signals & RatesSignals & Rates

Input:Input: A serial signal from the computer A serial signal from the computer

through a USB.through a USB.

Output:Output: 124 outlines of analog signal (0-295V).124 outlines of analog signal (0-295V).

Rate:Rate: The system will update all 124 outputs The system will update all 124 outputs

in 1mSec.in 1mSec.

External Flow ChartExternal Flow Chart

AMC

Optical Device Adaptive Mirror

USB

AMC

MMC

Internal Flow ChartInternal Flow Chart

USB

Adaptive Mirror

D/A

FPGA

USB Interface

Amp.

Amp.

Amp.

Amp.

8 Bit

12 Bit

The State The State Machine (SM)Machine (SM) Implemented as FSM within the FPGA.Implemented as FSM within the FPGA.

Main tasks:Main tasks:– Data flow controlling.Data flow controlling.– High Voltage Amplifiers power up/down High Voltage Amplifiers power up/down

sequence Controlling.sequence Controlling.– Carrying out a self test. Carrying out a self test. – FPGA-PC communication through the USB FPGA-PC communication through the USB

module.module.

Including a Watch Dog Timer (WDT) Including a Watch Dog Timer (WDT) feature for a PC-FPGA synchronization.feature for a PC-FPGA synchronization.

The State The State Machine (SM)Machine (SM)

System

Power

Down

DLP, FPGA Power

Up HVAmp Power

Up

MAIN

Self test

HVAmp Power Down

DLP ready!

HVAmps are powered on

OK/Error Massage

RUN Byte!

All capacitors were charged/ WDTR!

Shutdown Byte!

Power off AMC + USB cable disconnection!

Power on AMC + USB cable connection!

RUN

Self Test Byte!

Status Byte!

DLP to PC

Transmit

EOT EOT = End Of Transmission

WDTR = Watch Dog Timer Reset

DLP = USB Module

HVAmp = High Voltage Amplifier

The Control Bytes are marks in green

Testing The SystemTesting The System

The testing process composed of The testing process composed of separate checks for all of the system separate checks for all of the system modules.modules.

The modules are:The modules are:– The MMC card (HW & FW)The MMC card (HW & FW)– The amplification cardsThe amplification cards– The Wire-Wrap, containing:The Wire-Wrap, containing:

Bus-ExchangerBus-Exchanger LatchesLatches Switches and RelaySwitches and Relay Quad D/AQuad D/A ComparatorComparator

The MMC card (HW & FW)The MMC card (HW & FW)

Checking the HW:Checking the HW:– Programming the FPGA with a simple Programming the FPGA with a simple

program and sampling the FPGA’s pins program and sampling the FPGA’s pins and the transceiver’s inputs/outputsand the transceiver’s inputs/outputs

– Sampling the regulatorsSampling the regulators Checking the FW:Checking the FW:

– Comprehensive Test Bench was created in Comprehensive Test Bench was created in order to simulate the PC communicationorder to simulate the PC communication

– All the SM states were examinedAll the SM states were examined

The amplification cardsThe amplification cards

Two additional cards were made for this Two additional cards were made for this test. This cards contained:test. This cards contained:– Voltage switching capabilities for the power Voltage switching capabilities for the power

up/down sequenceup/down sequence– DIP Switch controlled address and EN signalsDIP Switch controlled address and EN signals– Analog signal, connected to a signal Analog signal, connected to a signal

generator.generator. A 5pF capacitor was connected to the A 5pF capacitor was connected to the

output of the tested amplifier, in order to output of the tested amplifier, in order to resemble the mirror capacitors. resemble the mirror capacitors.

The Wire-WrapThe Wire-Wrap

We added two headers on the We added two headers on the cards that were used to check the cards that were used to check the amplification capabilityamplification capability

This headers simulated logic This headers simulated logic inputs and control lines that could inputs and control lines that could be switched in order to examine be switched in order to examine the WW’s components the WW’s components

AMC SW InterfaceAMC SW Interface

C++ functions were written in C++ functions were written in order to communicate with the order to communicate with the AMC:AMC:

What we’ve learnWhat we’ve learn

HW practice:HW practice:– Reading datasheetsReading datasheets– Component selectionComponent selection– Wire WrapWire Wrap– Modular testingModular testing

FPGA Development flow:FPGA Development flow:– HDL Designer development environmentHDL Designer development environment– Logic & timing simulationLogic & timing simulation

Multidiscipline work:Multidiscipline work:– Customer: Physic’s Adaptive Optics LabCustomer: Physic’s Adaptive Optics Lab– Semi contractor: Supertex Semi contractor: Supertex – Soldering & Assembly with BruriaSoldering & Assembly with Bruria

Thanks for your supportThanks for your support!!

Erez & TomerErez & Tomer

HVAmp Power Up/DownHVAmp Power Up/Down

Improper power up/down sequence can Improper power up/down sequence can damage the HVAmps (High Voltage damage the HVAmps (High Voltage Amplifiers).Amplifiers).

Power up sequence:Power up sequence:

Vpp(300V)Vpp(300V)Vnn(-5.5V)Vnn(-5.5V)Vdd(6.5V)Vdd(6.5V)

Power down sequence:Power down sequence:

Vdd(6.5V) Vdd(6.5V) Vnn(-5.5V)Vnn(-5.5V)Vpp(300V)Vpp(300V)

HVAmp Power Up/DownHVAmp Power Up/Down

In order to control the Power up/down sequence, The In order to control the Power up/down sequence, The system includes Latch, Switches & Relay.system includes Latch, Switches & Relay.

The switches and the relay responsible on the physical The switches and the relay responsible on the physical connection between the power supplies and the connection between the power supplies and the HVAmps.HVAmps.

The power up/down control lines toggle the switches The power up/down control lines toggle the switches for the appropriate sequence.for the appropriate sequence.

The Latch locks the state of the switches when the The Latch locks the state of the switches when the system finished power up. This allows a reduction of system finished power up. This allows a reduction of control lines. control lines.

HVAmp Power Up/DownHVAmp Power Up/Down

DLP

(USB) Cyclone FPGA

Computer

Adaptive

Mirror

HV

Am

p

Bu

s

Exc

han

ge

Rel

ay

Tra

nsc

eive

rT

ran

scei

ver

Quad

Voltage

Output

D/A

Tra

nsc

eive

r

Sw

itch

es

Lat

ch

Power Up/Down Unit

HVAmp Power Supply

CLK EPCS ResetComparator

'1'

HV

Am

pH

VA

mp

HV

Am

p

Cyclone FPGA Adaptive

Mirror

HV

Am

p

Bu

s

Exc

han

ge

Rel

ay

Tra

nsc

eive

r

Sw

itch

es

Lat

ch

HVAmp Power Supply

HV

Am

pH

VA

mp

HV

Am

p

HVAmp Power Up/DownHVAmp Power Up/Down

The FPGA waits for a Control Sequence from The FPGA waits for a Control Sequence from the PCthe PC..

The Control Sequence composed of 3 bytes:The Control Sequence composed of 3 bytes:

According to The Control Byte the FPGA shifts According to The Control Byte the FPGA shifts to the next state:to the next state:• RUN Byte - updating all 124 outputs with the data received RUN Byte - updating all 124 outputs with the data received

from from the PC. the PC.• Self Test Byte - initiating a self test cycle. Self Test Byte - initiating a self test cycle. • Shutdown Byte - Power Down the High Voltage Amplifiers. Shutdown Byte - Power Down the High Voltage Amplifiers. • Status Byte - Status reporting to the PC.Status Byte - Status reporting to the PC.

The State Machine- The State Machine- MAIN StateMAIN State

0xFF0xFF 0x00 Control 0x00 Control ByteByte

Flag

Self TestSelf Test

The self test gives indication that:The self test gives indication that:– All components were powered up.All components were powered up.– All components are working All components are working

properly.properly.– Proper data flow.Proper data flow.

The FPGA sends the test’s result The FPGA sends the test’s result to the PC by the DLP module. to the PC by the DLP module.

Self TestSelf Test

DLP

(USB) Cyclone FPGA

Computer

Adaptive

Mirror

HV

Am

p

Bu

s

Exc

han

ge

Rel

ay

Tra

nsc

eive

rT

ran

scei

ver

Quad

Voltage

Output

D/A

Tra

nsc

eive

r

Sw

itch

es

Lat

ch

HVAmp Power Supply

CLK EPCS ResetComparator

'1'

HV

Am

pH

VA

mp

HV

Am

p

Self TestSelf Test

DLP

(USB) Cyclone FPGA

Computer

Adaptive

Mirror

HV

Am

p

Bu

s

Exc

han

geTra

nsc

eive

rT

ran

scei

ver

Quad

Voltage

Output

D/A

Tra

nsc

eive

r

Comparator

'1'

HV

Am

pH

VA

mp

HV

Am

p

Self Test – Self Test – Comparators SchemeComparators Scheme