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GLSVLSI 2003 Great Lakes Symposium on VLSI

April 28-29, 2003 Washington, DC

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Cover Page Table of Contents Author Index

Proceedings of the

2003 ACM Great LakesSymposium on VLSI

Radisson Barcelo HotelWashington, DC, USA

April 28-29, 2003

www.glsvlsi.org

GLSVLSI’03VLSI in the Nanometer Era

Sponsored by

withTechnical Support

from

GLSVLSI’032003 ACM Great Lakes Sym

posium on VLSI

GLSVLSI03-cover+spine.qxd 3/18/03 3:13 PM Page 1

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Foreword

Welcome to the 2003 edition of GLSVLSI, the conference still known as the Great Lakes Symposium on VLSI! Last year’s 12th edition was the first time when the symposium has moved significantly away from the Great Lakes area; with this year’s Washington, DC location this trend continues and reflects the transformation of GLSVLSI from its original regional roots into a national event. The motto for the 2003 edition can thus be: “Not a Great Lake, but a Great Location!” The theme for this year’s conference is “VLSI in the Nanometer Era”, which reflects the acceleration of technology from measuring silicon in microns to nanometers. This change permeates all aspects of our field, where the transistors and interconnect models are becoming even more complex, and current design methodologies struggle in building systems-on-a-chip (SOC) with hundreds of millions of transistors. GLSVLSI continues as a showcase of circuits, technologies and CAD research as we advance to the “Nanometer era.”

A main goal for the organizing committee has been to consolidate the symposium as a premier VLSI East Coast conference that can offer a balance to the many fine VLSI conferences located on the West Coast. In terms of attracting quality publications GLSVLSI has been extremely successful this year as the number of submissions received has almost doubled compared to last year! This has also put a lot of strain on the technical program committee and on the reviewers. It has also affected the acceptance rate as many outstanding papers could not be accepted due to lack of space. For next year we plan to have two parallel sections in order to address this issue, but this was not possible this year. Instead it was decided to expand the poster sessions and give posters more space in the proceedings. We received 136 high quality submissions in the six target areas for the conference: CAD, VLSI Circuits, VLSI Design, Low Power, Testing, and Nanotechnology. The submissions came from a mix of both academia and industry, with representation from 17 countries around the world! The overall acceptance rate was 51% with 17 full papers, 19 short papers, and 33 posters.

A “first” for GLSVLSI this year is the best paper award, which is intended to help even more with improving the quality of submissions. Congratulations to Chris Coulston for his paper “Constructing Exact Octagonal Steiner Minimal Trees” which was considered a seminal publication by the technical program committee. Chris will deliver the first presentation of the conference, the best paper becoming thus also the keynote presentation for GLSVLSI 2003! We hope to make this a tradition for GLSVLSI. Many thanks to technical program co-chair Kazuo Nakajima, finance chair Jim Aylor, publicity chair John Lach, local arrangements and registration chair Gang Qu, Donna Baglio and Maritza Nichols from ACM and to all members of the program committee.

Looking forward to seeing you again at GLSVLSI 2004 in Boston, MA!

Mircea Stan Dave Garrett GLSVLSI 2003 GLSVLSI 2003 General Chair Technical Program chair

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GLSVLSI 2004 Boston, MA

April 26-27, 2004

http://www.glsvlsi.org/ Sponsored by: ACM SIGDA

With the Technical Support of: IEEE CAS

The 2004 Great Lakes Symposium on VLSI (GLSVLSI) will be held on April 26-27, 2004 in Boston, Massachusetts. Original, unpublished papers, describing research in the general area of VLSI are solicited. Both theoretical and experimental research results are welcome. Proceedings will be published by the ACM and will be included on the SIGDA compendium CD-ROM.

Topics of Interest •VLSI Design: design of ASICs, microprocessors and micro-architectures, embedded processors, analog/digital/mixed-signal systems, multi-chip modules, FPGAs. •VLSI Circuits: analog/digital/mixed-signal circuits, RF and communication circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits. •Computer-Aided Design (CAD): hardware/software co-design, logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction, etc.), algorithms and complexity analysis. •Low Power Design: circuits, micro-architectural techniques, CAD support, power estimation methodologies and tools. •Testing, Reliability, Fault-Tolerance: digital/analog/mixed-signal testing, design for testability and reliability, online testing techniques, static and dynamic defect- and fault-recoverability. •Nanotechnology: emerging technologies (resonant tunneling devices, single electron transistors, quantum devices, molecular electronics, etc.), circuit design using nanotechnology devices, modeling and simulation tools for nanoelectronic devices and circuits.

Paper submission deadline: December 12th, 2003

Acceptance notification: February 13th, 2004

Camera ready paper due: February 27th, 2004

Paper Submission: Authors are invited to submit full-length (6 pages maximum), original, unpublished papers along with an abstract of at most 200 words. To enable blind review, the author list should be omitted from the main document. Previously published papers or papers submitted for publication to other conferences/journals will not be considered. Electronic submission in PDF format to the www.glsvlsi.org website is required. Author and contact information (name, street/mailing address, telephone, fax, e-mail) must be entered during the submission process.

Paper Format: To allow reduced turn-around time for accepted papers, GLSVLSI 2004 submissions should be in camera-ready two-column format, following the ACM proceedings specifications located at http://www.acm.org/sigs/pubs/proceed/template.html and the classification system detailed at http://www.acm.org/class/1998/

Symposium Presentations: Papers will be accepted for long, short, or poster presentation at the symposium.

Best Paper Award: A “Best Paper Award” will be voted on by the technical program committee and will be awarded during the symposium.

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Table of Contents

Foreword ................................................................................................................................................... iii

GLSVLSI 2004 Call for Papers ..........................................................................................................iv

Symposium Organization ....................................................................................................................x

Additional Reviewers...........................................................................................................................xii

Monday, April 28th

Welcome Address • 8:30 – 8:45 am

Session 1: CAD • 8:45 – 9:45 am Chair: Jagan Narasimhan s1.1 Constructing Exact Octagonal Steiner Minimal Trees (BEST PAPER WINNER) .........1

C. S. Coulston (Penn State Erie, USA) s1.2s Bounding the Efforts on Congestion Optimization for Physical Synthesis..................7

D. Pandini (STMicroelectronics, USA), L. T. Pileggi, A. J. Strojwas (Carnegie Mellon University, USA) s1.3s A Comprehensive High-level Synthesis System for Control-Flow Intensive

Behaviors .....................................................................................................................................11 W. Wang, T. K. Tan, J. Luo, Y. Fei, L. Shang, K. S. Vallerio, L. Zhong, N. K. Jha (Princeton University, USA), A. Raghunathan (NEC, USA)

Session 2: VLSI Circuits • 10:00 am – 12:00 noon Chair: Travis Blalock s2.1 Iterative Decoding In Analog CMOS ......................................................................................15

S. Hemati, A. H. Banihashemi (Carleton University, Canada) s2.2 Design Issues in Low-Voltage High-Speed Current-Mode Logic Buffers....................21

P. Heydari (University of California, USA) s2.3 Optimum Wire Sizing of RLC Interconnect With Repeaters............................................27

M. A. El-Moursy, E. G. Friedman (University of Rochester, USA) s2.4s Reduced Dynamic Swing Domino Logic..............................................................................33

R. Mader, I. Kourtev (University of Pittsburgh, USA) s2.5s A 5-20 GHz, Low Power FPGA Implemented by SiGe HBT BiCMOS Technology .....37

C. You, J.-R. Guo, R. P. Kraft, K. Zhou, M. Chu, J. F. McDonald (Rensselaer Polytechnic Institute, USA) s2.6s Interconnected Rings and Oscillators as Gigahertz Clock Distribution Nets ............41

M. S. Maza, M. L. Aranda (INAOE, Mexico)

Lunch • 12:00 noon – 1:15 pm

Session 3: Nanotechnology • 1:15 – 2:35 pm Chair: Azeez Bhavnagarwala s3.1 Information Storage Capacity of Crossbar Switching Networks ...................................45

P. P. Sotiriadis (John Hopkins University, USA) s3.2 Exploiting Multiple Functionality for Nano-Scale Reconfigurable Systems ...............50

P. Beckett (RMIT University, Australia)

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s3.3s A 0.07 µm CMOs Flash Analog-to-Digital Converter for High Speed and Low Voltage Applications ................................................................................................56 J. Yoo, K. Choi, J. Ghaznavi (Pennsylvania State University, USA)

s3.4s Modeling QCA for Area Minimization in Logic Synthesis................................................60 N. Gergel, S. Craft, J. Lach (University of Virginia, USA)

Poster Session 1 • 2:35 – 4:00 pm Chair : Ankur Srivastava p1.1 Power-aware Pipelined Multiplier Design Based On 2-Dimentional

Pipeline Gating............................................................................................................................64 J. Di, J. S. Yuan (University of Central Florida, USA)

p1.2 Low Power VLSI Sequential Circuit Architecture Using Critical Race Control ..........68 M. Lowy, N. Butler, R. Tinkler (BAE Systems, USA)

p1.3 A Hybrid Adiabatic Content Addressable Memory for Ultra Low-Power Applications ..........................................................................................................72 A. Natarajan, D. Jasinski, W. Burleson, R. Tessier (University of Massachusetts, Amherst, USA)

p1.4 TEM-Cell and Surface Scan to Identify the Electromagnetic Emission of Integrated Circuits.................................................................................................................76 T. Ostermann (University of Linz, Austria), B. Deutschmann (austriamicrosystems AG, Austria)

p1.5 MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits ................................................................................................80 R. Drechsler, J. Shi, G. Fey (University of Bremen, Germany)

p1.6 Cooling of Integrated Circuits Using Droplet-Based Microfluidics ...............................84 V. K. Pamula, K. Chakrabarty (Duke University, USA)

p1.7 Language Emptiness Checking using MDGs .....................................................................88 F. Wang, S. Tahar (Concordia University, Canada)

p1.8 A System-Level Methodology for Fast Multi-Objective Design Space Exploration ......................................................................................................................92 G. Palermo, C. Silvano, S. Valsecchi, V. Zaccaria (Politecnico di Milano, Italy)

p1.9 A Practical CAD Technique for Reducing Power/ground Noise in DSM Circuits......96 A. Mukherjee, K. R. Dusety, R. Sankaranarayan (The University of North Carolina at Charlotte, USA)

p1.10 RF CMOS Circuit Optimizing Procedure and Synthesis Tool.......................................100 C. Rajagopal, K. Sridhar, A. Nunez (Syracuse University, USA)

p1.11 Wirelength Reduction by Using Diagonal Wire ................................................................104 C. Chiang, Q. Su (Synopsys, Inc., USA), C.-S. Chiang (Soochow University, Taiwan)

p1.12 A Fast Simulation Approach for Inductive Effects of VLSI Interconnects ................108 X. Qi, G. Leonhardt, D. Flees, X.-D. Yang, S. Kim, S. Mueller, H. Mau (Sun Microsystems, Inc. USA), L. T. Pileggi (Carnegie Mellon University, USA)

p1.13 Buffer Sizing for Minimum Energy-Delay Product by Using an Approximating Polynomial...............................................................................................112 C. W. Kang, S. Abbaspour, M. Pedram (University of Southern California, USA)

p1.14 FORCE: A Fast and Easy-To-Implement Variable-Ordering Heuristic........................116 F. A. Aloul, I. L. Markov, K. A. Sakallah (University of Michigan, USA)

p1.15 Routing Methodology for Minimizing Interconnect Energy Dissipation....................120 A. Sakai, T. Yamada, Y. Matsushita (SANYO Electric Co., Ltd., Japan), H. Yasuura (Kyusyu University)

p1.16 Circuit Design of a Wide Tuning Range CMOS VCO with Automatic Amplitude Control ......................................................................................124 J. Chen, B. Shi (Tsinghua University, China)

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p1.17 A Decoupling Technique for CMOS Strong-Coupled Structures.................................128 L. Yang, J. S. Yuan (University of Central Florida, USA)

p1.18 A Custom FPGA for the Simulation of Gene Regulatory Networks ............................132 I. Tagkopoulos, C. Zukowski, G. Cavelier, D. Anastassiou (Columbia University, USA)

Session 4: VLSI Design • 4:00 – 6:00 pm Chair: Vijay Narayanan s4.1 A Novel Architecture for Power Maskable Arithmetic Units .........................................136

L. Benini (Università di Bologna), A. Macii, E. Macii (Politecnico di Torino, Italy), E. Omerbegovic (BullDAST s.r.l., Italy), M. Poncino (Università di Verona, Italy), F. Pro (BullDAST s.r.l., Italy)

s4.2 3D Direct Vertical Interconnect Microprocessors Test Vehicle ...................................141 J. Mayega, O. Erdogan, P. M. Belemjian, K. Zhou, J. F. McDonald, Russel P. Kraft (Rensselaer Polytechnic Institute, USA)

s4.3 Zero Overhead Watermaking Technique for FPGA Designs ........................................147 A. K. Jain, L. Yuan, P. R. Pari, G. Qu (University of Maryland, USA)

s4.4s Matrix Datapath Architecture for an Iterative 4x4 MIMO Noise Whitening Algoithm .................................................................................................................153 G. Knagge (University of Newcastle, Australia), D. Garrett, S. Venkatesan, C. Nicol (Lucent Technologies, Australia)

s4.5s System Level Design of Real Time Face Recognition Architecture Based on Composite PCA...................................................................................................................157 R. Gottumukkal, V. K. Asari (Old Dominion University)

s4.6s Design and Modeling of a 16-bit 1.5MSPS Successive Approximation ADC with Non-binary Capacitor Array..........................................................................................161 J. Gan (Cirrus Logic, Inc., USA), S. Yan, J. Abraham (University of Texas at Austin, USA)

Banquet • 6:00 pm

Tuesday, April 29th

Session 5: VLSI Circuits • 8:30 – 9:45 am Chair: Ruchir Puri s5.1 Shielding Effect of On-Chip Interconnect Inductance ....................................................165

M. A. El-Moursy, E. G. Friedman (University of Rochester, USA) s5.2 A Pipelined Clock-Delay Domino Carry-Lookahead Adder ...........................................171

B. A. Shinkre, J. E. Stine (Illinois Institute of Technology, USA) s5.3 A Globally Asynchronous Locally Dynamic System for ASICs and SoCs ................176

A. Chattopadhyay, Z. Zilic (McGill University, USA) s5.4s 40 MHz 0.25 µm CMOS Embedded 1T Bit-Line Decoupled DRAM FIFO

for Mixed-Signal Applications...............................................................................................182 M. I. Fuller, J. P. Mabry, J. A. Hossack, T. N. Blalock (University of Virginia, USA)

Session 6: CAD • 10:00 am – 12:00 noon Chair: Rhett Davis s6.1 Design Topology Aware Physical Metrics for Placement Analysis ............................186

S. Ramji, N. R. Dhanwada (IBM Microelectronics, USA) s6.2 A Novel Ultra-Fast Heuristic for VLSI CAD Steiner Trees ..............................................192

B. Krishna (Intel Corporation, USA), C. Y. R. Chen (Syracuse University, USA), N. K. Sehgal (Intel Corporation, USA)

viii

s6.3 Combining Wire Swapping and Spacing for Low-Power Deep-Submicron Buses..........................................................................................................198 E. Macii (Politecnico di Torino, Italy), M. Poncino (Università di Verona, Italy), S. Salerno (Politecnico di Torino, Italy)

s6.4s Clustering Based Acyclic Multi-way Partitioning.............................................................203 E. S. H. Wong, E. F. Y. Young (The Chinese University of H. K.), W. K. Mak (University of S. Florida, USA)

s6.5s Synthesis of Continuous-Time Filters and Analog to Digital Converters by Integrated Constraint Transformation, Floorplanning and Routing......................207 H. Tang, H. Zhang, A. Doboli (SUNY-Stony Brook, USA)

s6.6s Congestion Reduction in Traditional and New Routing Architectures ......................211 A. R. Agnihotri, P. H. Madden (State University of New York at Binghamton, USA)

Lunch • 12:00 noon – 1:15 pm

Session 7: Low Power • 1:15 – 2:15 pm Chair: Gang Qu s7.1 Simultaneous Peak and Average Power Minimization

during Datapath Scheduling for DSP Processors ...........................................................215 S. P. Mohanty, N. Ranganathan, S. K. Chappidi (University of South Florida, USA)

s7.2s Unification of Basic Retiming and Supply Voltage Scaling to Minimize Dynamic Power Consumption for Synchronous Digital Designs................................221 N. Chabini (Princeton University, USA), E. M. Aboulhamid (Université de Montréal, Canada), I. Chabini (Massachusetts Institute of Technology, USA), Y. Savaria (École Polytechnique de Montréal, Canada)

s7.3s Branch Prediction Techniques for Low-Power VLIW Processors...............................225 G. Palermo (Politecnico di Milano, Italy, STMicroelectronics, Italy), M. Sami, C. Silvano, V. Zaccaria (Politecnico di Milano, Italy), R. Zafalon (STMicroelectronics, Italy)

Poster Session 2 • 2:15 – 3:30 pm Chair: Mircea Stan p2.1 Orthogonal Code Generator for 3G Wireless Transceivers ..........................................229

B. D. Andreev, E. L. Titlebaum, E. G. Friedman (University of Rochester, USA) p2.2 54x54-bit Radix-4 Multiplier based on Modified Booth Algorithm...............................233

K. Cho, J. Park, J. Hong, G. Choi (Samsung Electronics Co., Korea) p2.3 Power-Time Flexible Architecture For GF(2k) Elliptic Curve Cryptosystem

Computation ..............................................................................................................................237 A. A.-A. Gutub, M. K. Ibrahim (King Fahd University of Petroleum and Minerals, Saudi Arabia)

p2.4 A Novel 32-bit Scalable Multiplier Architecture................................................................241 Y. Kolla (Sun Microsystems, Inc. USA), Y.-B. Kim (Northeastern University, USA), J. Carter (University of Utah, USA)

p2.5 High Throughout Overlapped Message Passing for Low Density Parity Check Codes .................................................................................................................245 Y. Chen, K. K. Parhi (University of Minnesota, USA)

p2.6 Exponential Split Accumulator for High-Speed Reduced Area Low-Power Direct Digital Frequency Synthesizers .........................................................249 E. Merlo, K-H. Baek, M. J. Choe (Rockwell Scientific Company, USA)

p2.7 Using Dynamic Domino Circuits in Self-Timed Systems...............................................253 J.-L. Yang, E. Brunvand (University of Utah, USA)

p2.8 Dynamic Single-rail Self-timed Logic Structures for Power Efficient Synchronous Pipelined Designs .........................................................................257 F. Grassert, D. Timmermann (University of Rostock, Germany)

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p2.9 Comparison of Noise Tolerant Precharge (NTP) to Conventional Feedback Keepers for Dynamic Logic................................................................................261 D. Harris, G. Breed, M. Erler, D. Diaz (Harvey Mudd College, USA)

p2.10 Variable Gain Amplifier with Offset Cancellation.............................................................265 A. Emira, E. Sánchez-Sinencio (Texas A&M University, USA)

p2.11 Repeater and Current-sensing Hybrid Circuits for On-chip Interconnects ..............269 A. Maheshwari, W. Burleson (University of Massachusetts, Amherst, USA)

p2.12 A Slew Rate Enhancement Technique for Operational Amplifiers based on a Tunable Active Gm-based Capacitance Multiplication Circuit ...............273 R. Suryanarayan, A. Gupta, T. N. Blalock (University of Virginia, USA)

p2.13 A Dual band CMOs VCO with a Balanced Duty Buffer ...................................................277 Y. C. Han (Samsung Electronics Co., Korea), K. Kim, J. Kim, K. S. Yoon, J. Chen, B. Shi (Inha University, Korea)

p2.14 New Approach to CMOS Current Reference with Very Low Temperature Coefficient .........................................................................................................281 J. Chen, B. Shi (Tsinghua University, China)

p2.15 Noise Tolerant Low Voltage XOR-XNOR for Fast Arithmetic........................................285 M. Elgamel, S. Goel, M. Bayoumi (University of Louisiana at Lafayette, USA)

Session 8: Testing • 3:30 – 4:45 pm Chair: John Lach s8.1 On Automatic Generation of RTL Validation Test Benches

Using Circuit Testing Techniques .......................................................................................289 I. Ghosh (Fujitsu Laboratories of America, USA), S. Ravi (NEC Laboratories of America, USA)

s8.2s A Highly Regular Multi-Phase Reseeding Technique for Scan-based BIST .............295 E. Kalligeros, X. Kavousianos (University of Patras, Greece), D. Nikolos (Computer Technology Institute, Greece)

s8.3s Coefficient-Based Parametric Faults Detection in Analog Circuits ............................299 Z. Guo (New Jersey Institute of Technology, USA)

s8.4s Mixing ATPG and Property Checking for Testing HW/SW Interfaces.........................303 A. Fin, F. Fummi, G. Pravadelli (University of Verona, Italy)

Closing Remarks • 4:45 – 5:00 pm

Author Index ..........................................................................................................................................307

x

GLSVLSI’03 Organization General Chair: Mircea Stan (University of Virginia)

Program Co-Chairs: David Garrett (Bell Labs Research, Lucent Technologies) Kazuo Nakajima (University of Maryland)

Steering Committee: Kaushik Roy (Purdue University) Naveed Sherwani (Intel Corporation) Vishwani Agrawal (Agere Systems) Kanad Ghose (SUNY Binghamton)

Finance Chair: James Aylor (University of Virginia)

Local Arrangements Chair: Gang Qu (University of Maryland)

Publications Chair: Hai Zhou (Northwestern University)

Publicity Chair: John Lach (University of Virginia)

Technical Program Committee:

CAD

Chuck Alpert (IBM) Kia Bazargan (University of Minnesota) Rhett Davis (North Carolina State) Patrick Groeneveld (Magma) Wen-Ben Jone (University of Cincinnati) Ryan Kastner (University of California at Santa Barbara) Cheng-Kok Koh (Purdue University) Sung Lim (Georgia Tech) Patrick Madden (SUNY Binghamton) Igor Markov (University of Michigan) Jagannathan Narashimhan (IBM) Zhigang Pan (IBM) Keshab Parhi (University of Minnesota) Ruchir Puri (IBM) Salil Raje (Monterey Design Systems) Sumit Roy (Calypto Design Systems) Gary Spivey (Rincon Research Corp) Ankur Srivastava (University of Maryland) Martin Wong (University of Illinois at Urbana Champaign)

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Technical Program Committee (continued)

Low Power

Kanad Ghose (SUNY Binghamton) Enrico Macii (Polytecnico di Torino) Diana Marculescu (Carnegie Mellon University) Radu Marculescu (Carnegie Mellon University) Vijay Narayanan (Pennsylvania State University) Gang Qu (University of Maryland) Victor Zyuban (IBM)

Nanotechnology

Eric Snow (Naval Research Laboratory) Chia-Hung Yang (University of Maryland) Nikolai Zhitenev (Bell Labs, Lucent Technologies)

Testing, Reliability & Fault Tolerance Ian Harris (University of Massachusetts) Niraj Jha (Princeton University) John Lach (University of Virginia) Shambhu Upadhay (SUNY Buffalo)

VLSI Circuits Nael Abu-Ghazaleh (SUNY Binghamton) Travis Blalock (University of Virginia) Olga Boric-Lubecke (University of Hawaii) Eby Friedman (University of Rochester) Roman Genov (University of Toronto) Neil Goldsman (University of Maryland) Timothy Horiuchi (University of Maryland) Kevin Kornegay (Cornell University) Ken Shepard (Columbia University) Mircea Stan (University of Virginia) Andre Van Scheke (Sydney University)

VLSI Design

Pradip Bose (IBM) David Garrett (Bell Labs, Lucent Technologies) Nihar Mahapatra (SUNY Buffalo) Stamatis Vassiliadis (TU Delft)

xii

Additional Reviewers: Boris Andreev Iosif Antochi Reinaldo Bergamaschi Mark Brehob Aiqun Cao Shih-Chieh Chang Yao-Wen Chang Guoqing Chen Dmitry Cheresiz Dan Crisu Anil Dalwani Azade Davoodi Dhananjay Dhole Monica Donno Magdy El-Moursy Jeroen Geuzebroek John Glossner Wenrui Gong Deepak Goyal Jingcao Hu Shaoxiong Hua Wei Huang Alessandro Ivaldi Geert Janssen Yunjian William Jiang Vishal Khandelwal Geoff Knagge Tianming Kong Mucahit Kozak Harish Kriplani Srivathsan Krishnamohan Volkan Kursun

Georgi Kuzmanov Casper Lageweg Kyoung Keun Lee Ying Ming Li Ruibing Lu Alberto Macii Rohit Mathur Andrey Mezhiba Jacob Minz Elena Moscu/Panainte Ketan Patel Massimo Poncino Mikhail Popovich Garrett Rose Youngsoo Shin Pun Hang Shiu Mihai Sima Kevin Skadron Xiaoyu Song Pyrrhos Stathis Krishnan Sundaresan Taku Uchino Girish Varatkar Dimitrios Velenis Chandramouli Visweswariah Qi Wang Yu-Liang Wu Weize Xu Lin Yuan Junmou Zhang Yan Zhang Matthew Ziegler

307

Author Index

Abbaspour, S. .................................................112 Aboulhamid, E. M. .........................................221 Abraham, J......................................................161 Agnihotri, A. R. ..............................................211 Aloul, F. A......................................................116 Anastassiou, D................................................132 Andreev, B. D.................................................229 Aranda, M. L. ...................................................41 Asari, V. K......................................................157 Baek, K.-H......................................................249 Banihashemi, A. H. ..........................................15 Bayoumi, M....................................................285 Beckett, P..........................................................50 Belemjian, P. M..............................................141 Benini, L.........................................................136 Blalock, T. N. .........................................182, 273 Breed, G. ........................................................261 Brunvand, E....................................................253 Bulter, N. ..........................................................68 Burleson, W..............................................72, 269 Carter, J. .........................................................241 Cavelier, G......................................................132 Chabini, I. .......................................................221 Chabini, N. .....................................................221 Chakrabarty, K. ................................................84 Chappidi, S. K. ...............................................215 Chattopadhyay, A. ..........................................176 Chen, C. Y. R. ................................................192 Chen, J. ...................................................124, 281 Chen, Y...........................................................245 Chiang, C........................................................104 Chiang, C.-S. ..................................................104 Cho, K. ...........................................................233 Choe, M.-J. .....................................................249 Choi, G. ..........................................................233 Choi, K. ............................................................56 Chu, M..............................................................37 Coulston, C. S.....................................................1 Craft, S. ............................................................60 Dreschsler, R.....................................................80 Deutschmann, B. ..............................................76 Dhanwada, N. R. ............................................186 Di, J. .................................................................64 Diaz, D. ..........................................................261 Doboli, A. .......................................................207 Dusety, K. R. ....................................................96 Elgamel, M. ....................................................285 El-Moursy, M. A. .....................................27, 165

Emira, A......................................................... 265 Erdogan, O. .................................................... 141 Erler, M.......................................................... 261 Fei, Y. .............................................................. 11 Fey, G. ............................................................. 80 Fin, A. ............................................................ 303 Flees, D. ......................................................... 108 Friedman, E. G................................. 27, 165, 229 Fuller, M. I. .................................................... 182 Fummi, F........................................................ 303 Gan, J. ............................................................ 161 Garrett, D. ...................................................... 153 Gergel, N.......................................................... 60 Ghaznavi, J....................................................... 56 Ghosh, I.......................................................... 289 Goel, S. .......................................................... 285 Gottumukkal, R.............................................. 157 Grassert, F...................................................... 257 Guo, J.-R. ......................................................... 37 Guo, Z. ........................................................... 299 Gupta, A......................................................... 273 Gutub, A. A.-A. ............................................. 237 Han, Y. C. ...................................................... 277 Harris, D. ....................................................... 261 Hemati, S. ........................................................ 15 Heydari, P. ....................................................... 21 Hong, J. .......................................................... 233 Hossack, J. A. ................................................ 182 Ibrahim, M. K. ............................................... 237 Jain, A. K. ...................................................... 147 Jasinski, D........................................................ 72 Jha, N. K. ......................................................... 11 Kalligeros, E. ................................................. 295 Kang, C. W. ................................................... 112 Kavousianos, X. ............................................. 295 Kim, J............................................................. 277 Kim, K. I. ....................................................... 277 Kim, S. ........................................................... 108 Kim, Y.-B. ..................................................... 241 Knagge, G. ..................................................... 153 Kolla, Y.......................................................... 241 Kourtev, I. ........................................................ 33 Kraft, R. P. ............................................... 37, 141 Krishna, B. ..................................................... 192 Lach, J.............................................................. 60 Leonhardt, G. ................................................. 108 Lowy, M. ......................................................... 68 Luo, J. .............................................................. 11

308

Mabry, J. P......................................................182 Macii, A..........................................................136 Macii, E. .................................................136, 198 Madden, P. H..................................................211 Mader, R...........................................................33 Maheshwari, A. ..............................................269 Mak, W. K. .....................................................203 Markóv, I. L....................................................116 Maza, M. S. ......................................................41 Matsushita, Y..................................................120 Mau, H............................................................108 Mayega, J........................................................141 McDonald, J. F. ........................................37, 141 Merlo, E..........................................................249 Mohanty, S. P. ................................................215 Moursy, E. M. A.......................................27, 165 Mueller, S. ......................................................108 Mukherjee, A....................................................96 Natarajan, A......................................................72 Nicol, C. .........................................................153 Nikolos, D. .....................................................295 Nunez, A.........................................................100 Omerbegovic, E..............................................136 Ostermann, T. ...................................................76 Palermo, G................................................92, 225 Pamula, V. K. ...................................................84 Pandini, D...........................................................7 Parhi, K. K......................................................245 Pari, P. R.........................................................147 Park, J. ............................................................233 Pedram, M. .....................................................112 Pileggi, L. T................................................7, 108 Poncino, M. ............................................136, 198 Pravadelli, G...................................................303 Pro, F. .............................................................136 Qi, X. ..............................................................108 Qu, G. .............................................................147 Raghunathan, A. ...............................................11 Rajagopal, C. ..................................................100 Ramji, S. .........................................................186 Ranganathan, N. .............................................215 Ravi, S. ...........................................................289 Sakai, A. .........................................................120 Sakallah, K. A. ...............................................116 Salerno, S........................................................198 Sami, M. .........................................................225 Sánchez-Sinencio, E. ......................................265 Sankaranarayan, R. ...........................................96

Savaria, Y. ..................................................... 221 Sehgal, N. K................................................... 192 Shang, L. .......................................................... 11 Shi, B. .................................................... 124, 281 Shi, J. ............................................................... 80 Shinkre, B. A. ................................................ 171 Silvano, C. ............................................... 92, 225 Sinencio, E. S................................................. 265 Sotiriadis, P. P.................................................. 45 Sridhar, K....................................................... 100 Stine, J. E. ...................................................... 171 Strojwas, A. J. .................................................... 7 Su, Q. ............................................................. 104 Suryanarayan, R............................................. 273 Tagkopoulos, I. .............................................. 132 Tahar, S............................................................ 88 Tan, T. K.......................................................... 11 Tang, H. ......................................................... 207 Tessier, R. ........................................................ 72 Timmermann, D............................................. 257 Tinkler, R. ........................................................ 68 Titlebaum, E. L. ............................................. 229 Vallerio, K. S. .................................................. 11 Valsecchi, S. .................................................... 92 Venkatesan, S................................................. 153 Wang, F............................................................ 88 Wang, W. ......................................................... 11 Wong, E. S. H. ............................................... 203 Yamada, T...................................................... 120 Yan, S. ........................................................... 161 Yang, J.-L. ..................................................... 253 Yang, L. ......................................................... 128 Yang, X.-D..................................................... 108 Yasuura, H. .................................................... 120 Yoo, J. .............................................................. 56 Yoon, K. S. .................................................... 277 You, C.............................................................. 37 Young, E. F. Y. .............................................. 203 Yuan, J. S. ................................................ 64, 128 Yuan, L. ......................................................... 147 Zaccaria, V............................................... 92, 225 Zafalon, R. ..................................................... 225 Zhang, H. ....................................................... 207 Zhong, L. ......................................................... 11 Zhou, K. ................................................... 37, 141 Zilic, Z. .......................................................... 176 Zukowski, C................................................... 132