1388 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 7, JULY 1995

TABLE I SOME PHYSICAL PROPERTIES OF MATERIALS USEO IN THE SIMULATION

Parameter Al Si02 Si-jN4 Si

Thermal conductivity 2.37 0.014 0.28 I .5

(W/cm.”C)

Specific heat (J/g.’C) 0.896 1 .oo 0.13 0.10

Density (g/cm3) 2.101 2.21 3.10 2.33

have, in general. a higher dielectric constant. As a consequence, cool- ing chips with such a dielectric may add line capacitance and reduce device speed. Nevertheless, passivation is an indispensable process for today’s VLSI devices, and the advantage of depositing dielectric materials with good thermal properties has clearly been demonstrated.

Some of the previous experimental data of line temperature mea- surements [4], [lo] differ evidently from each other. The accuracy attainable experimentally is a problem as transient temperature re- sponse to a short current pulse is very difficult to measure in practice. Moreover, the influence of electrical resistivity ( p ) could be a further reason responsible for the discrepancy between the present calculation on AI films and the data reported in [4], where a stack of AI-Si and Ti films were employed. AI alloy films generally have larger values of p , e.g., about 1.3-1.8 times of pure AI for Al-l%Si-l%Ti or AI-I%Ti films [ 111. Although the alloy addition is beneficial to improving the electromigration resistance [ I ] , the increase of p would enhance the Joule heat generation and reduce the maximum current density if the same Of is assumed. Finally, it is worthwhile to note that the curves shown in Fig. 2 represent the limits of the simulation. A fairly high current pulse even in the admissible region might result in a degradation long before a catastrophic failure of the metal line, and the damage position would most likely become a weak site prone to electromigration failure. Considering this possible relationship between instantaneous pulse damage and long-term electromigration failure, certain care must be taken when driving a high current pulse through a microcircuit.

IV. CONCLUSION

In summary, we have outlined some important features of transient temperature distributions in VLSI metallization structures, with the emphasis on the significant effects of dielectric passivation. The graphs of pulse width versus maximum current density through AI interconnects presented can be used as a design guideline for VPL- based FPGA and other VLSI devices.

REFERENCES

[ I ] P. S. Ho and T. Kwok, “Electromigration in metals,” Rep. frog. fhys., vol. 52. pp. 301-348, 1989.

[2] E. Hamdy er al., “Dielectric based antifuse for logic and memory ICs,” in IEDM Tech. Dig., 1988, pp. 786789.

[3] S. S. Cohen, J. I. Raffel, and P. W. Wyatt, “A novel double-metal structure for voltage-programmable links,” IEEE Electron Device Let?. , vol. 13, pp. 488490, 1992.

[4] J. E. Murguia and J. B. Bemstein, “Short-time failure of metal inter- connect caused by current pulses,” IEEE Elecrron Device Lett., vol. 14, pp. 481483, 1993.

[5 ] X. Gui, S. K. Dew, and M. J. Brett, “Three-dimensional thermal analysis of high density triple-level interconnection structures in very large scale integrated circuits,” J. Vac. Sci. Technol. B, vol. 12, pp. 59-62, 1994.

[6] X. Cui, P. W. Webb, and G. B. Gao, “Use of the three-dimensional TLM method in the thermal design and simulation of semiconductor devices,” IEEE Trans. Electron Devices, vol. 39, pp. 1295-1302, 1992.

171 X. Cui, P. W. Webb, and D. de Cogan, “An error parameter in TLM diffusion modelling,” Inr. J. Numer. Model., vol. 5 , pp. 129-137, 1992.

[8] P. W. Webb and X. Cui, “Implementation of timestep changes in transmission-line matrix diffusion modelling,” Int. J. Numer. Model.,

[9] K. Y. Kim and W. Sachse, “Dynamic fracture test of metal thin films deposited on an insulating substrate by a high current pulse method,” Thin Solid Films, vol. 205, pp. 176181, 1991.

[IO] T. Smy, D. J. Reny, and M. J. Brett, “Simulation of the effect of thin film microstructure on current and temperature distributions in very large scale integrated metallization structures,” J. Vac. Sci. Technol. B, vol.

[ 111 J. M. Towner, A. G. Dirks, and T. Tien, “Electromigrdtion in titanium doped aluminum alloys,” in Proc. 24rh Inf. Reliab. fhvs. Symp., 1986,

vol. 5 , pp. 251-257, 1992.

IO, pp. 2267-2276, 1992.

pp. 7-11.

A Simple Method to Extract the Asymmetry in Parasitic Source and Drain Resistances from Measurements on a MOS Transistor

A. Raychaudhuri, J. Kolk, M. J. Deen, and M. I. H. King

Abstract- For reasons related to layout, processing, or hot-carrier stressing, a MOSFET may have unequal source and drain parasitic resistances. In such cases, it is important to accurately extract the asym- metry in these resistances, without depending on individual judgments. In this brief, we present a simple method to extract this asymmetry. This method is based on an accurate formulation and measurement of the ac conductances with respect to the gate terminal of an MOS transistor in saturation.

I. INTRODUCTION For submicrometer MOSFET’s, the source and drain parasitic resis-

tances (Rs and RD, respectively) are large. As such, any asymmetry in their values arising out of layout, process, or electrical stressing shows up more clearly in their asymmetric drain currents when the roles of the source and the drain are interchanged. It is therefore important to accurately extract the asymmetry in R S and RD in order to properly understand layout faults, processing problems, or stress effects that affect source and drain sides differently. Also, it is preferable to do this extraction based on the measurements of a single transistor, because the asymmetry may vary from transistor to transistor. So far, we have not seen any paper that presents a direct and accurate method for the extraction of the difference between Rs and RD. Earlier papers in the area of extraction of R , and RD [l], (the methods reviewed in [2]), [3]-[5] assume that they are equal and go on to find their sum. Also, the papers [ 11, [2], and [3] discuss methods that depend on dc measurements on more than one transistor.

Manuscript received December 21, 1993; revised December 19, 1994. The

A. Raychaudhuri and J. Deen are with the School of Engineering Science,

J. Kolk and M. I. H. King are with Northem Telecom Ltd, Nepean, Ontario,

IEEE Log Number 9411417.

review of this brief was arranged by Associate Editor Y. Nishi.

Simon Fraser University, Bumaby, British Columbia, Canada V5A 156.

Canada K2H 8V4.

0018-9383/95$04.00 0 1995 IEEE

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 7, JULY 1995 1389

- Fig. 1. The MOSFET (n-channel) with source (Rs ) and drain ( R D ) series resistances. The applied voltages (ti 's and VDS) and the intrinsic voltage drops (I:?, \'As. and LgB) are also indicated.

In this paper, we present a direct and accurate method to find the difference between Rs and RD from the measurements of the dynamic transconductances in the saturation region of operation of a single MOSFET.

11. METHODOLOGY OF EXTRACTION For a MOSFET (see Fig. 1) with parasitic resistances R.7 and RD

associated with source and drain, respectively, we can show that the measured transconductance (g,) is given by

where gmorgdo, and gbO are the magnitudes of the intrinsic conduc- tances with respect to gate, drain, and substrate biases respectively. The above ( 1 ) represents correction to a similar equation derived in [6] to take care of the conductance ( g b O ) with respect to the substrate bias. The above equation neglects the variation of R.7 and Ru with T ~ s . But, in saturation, the channel pinch-off allows for this assumption to be valid.

Again, in saturation, as gclo is normally negligible compared to (gmo + gbo) the sum of Rs and RD as it occurs in the third term of the denominator of (1) has little effect on the measured g,. As such the measured value of gn2 is sensitive to only Rs. Now, if the source and drain are interchanged, the measured value of gm is sensitive to only RD. Hence any asymmetry in Rs and RD will show up in the measured gm and hence the IDS versus VGS characteristics in saturation measured normally, and again with the source and drain interchanged. We noted these saturation IDS versus I?;.? characteristics, as shown in Fig. 2, for an LDD NMOSFET of channel length 0.8 pm (as drawn) and channel width 24 pm. This MOSFET had asymmetric layout with the source side interconnection to the pad much longer than that on the drain side. The MOSFET measured had 175 A gate oxide, the LDD phosphorus implant dose was 2 x 10"' cmp2 at 40 keV, followed by a drive cycle at 900°C in a combination of dry 0 2 and N2 ambients for about 70 minutes. The MOSFET had salicided arsenic-implanted source/drain regions.

Now, if we intentionally add external resistances ( R,x- ) to the source side and measure the transconductance gm.r (measured straight, i.e., source and drain not interchanged), it should be given

2 a v

i; U

Fie. 2.

6 Vn,=S.OV

4

0 1 2 3 4 5

v,, (VI Saturation transconductance characteristics of the MOSFET with .,

VDS = 5 V. The asymmetry in R s and RD translates directly into these characteristics with sourcddrain as laid out and as interchanged.

(using ( 1 ) above) by

(2) Smo gmo

Again, if we intentionally add external resistances ( R ~ , ) to the drain side and measure the transconductance glnD (measured straight, i.e., source and drain not interchanged), it should be given (using (1) above) by

g m D gm0

+ ~ ( R . ~ + R D ) + R ~ QdO . (3) Smo Lymo J

If for different values of Rx , gm.y and g m D are measured in saruration for a constant current IDS, we can assume gmor g(i0. and gbO to be roughly constant because

where VA is the early voltage. Also

960 ff

where +F represents the Fermi potential corresponding to the sub- strate doping concentration. For small I D S , gbO represents a very slowly varying function of R x for low Rx(<lOOfI). The above assumptions are justified when we plot l/g,S and l l g , , , ~ (measured at a constant saturation IDS of 3 mA in our case) as in (2) and (3) versus Rx and obtain two straight lines with same intercept (-48012) as in Fig. 3. The slopes of these least-squares-fitted lines as obtained in Fig. 3 are given by

1 + QbO + E = 1.167 and - = 0.055. ( gmO gmo ) Smo

So that on subtracting the smaller slope from the larger one we get

1 + = = 1.112. gmO

(4)

If we now remove the external resistances ( Rx ) and measure at the same constant current (3 mA in our case) the forward (gm1) and reverse ( gmr ) saturation transconductances, Le., gn,f with source and

1390 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 42, NO. 7, JULY 1995

- 800 1 c_ 1

dope-1.167

slope-0.055 = 400 P M

i 200 NMOSFET, W-24 pm, L-0.8 pm 4 vm-5 v, vsn-o v

0 0 50 100 150 200

R, (n) Fig. 3. l/y,,.y and l/y,o measured at saturation I D S of 3 mA versus R.y . The straight lines through the p i n t s are least-squares fitted. gms is gm measured with R,y on source side and g , U is gm measured with R,y on drain side.

drain as connected, and gmr with source and drain interchanged, we can show using ( 1 ) above that

Substituting the value for 1 + gba/gmo from (4) into the denominator of (3, we obtained RD - Rs = -39 R. In fact all 24 pm x 0.8 pm devices with similar layout asymmetry between source and drain showed RD - R.5 between -30 and -40 0 using the above method. When this difference resistance was placed in series with the drain, the forward and reverse saturation transconductance characteristics matched exactly, confirming the accuracy of the extraction method.

111. CONCLUSION In conclusion, we have developed a direct and accurate method to

extract the asymmetry in the source and drain parasitic resistances of a MOSFET. This asymmetry can be caused by faulty layout, processing related problems, or hot-carrier stressings. The method is based on the measurement of dynamic transconductances of a MOSFET in saturation, and is based on a very generalized expression for the transconductance.

REFERENCES

P. I. Suciu and R. L. Johnston, “Experimental derivation of the source and drain resistance of MOS transistors,” IEEE Trans. Electmn Devices,

K. K. Ng and J. R. Brews, “Measuring the effective channel length of MOSFET’s.” IEEE Circuits and Devices Magazine, vol. 6, pp. 33-38, Nov. 1990. Z. P. Zuo, M. J. Deen, and J. Wang, “A new method for extracting short- channel length or narrow-channel width MOSFET linear parameters,” in Proc. Canadian Con$ Electrical and Computer Eng., Sept. 17-20,

S. T. Hsu. “A simple method to determine series resistance and h. factor of an MOS field effect transistor,” RCA Review, vol. 44, pp. 4 2 U 2 9 , 1983. B. Ricco, L. Selmi, and E. Sangiorgi, “A novel method to determine the source and drain resistances of individual MOSFET’s,” IEDM Technical Digest, pp. 122-125, 1988. S. Y. Chou and D. A. Antoniadis, “Relationship between measured and intrinsic transconductances of FET’s,” fEEE Trans. Elecrron Devices, vol. ED-34, pp. 448-450, 1987.

vol. ED-27, pp. 1846-1848, 1980.

1989, pp. 1038-1041.

Correction to “A Silicon Homojunction Infrared Detector Having an Active Metal Film on an N++ Layer”

Shigeru Tohyama, Akihito Tanabe, and Nobukazu Teranishi

Editor’s Note: Due to a production error, part of Section IV-A, beginning on page 1537 of the aforenoted paper’ was omitted in the September 1994 issue of the IEEE TRANSACTIONS ON ELECTRON DEVICES. Following is the corrected version.

A. Current- Voltage Characteristics

The current-voltage characteristics for the Type-M detector, mea- sured at 77 K, are shown in Fig. 6. Although the hot carrier emitter consists of a thinner n++ layer and a thinner PtSi film than those for the device described in Section 111, the I-V characteristics are seen to be quite diode-like. In addition, this means that an ohmic contact can be formed at the interface between the n++ layer and the PtSi film. The turn-on voltage is evaluated to be 93 mV.

Current density per square of absolute temperature. J/T2, versus reciprocal absolute temperature, I /T , for the Type-M detector has been examined, based on the J values measured at temperatures between 30 K and 100 K for bias voltage 1s values of -0.11 V, -0.85 V, and -6.00 V. As indicated later, these bias voltages are used to measure responsivity at 70 K, 50 K, and 30 K, respectively. The saturation current density is expressed as

J = A*T’exp( - a ~ / k T ) ( 1 )

where A* denotes a coefficient, which is equivalent to the effective Richardson constant, +B is the potential barrier height between the n++ layer and the banier layer, and kT is the thermal energy [7]. The characteristics for J / T 2 versus 1/T are shown in Fig. 7. In this figure, the characteristics for the Type-I11 detector are inserted. Open and closed symbols indicate the characteristic\ for the Type- M detector and for the Type-I11 detector, respectively. The plots fit straight lines very well. From the activation energies determined from the slope of (1) on a log-linear plot, the barrier heights for the Type-M detector are estimated to be 0.101 eV for S i , = -0.11 V, 6 . 5 9 ~ eV for 1iR = -0.85 V and 4.14 x lo-‘ eV for 1 . ~ = -6.00 V. These values correspond to cutoff wavelengths of 12.3 pm, 18.8 pm and 30.Opm, respectively. The Type-I11 detector has a 6.59 x lo-’ eV barrier height for VB = -0.62 V. Although the Type-M detector for VB = -0.85 V and the Type-I11 detector for IN = -0.62 V are equals in potential barrier height, the saturation current density of the Type-M detector is less than that of the Type-I11 detector. The extent of the reduction for the saturation current density may be estimated by examining the value of the coefficient -4’. For the Type- M detector, the d* value is 0.466A.cm-*.K-’ with 1 k = -0.85V. For the Type-I11 detector, the .-I* value is 4.34 A . cni-’ . K-’ with VB = -0.62 V. The saturation current density of the Type-M detector is estimated to be approximately one tenth the value for the Type- 111 detector, for the same barrier height. This shows that the reverse characteristics of the new detector have been greatly improved.

Manuscript received June 3, 1993; revised May 9, 1994. The review of this

The authors are with Microelectronics Research Laboratories, NEC Corpo-

IEEE Log Number 9403886. ‘S. Tohyama, A. Tanabe, and N. Teranishi, IEEE Trans. Elecrron Devices,

paper was arranged by Associate Editor W. F. Kosonocky.

ration, 1120, Shimokuzawa, Sagamihara, Kanagawa 229, Japan.

vol. 41, vol. 9, pp. 1535-1540, Sept. 1994.

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