a miniaturised wideband frequency synthesiser · 2010. 6. 9. · table 3.3: synthesiser efficiency...

A Miniaturised Wideband Frequency

Synthesiser

David Samuel Enchelmaier

Bachelor of Engineering (Aerospace/Avionics)

School of Engineering Systems

Submitted for the qualification of Master of Engineering

(Research) 2009

ii D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser

D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser iii

KEYWORDS

Broadband, electronics, frequency synthesiser, microwave, microwave circuit design,

microwave packaging, millimetre wave, wideband, phase locked loop, voltage

controlled oscillator, wideband

iv D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser

ABSTRACT

Wideband frequency synthesisers have application in many areas, including test

instrumentation and defence electronics. Miniaturisation of these devices provides

many advantages to system designers, particularly in applications where extra space

and weight are expensive.

The purpose of this project was to miniaturise a wideband frequency synthesiser and

package it for operation in several different environmental conditions while

satisfying demanding technical specifications. The four primary and secondary goals

to be achieved were:

1. an operating frequency range from low MHz to greater than 40 GHz, with

resolution better than 1 MHz,

2. typical RF output power of +10 dBm, with maximum DC supply of 15 W,

3. synthesiser package of only 150 100 30 mm, and

4. operating temperatures from -20C to +71C, and vibration levels over 7 grms.

This task was approached from multiple angles. Electrically, the system is designed

to have as few functional blocks as possible. Off-the-shelf components are used for

active functions instead of customised circuits. Mechanically, the synthesiser

package is designed for efficient use of the available space. Two identical prototype

synthesisers were manufactured to evaluate the design methodology and to show the

repeatability of the design.

Although further engineering development will improve the synthesiser’s

performance, this project has successfully demonstrated a level of miniaturisation

which sets a new benchmark for wideband synthesiser design. These synthesisers

will meet the demands for smaller, lighter wideband sources. Potential applications

include portable test equipment, radar and electronic surveillance systems on

unmanned aerial vehicles. They are also useful for reducing the overall weight and

power consumption of other systems, even if small dimensions are not essential.

D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser v

TABLE OF CONTENTS

Keywords .................................................................................................................... iii

Abstract ....................................................................................................................... iv

Table of Contents ......................................................................................................... v

List of Figures ............................................................................................................ vii

List of Tables ............................................................................................................... x

Abbreviations and Acronyms ...................................................................................... xi

List of Publications ................................................................................................... xiii

Statement of Original Authorship ............................................................................. xiv

Acknowledgements .................................................................................................... xv

CHAPTER 1: Introduction ...................................................................................... 1

1.1 Project Objectives and Design Criteria ........................................................ 1

1.2 Meeting the Challenge ................................................................................. 3

1.3 Thesis Structure and Overview .................................................................... 4

CHAPTER 2: Literature Review ............................................................................. 5

2.1 Literature Review ......................................................................................... 5

2.1.1 Synthesiser Design ............................................................................... 5

2.1.2 Oscillator Design ................................................................................ 10

2.1.3 Packaging and Integration Technology .............................................. 16

2.2 Product Review .......................................................................................... 17

2.2.1 Performance Comparison ................................................................... 18

2.2.2 Design Trade-Offs .............................................................................. 20

2.3 Review Summary ....................................................................................... 21

CHAPTER 3: System Design ................................................................................ 23

3.1 System Architecture ................................................................................... 23

3.1.1 Dual Oscillator Synthesiser Architecture ........................................... 25

3.2 System Design and Performance ............................................................... 27

3.2.1 PLL Synthesisers ................................................................................ 27

3.2.2 Low Frequency Extension ................................................................. 36

vi D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser

3.2.3 High Frequency Extension ................................................................. 38

3.2.4 Output Amplification and Level Control ........................................... 46

3.2.5 System Control ................................................................................... 48

3.3 System Design Conclusion ......................................................................... 56

CHAPTER 4: Packaging ....................................................................................... 59

4.1 Packaging Technologies ............................................................................. 59

4.1.1 Low Temperature Co-fired Ceramic .................................................. 60

4.1.2 Multilayer PTFE ................................................................................. 61

4.1.3 Microwave Supercomponents ............................................................ 62

4.2 Packaging the Synthesiser .......................................................................... 64

4.2.1 Efficiency ........................................................................................... 65

4.2.2 Performance ....................................................................................... 67

4.2.3 Manufacturability ............................................................................... 69

CHAPTER 5: Performance ................................................................................... 73

5.1 Test Equipment and Methods ..................................................................... 73

5.1.1 Frequency Sweep ............................................................................... 74

5.1.2 Settling Time ...................................................................................... 74

5.1.3 Phase Noise ........................................................................................ 75

5.2 Frequency Sweep Results and Discussion ................................................. 75

5.2.1 Output Power ...................................................................................... 76

5.2.2 Harmonics .......................................................................................... 79

5.2.3 Spurious Signals ................................................................................. 81

5.3 Settling Time Results and Discussion ........................................................ 84

5.4 Phase Noise Results and Discussion .......................................................... 87

5.5 DC Power Results and Discussion ............................................................. 89

5.6 Environmental Results and Discussions .................................................... 91

5.7 Summary of Synthesiser Performance ....................................................... 94

CHAPTER 6: Conclusion ...................................................................................... 95

Bibliography ............................................................................................................... 99

D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser vii

LIST OF FIGURES

Figure 2.1: Incoherent direct synthesis frequency synthesiser..................................... 6

Figure 2.2: Indirect frequency synthesiser using a phase locked loop ......................... 8

Figure 2.3: Direct digital synthesiser ........................................................................... 8

Figure 2.4: Comparison of the bandwidth of commercial synthesisers available from

various companies and the project goal ..................................................................... 18

Figure 2.5: Comparison of the phase noise of commercial products with the project

objective ..................................................................................................................... 20

Figure 3.1: A simplified block diagram of the Dual Oscillator Synthesiser [41] ...... 26

Figure 3.2: Recommended loop filter schematic [53] ................................................ 33

Figure 3.3: HMC587 tuning gain (sensitivity) [54] ................................................... 34

Figure 3.4: Loop bandwidth is more consistent with variable fCOMP than with fixed

fCOMP ........................................................................................................................... 35

Figure 3.5: A single prescaler stage ........................................................................... 36

Figure 3.6: A Microstrip to GCPW transition provides a top-side ground for GSG

wirebonding ............................................................................................................... 40

Figure 3.7: The Microstrip to GCPW transition has less than 0.25 dB loss at 100

GHz ............................................................................................................................ 40

Figure 3.8: A bandpass filter designed using a highpass filter structure ................... 42

Figure 3.9: Measured results confirm that the bandpass filter performance matches

the simulation ............................................................................................................. 42

Figure 3.10: The change in mixer output phase noise decreases as the difference

between input phase noise levels increases ................................................................ 44

Figure 3.11: Expected synthesiser phase noise .......................................................... 45

Figure 3.12: Level control in the output amplifier ensures consistent output power at

all frequencies ............................................................................................................ 48

Figure 3.13: The over-voltage protection circuit shields the synthesiser from

damaging input levels up to 32 V .............................................................................. 53

viii D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser

Figure 3.14: The supply sequencing circuit prevents damage to MMICs and FETs

when the negative supply is missing .......................................................................... 54

Figure 3.15: Bubble diagram of states in the FPGA state machine ........................... 57

Figure 4.1: 3D CAD sketch of the synthesiser, showing modules in four layers ...... 65

Figure 4.2: Cross-sectional view of the VCO/PLL module, showing layering of the

RF and DC circuits, and the use of pockets to accommodate taller DC components 66

Figure 4.3: Cross-sectional view of the Low Frequency module, showing that

pockets can also be used to accommodate taller RF components .............................. 67

Figure 4.4: The synthesiser backplane assemblies provide straightforward RF

interconnection between modules and protect the flexi-PCB DC interconnections .. 69

Figure 4.5: The VCO/PLL module incorporates many different technologies and is

designed to provide easy access to SOT components during manufacturing (image

digitally edited to remove commercially sensitive information) ................................ 70

Figure 4.6: The Low Frequency module incorporates many different technologies

and is designed to provide easy access to SOT components during manufacturing

(image digitally edited to remove commercially sensitive information) .................... 70

Figure 4.7: Cross-sectional view through the complete synthesiser assembly .......... 71

Figure 4.8: The finished synthesiser .......................................................................... 72

Figure 5.1: Spectrum analyser input cable insertion loss ........................................... 76

Figure 5.2: Fundamental output from the first synthesiser ........................................ 77

Figure 5.3: Fundamental output from the second synthesiser .................................... 77

Figure 5.4: The second synthesiser’s output at different operating temperatures ...... 78

Figure 5.5: Harmonic output from the first synthesiser at +25C .............................. 80

Figure 5.6: Harmonic output from the second synthesiser at +25C ......................... 80

Figure 5.7: Spurious output up to 30 GHz from the first synthesiser ........................ 82

Figure 5.8: Spurious output up to 30 GHz from the second synthesiser .................... 82

Figure 5.9: Measured synthesiser settling time, 74 samples, 250 sec bin size ........ 84

Figure 5.10: Synthesiser settling time ........................................................................ 85

Figure 5.11: Synthesiser settling time – a close up view of the effect of cycle slipping

.................................................................................................................................... 86

Figure 5.12: First synthesiser phase noise at 10 GHz ................................................ 87

Figure 5.13: Second synthesiser phase noise at 10 GHz ............................................ 88

D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser ix

Figure 5.14: The first synthesiser’s phase noise at 1.75 GHz has a clear peak ......... 89

Figure 5.15: The first synthesiser’s phase noise at 26.5 GHz has no discernible peak

.................................................................................................................................... 89

Figure 5.16: Harmonic rejection improves as the operating temperature increases .. 92

Figure 5.17: A typical random vibration profile for the synthesiser .......................... 93

x D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser

LIST OF TABLES

Table 1.1: Project objectives and design criteria .......................................................... 2

Table 2.1: Relative performance of key YTO and VCO parameters ......................... 11

Table 2.2: Comparison of specifications of commercial products with the project

objectives .................................................................................................................... 19

Table 3.1: Typical prescaler gain budget ................................................................... 37

Table 3.2: Typical spurious suppression (dBc) of Marki Microwave double-balanced

mixers [58] ................................................................................................................. 46

Table 3.3: Synthesiser efficiency varies according to output frequency .................... 51

Table 4.1: Relative performance of different packaging approaches ......................... 64

Table 5.1: Examples of spurious sources for fundamental frequencies up to 30 GHz

.................................................................................................................................... 83

Table 5.2: Synthesiser phase noise requirement at 10 GHz ....................................... 87

Table 5.3: Estimated and actual DC power consumption .......................................... 90

Table 5.4: The synthesiser’s phase noise at 10 GHz does not change significantly

with changes in temperature ....................................................................................... 93

Table 6.1: Comparison of commercial products’ specifications with the project

results ......................................................................................................................... 97

D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser xi

ABBREVIATIONS AND ACRONYMS

ADC Analog to Digital Converter

ALC Automatic Level Control

BGA Ball Grid Array

CAD Computer Aided Drafting

CPW Coplanar Waveguide

CSR Cycle Slip Reduction

DAC Digital to Analog Converter

DC Direct Current

DSM Delta-Sigma Modulator

EA Electronic Attack

ECL Emitter Coupled Logic

EMC Electromagnetic Compatibility

EMI Electromagnetic Interference

EW Electronic Warfare

ES Electronic Support

ESR Equivalent Series Resistance

FDTD Finite Differences Time Domain

FET Field Effect Transistor

FPGA Field Programmable Gate Array

FOM Figure of Merit

GCPW Grounded Coplanar Waveguide

GSG Ground Signal Ground

IC Integrated Circuit

IF Intermediate Frequency

LNA Low Noise Amplifier

LO Local Oscillator

LTCC Low Temperature Co-fired Ceramic

LUT Look-Up Table

xii D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser

LVPECL Low Voltage Positive Emitter Coupled Logic

MIC Microwave Integrated Circuit

MMIC Monolithic Microwave Integrated Circuit

MOSFET Metal Oxide Semiconductor Field Effect Transistor

PCB Printed Circuit Board

PFD Phase-Frequency Detector

PLCC Plastic Leaded Chip Carrier

PLL Phase Locked Loop

PQFP Plastic Quad Flat Pack

PTFE Polytetrafluroethylene (also referred to as Teflon)

RF Radio Frequency (also applies to microwaves)

RWR Radar Warning Receiver

SOC System On Chip

SOP System On Package

SOT Select-On-Test

SSS Suspended Stripline Substrate

TE Transverse Electric

TM Transverse Magnetic

TQFP Thin Quad Flat Pack

UAV Unmanned Aerial Vehicle

VCO Voltage Controlled Oscillator

VNA Vector Network Analyser

YIG Yttrium-Iron-Garnet

D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser xiii

LIST OF PUBLICATIONS

Enchelmaier, D., Tang, T., Robinson, A., Wideband Frequency Synthesisers –

Maximising Performance and Minimising Space, AOC International Symposium

2008, 26-27 May 2008.

xiv D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser

STATEMENT OF ORIGINAL

AUTHORSHIP

The work contained in this thesis has not been previously submitted to meet

requirements for an award at this or any other higher education institution. To the

best of my knowledge and belief, the thesis contains no material previously

published or written by another person except where due reference is made.

Date:

D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser xv

ACKNOWLEDGEMENTS

Microwave electronics manufacturing is a team effort and there are very few

occasions where a person can claim to have done something entirely on his own,

without any help or support. The completion of this thesis and the success of the

project behind it are evidence of this fact.

Thanks are due to my supervisor, Dr Tee Tang for his continual encouragement to

persevere, and also to my co-supervisors Dr Ashley Robinson (Micreo) and Dr John

Edwards. Ashley’s eye for detail and challenging questions were invaluable during

the design phase.

Thanks also to those who worked on the project with me. From the project sponsor,

thanks to Tony Moran, Michael Manka and Eugene Suchcicki for your oversight of

the project and for helping me to understand the bigger picture. To Dr Linh Nguyen,

Dr Brad Ferguson, and Angelo Sarti, thanks for your encouragement during all the

technical reviews as the project progressed. And thanks to all the Micreo staff who

put their time and effort into this project in engineering, purchasing, and

manufacturing.

Finally, thanks to my wife Petrina for all your loving support, and for bearing with

me so patiently when the synthesiser and this thesis seemed to be the only thing on

my mind.

xvi D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser

D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser 1

CHAPTER 1: INTRODUCTION

Like all areas of electronics, microwave circuits and systems are shrinking in

physical size. Much of the current focus for microwave circuits in the consumer

electronics area involves the development of circuits to support various wireless

communications applications such as mobile phones and wireless networking. The

common feature of these applications is the relatively low operating frequencies – up

to a few GHz – and the narrow relative bandwidth.

In fields such as test instrumentation, defence electronics and radio-astronomy, there

is a need to cover much higher frequencies and much wider bandwidths. There is

also a strong push for smaller, lighter and more cost-effective components,

particularly for applications where extra space and weight are expensive.

The purpose of this project was to develop a small, low-power frequency synthesiser

that also had wide bandwidth and high resolution. It had to be packaged to withstand

a wide operating temperature and a moderately high vibration level. A synthesiser

like this could be used in applications such as portable test equipment or light-weight

radar warning receivers (RWR), which could be installed on both manned and

unmanned aerial vehicles (UAVs).

1.1 PROJECT OBJECTIVES AND DESIGN CRITERIA

The primary objectives of the project were bandwidth and size. The target frequency

range started at low MHz values and covered a span of more than three decades, with

an upper frequency requirement greater than 40 GHz. The target package size for

this project was 150 100 30 mm, excluding connectors.

Secondary objectives of the project were frequency resolution and power

consumption. Frequency resolution was required to be better than 1 MHz. The

target maximum power consumption was 15 W.

Chapter 1: Introduction

2 D. Enchelmaier: A Miniaturised Wideband Frequency Synthesiser

As well as the four objectives stated above, the project had a range of other

performance goals, relating to RF output power, spurious signal levels, phase noise

levels, settling time, and environmental survivability. These goals are shown in

Table 1.1.

Table 1.1: Project objectives and design criteria

Requirement Specification

Frequency Range Low MHz to > 40 GHz

Frequency Resolution < 1 MHz

RF Output Power > +10 dBm

Output Harmonics < -20 dBc

Output Spurious < -50 dBc

Settling Time < 250 sec

Phase Noise at 10 GHz Offset (kHz) Level (dBc)

0.1 -60

1 -65

10 -70

100 -75

1000 -80

DC Power Consumption < 15 W

Operating Temperature -54C to +71C

Random Noise Vibration (Operating) 7.325 grms

Size 150 100 30 mm

Taken individually, none of these requirements are particularly challenging. As the

product review in Chapter 2 will demonstrate, each one has been met in a

commercially available synthesiser. The challenge of this project is in meeting all of

these requirements at once. For example, it is not difficult to find lower frequency

synthesisers with RF output levels greater than +10 dBm. However, developing an

amplifier to operate from low MHz frequencies to greater than 40 GHz is not a trivial

task. Developing an amplifier that does this with good DC power efficiency is even

more challenging.



Another example of the challenges in this project is the phase locked loop (PLL). A

PLL using a narrowband oscillator will typically have lower phase noise and a faster

settling time than one using a wideband oscillator. Covering the whole frequency

range would require multiple narrowband oscillators, multiple frequency multipliers,

and various filters – which in turn will require more space and more DC power.

1.2 MEETING THE CHALLENGE

A synthesiser which meets all of the parameters of Table 1.1 will, in some aspects at

least, be at the limit of what can be achieved with current technology. As an

industry-based project, it was also necessary to take into account the technical

competencies of the industry partner, Micreo Limited.

Micreo is a microwave and electro-optic design and manufacturing firm, specialising

in wideband microwave components and photonic links. To meet the challenge of

this design, the approach was to use a minimum number of wideband RF paths.

Commercial-off-the-shelf MMIC components were preferred over custom designed

hybrid MIC components wherever possible.

By using the same packaging and layout techniques which are common to current

Micreo products, the synthesiser will be physically robust and able to withstand a

wide range of different environmental conditions. In doing so, this project will

demonstrate how the required level of electrical performance can be achieved, not

only under ideal laboratory conditions, but in a real-world environment as well.

An industry-based project such as this has many contributors. The author was

responsible for the synthesiser system architecture, RF circuit design, the PLL active

filters and the voltage regulator circuits, layout for all DC and RF circuit boards, and

testing of the assembled prototypes. Package mechanical design and FPGA

programming were done by other engineers at Micreo, in close consultation with the



author. Assembly of the prototypes was done by Micreo’s manufacturing

department in a class 8 clean room under the author’s supervision.

1.3 THESIS STRUCTURE AND OVERVIEW

This thesis contains six chapters. Chapter 1, this chapter, is the introduction.

Chapter 2 is the literature review and product review. The literature review focuses

on three critical aspects of microwave technology and synthesiser design:

1. Synthesiser design, which considers the system level architecture and also

phase locked loop circuits – a critical aspect of most synthesisers.

2. Voltage controlled oscillator (VCO) design. More than almost any other

component, the VCO has a large effect on system performance.

3. Different packaging and integration technologies.

In the product review, a comparison was made of the advertised performance of

products aimed at two of the most demanding wideband markets: high performance

test equipment, and wideband military/aerospace equipment. The product review

also aimed to discover if any existing products could meet all of the performance

requirements of this project, and if not, what performance could be achieved.

Chapter 3 deals with the synthesiser system design. It describes the strengths and

weaknesses of several options proposed for this project, and the architecture that was

finally selected. The chosen architecture is then investigated in more detail.

Chapter 4 describes the physical packaging of the synthesiser. As for the system

design in Chapter 3, it describes the different packaging options that are available,

and the option that was finally chosen.

Chapter 5 describes the assembly and test of two prototype synthesisers.

Performance was measured at room temperature and under different environmental

conditions and evaluated relative to the design criteria presented in Chapter 1.

The conclusion of the thesis is presented in Chapter 6.


CHAPTER 2: LITERATURE REVIEW

The first section of this chapter presents a review of the academic research literature.

It focuses on three particular aspects of microwave technology: synthesiser design,

oscillator design, and packaging and integration technology. The second section is a

review of commercially available wideband synthesisers aimed at the test equipment

market and the military/aerospace market. Based on the key findings from the

review, this chapter concludes with several questions to be addressed by this project.

2.1 LITERATURE REVIEW

2.1.1 SYNTHESISER DESIGN

2.1.1.1 Fundamental Synthesiser Architectures

All microwave signal synthesisers, whatever the application, will use one or more of

three basic methods: direct synthesis, indirect synthesis or direct digital synthesis [1,

2].

Direct synthesis uses a combination of mixers, frequency multipliers, comb

generators and frequency dividers to generate the desired output signals. There is a

direct RF path from the reference input to the output. If the output is generated from

a single reference, it is referred to as a coherent synthesiser; if more than one

references are used, it is an incoherent synthesiser. A simple example of an

incoherent direct synthesiser using two comb generators and a mixer is shown in

Figure 2.1.

Chapter 2: Literature Review


Comb Generator

Switched Filter Bank


Output

Stable Reference Input f1

Stable Reference Input f2

Comb Generator


Figure 2.1: Incoherent direct synthesis frequency synthesiser

There are several characteristics of direct synthesisers that are worth noting. Fast

tuning is perhaps the most significant of these. The time taken to settle from one

frequency to another is only limited by the switching logic speed and the filter pulse

response [3].

The phase noise of a direct synthesiser output is dependant on the quality of the

reference signals. Comb generators, frequency multipliers and prescalers all affect

the phase noise by a factor of Nlog20 , where N is the multiplication ratio. In an

incoherent synthesiser, the typical phase noise output, fLSSB , of a mixer can be

approximated from manufacturer’s data as

1010 1010log10

fIFfLO

SSB fL , (2.1)

where f is the offset frequency in Hz,

fLO is the local oscillator phase noise in dBc/Hz, and

fIF is the IF input phase noise in dBc/Hz.

In a coherent synthesiser, where the same reference is used for both LO and IF

inputs, the log multiplication factor will be 20 instead of 10, ie

LO

IF RF



1010 1010log20

fIFfLO

coherentSSB fL . (2.2)

However, the direct synthesiser topology is not without drawbacks. If wideband

output frequencies and fine resolution are both required, the synthesiser will become

very complicated, requiring a large number of switches and filters. This in turn will

take up more space in the synthesiser.

Indirect synthesis uses many of the same components as direct synthesis, but with

one fundamental difference: it is a closed loop control system. Indirect synthesisers

rely on a phase locked loop (PLL) or frequency locked loop (FLL). As the names

suggest, both methods rely on locking the phase or frequency to a stable reference

source.

The PLL method dominates in both the literature and engineering practice. In a

PLL, the phase of the output signal VOUT is compared with the phase of the reference

input VREF. The loop is locked when both signals are in phase. It follows that in this

condition the frequencies will also be equal. If there is a difference between VOUT

and VREF, the phase detector creates an error signal. This error signal is used to

adjust the tuning voltage of the VCO in order to bring it back to the correct

frequency and a locked state.

In the situation described in the previous paragraph, the output is at the same

frequency as the reference, which raises the question: why go to the trouble of

designing and building a phase locked loop? If the loop is modified so that a

frequency divider with division ratio N is inserted into the feedback path, the VCO

can now be locked to a reference input that is N times lower in frequency. When the

divider is made programmable, as in most practical synthesisers, the loop can be

locked for multiple output frequencies. An example of this sort of synthesiser is

shown in Figure 2.2.



VCO

Programmable Divider

Loop Filter

Output

Phase Detector

Stable Reference Input

Figure 2.2: Indirect frequency synthesiser using a phase locked loop

Direct Digital Synthesisers (DDS), as the name suggests, are based on digital

circuits. A simplified DDS block diagram is shown in Figure 2.3. The DDS uses a

sine look-up table to convert phase sample information into digitised sine-wave

amplitude information. After digital to analogue conversion, the low-pass filter

eliminates the unwanted high frequency components of the signal, as well as other

spurious outputs.

Sine Look-up

Table

D-A Converter

Low-pass Filter Output

Phase Accumulator

Clock

Frequency Setting Data

Figure 2.3: Direct digital synthesiser

The Nyquist theorem requires two samples per cycle to reconstruct the output

waveform [4]. Consequently the maximum output frequency of the DDS is limited

to half the clock frequency. In practice it is limited to approximately 40% of the

clock frequency, in order to maintain reasonable low-pass filter requirements. A

consequence of this is that with current technology, DDS output frequencies are

limited to a few hundred megahertz. Direct synthesis components such as frequency

multipliers are required to achieve higher frequencies. However, direct digital

synthesisers have several advantages. Being digital, they are easier to interface with

microprocessors. Also, because they can be integrated onto a single chip, a DDS can



be packaged into a small PLCC or TQFP footprint. Frequency resolution in the DDS

is increased by simply increasing the number of input bits.

2.1.1.2 Wideband Synthesiser Architectures

Although much has been written about wideband components such as oscillators,

mixers, doublers and amplifiers, there is less in the open literature about wideband

synthesiser architectures which use these components. Many papers on synthesisers

focus on narrowband designs, or if they allude to wideband design, it is in the context

of wireless communications where 1 GHz is considered “wideband”, compared to

the multi-decade context of this project.

Egan [1] and Manassewitsch [2] both refer to wideband synthesisers, but do not

spend significant time on them. Prior to these, [5] is possibly the earliest paper to

directly address wideband synthesisers. This approach provides octave bandwidth

with 1 Hz resolution at 10 GHz. The bandwidth can be increased by adding more

octave bandwidth microwave oscillator modules. By using YIG tuned oscillators

(YTO), the synthesiser exhibits good spectral purity. However, the drawback of

using a YTO is that it has high DC power requirements. No attempt was made to

optimise its size; the synthesiser package is designed for a standard 19” rack.

More recently, in 1997 two very different wideband architectures were reported.

Madni et al. [6] miniaturised a classic direct synthesiser architecture with outputs

from 1 GHz to high Ku-band. High isolation (better than -80 dBc between channels)

and low phase noise were important requirements for this system. The design used a

modular approach, which helped to maintain the isolation requirement. The overall

package was 7.0 7.8 2.31 inches (117.8 198.1 58.6 mm), and had power

consumption of over 38 W in the worst case.

In contrast, Mondal et al. [7] integrated most of their 2-18 GHz synthesiser onto a

single MMIC (monolithic microwave integrated circuit), claiming 60-70% reduction

in volume and weight for the RF functions of the synthesiser. A supporting comb



generator and IF divider circuits took the overall size to 6.6 in3 (108 cm3), with

15-20 W DC power consumption. This does not include the size or power

requirements of the supporting control circuits, or the UHF synthesisers that provide

two essential input signals. To achieve such a high level of integration requires a

team of skilled MMIC designers and access to foundry services. One drawback of

this approach is that the reported wafer yield of 50%, although reasonable given the

density of integration, is too low to be commercially attractive.

To give an indication of relative sizes, Mondal’s highly integrated design has a

volume of approximately 108 cm3, excluding the control circuits and UHF

synthesisers as mentioned previously. Madni’s design has a volume greater than

2064 cm3, while the target volume for this project is 450 cm3.

Another approach is the double-PLL design [8]. In this synthesiser, 2-18 GHz with

100 kHz resolution is achieved by using a wideband YTO in the main PLL. An

auxiliary PLL provides a variable LO source for a sub-harmonic mixer. The mixer is

used to offset the YTO output to a lower frequency without frequency division,

which helps to maintain low phase noise. However, this synthesiser was not

packaged, but was left as brass-board bench-top modules.

2.1.2 OSCILLATOR DESIGN

Perhaps the most critical component in any type of synthesiser is the oscillator. The

performance of the oscillator will determine the performance of the system in terms

of various parameters. Most of the wideband synthesiser architectures discussed in

the previous section utilise PLLs; consequently the oscillator must be electronically

tuneable.

Electronically tuneable oscillators generally rely on one of two methods to control

the output frequency. The resonator in a YIG tuned oscillator (YTO) is a sphere of

Yttrium-Iron-Garnet. By controlling the current in one or more coils around the YIG

sphere, the magnetic field changes, which changes the sphere’s resonant frequency.

In varactor based voltage controlled oscillators (VCOs), the tuning element is a



varactor diode. By changing the varactor’s reverse bias voltage, the diode

capacitance changes and so does the circuit resonant frequency.

There are five key areas where the oscillator performance has a strong influence on

synthesiser performance. As will be discussed in the following sections, the relative

performance of YTO and VCO are clearly complimentary to one another. This is

summarised in Table 2.1.

Table 2.1: Relative performance of key YTO and VCO parameters

Parameter YIG Tuned

Oscillator

Voltage Controlled

Oscillator

Bandwidth Good Poor

Phase Noise Good Poor

Tuning Linearity Good Poor

Tuning Speed Poor Good

Power Consumption Poor Good

2.1.2.1 Bandwidth

YIG tuned oscillators set the benchmark for bandwidth. They can be tuned over

bandwidths greater than a decade. In 1989, Odyniec [9] reported on the design of a

3.8-30 GHz oscillator. Three years later, Khanna et al. [10] broke the decade barrier

with a 1.94-22.3 GHz single sphere oscillator.

Varactor tuned oscillators have somewhat restricted bandwidths by comparison. In

1966, Johnson [11] reported on octave and near-octave bandwidth oscillators in the

UHF and L bands. More recently, oscillators have been reported with bandwidths of

10-18 GHz [12] and 7.3-15.6 GHz [13].

Both of these oscillators highlighted the difficulty in achieving wide bandwidths with

varactors. The 10-18 GHz bandwidth could only be achieved by tuning both the



varactor and the gunn diode active element simultaneously. The 7.3-15.6 GHz

bandwidth required two varactors: one on the FET gate and one on the source. The

first direct comparison of YIG and varactor oscillators showed that with a single

tuning element and all other things equal between the two circuits, the varactor could

only achieve 30% bandwidth, compared with 80% for the YIG oscillator [14].

2.1.2.2 Phase Noise

Phase noise is a measure of an oscillator’s stability and is directly linked to the

quality factor Q. A very simple model of phase noise, showing the relationship

between noise, Q and offset frequency is given in Equation (2.3) [15].

2

0

2

2log10

QP

kTL

sig

, (2.3)

where L is the normalised single-sideband noise spectral density in dBc/Hz,

is the frequency offset in Hz,

0 is the carrier frequency in Hz,

k is Boltzmann’s constant,

T is the temperature in Kelvin, and

Psig is the oscillator signal level in dBm.

Although this is a good starting point, it fails to identify two key segments of real

phase noise measurements: the oscillator noise floor and the 31 f noise which is

found close to the carrier. The most widely used noise model is that proposed by

Leeson [16]. This model accounts for both of these physical characteristics, as

shown in Equation (2.4).

31

2

0 12

12

log10f

sig QP

FkTL , (2.4)

where F is the effective noise figure, and

31 f is the device 31 f corner frequency in Hz.



It is clear from these equations that higher Q results in lower phase noise. Both YIG

[5, 17] and varactors [18] have Q factors in the order of 2000-4000. The critical

difference is that for YIG spheres, this Q is measured at X band, whereas for

varactors the measurement is normalised to 50 MHz. As Equation (2.5) shows,

varactor Q is frequency dependent:

jsCfRQ

2

1 , (2.5)

where f is the frequency in Hz,

Rs is the varactor series resistance in Ohms, and

Cj is the varactor junction capacitance in Farads.

The impact of this at microwave frequencies is that the Q of a VCO will be

significantly lower than that of a YTO at the same frequency. Therefore the VCO

phase noise will also be correspondingly higher.

2.1.2.3 Tuning Linearity

Oscillator tuning linearity has most impact on the control circuits used to tune

frequency. In this area also, YIG oscillators are typically superior to VCOs because

the YTO is inherently linear [1]. The 1.94-22.3 GHz oscillator in [10] had a

measured tuning linearity of 0.25%.

Varactors however are inherently non-linear. A varactor diode is primarily

characterised according to the junction doping profile, which may be abrupt or

hyperabrupt. From the oscillator designer’s perspective, the main difference between

the two types is that the hyperabrupt diode leads to a more linear tuning response

than the abrupt diode.

The most linear wideband varactor performance was reported in [19]. In this case, a

FET VCO from 7-12 GHz and a BJT oscillator from 2-4 GHz were manufactured

and tested. The FET VCO had a maximum deviation of 0.2% at 10 GHz, with a

tuning range of 0-10 V. The BJT was tested in two configurations. In a single diode

configuration, the worst case deviation was 1.6% at 2.4 GHz. With a two diode



configuration, it was improved to 0.21%. A drawback of the BJT oscillator was the

required tuning range of 8.5-30 V. Although this level of performance appears to

exceed the linearity of the YTO, there is a problem in that the diode doping profile

was carefully calculated and controlled to match the requirements of the VCO – a

capability which most oscillator designers could not expect to have access to.

2.1.2.4 Tuning Speed

If an oscillator only requires high bandwidth, low noise and linear tuning, then a

YTO is clearly superior to a VCO. However, if tuning speed is also important, then

the designer is faced with a trade-off. Varactors are much faster to tune than YIG

resonators [2, 20]. This is due to the fact that YIG oscillators are tuned by changing

the current through one or more inductive coils. Because of the longer time constant

of inductors compared to varactors, the frequency changes more slowly. The typical

slew rate of a YTO is in the order of 1 ms/GHz [21]. Varactors on the other hand

have been reported with tuning speeds as fast as 600 MHz/ns [22]. To put this in

common units for comparison, a slew rate of 1 ms/GHz is equivalent to a tuning

speed of only 1 kHz/ns, which makes the YTO more than five orders of magnitude

slower than the varactor tuned oscillator. Although communication systems and test

equipment can often operate successfully at slow switching speeds, radar and EW

systems sometimes require much faster switching. In these applications, varactors

have a distinct advantage over YTOs.

2.1.2.5 Power Consumption

Power consumption is another parameter that is more important in radar and EW

systems than in communications and test equipment, and is one of the main criteria

of this research. Power consumption is another case where VCOs are superior to

YTOs. A large proportion of the power consumption of YTOs goes to generating the

magnetic bias field around the YIG resonator, particularly when generating higher

frequencies.

One solution for generating this field is to use permanent magnets (PM-YTO), but

this is not without problems [23]. Although material stability has improved over the



years, a more fundamental problem is the limited bandwidth that results from using a

PM-YTO. Electronically tuned, the bandwidth of these oscillators is limited to

approximately 4 GHz. Alternatively, the oscillator can be tuned by varying the air

gap between the YIG resonator and the permanent magnet. This allows the YTO to

achieve multi-octave bandwidths, though not the decade bandwidths achieved with

conventional electro-magnetic tuning. As well as lower bandwidth, another problem

is the fact that mechanical tuning is impractical in many environments, and is subject

to long-term reliability problems because of the number of moving parts involved.

2.1.2.6 Advanced Oscillator Methods

The basic theory and techniques for designing YIG and varactor oscillators is well

established. There are two techniques which have been developed over recent years

which are worth consideration in the context of this research: magnetostatic surface

waves and N-push oscillators.

The Magnetostatic Surface Wave (MSSW) resonator is essentially a planar

equivalent of the YIG sphere. It uses the same materials, but manufactured in thin

films, using the same sort of technologies as MMIC circuits. This is the primary

advantage and attraction of the MSSW – its planar nature results in a much smaller

device that can easily be integrated with other MMIC chips as part of a larger hybrid

microwave circuit. The bandwidth of an MSSW resonator is similar to YIG spheres,

as is its Q, which is in the order of 1000-2000 [24]. However, MSSW resonators

have the same drawbacks as YIG spheres: the bias field requires large magnets and

draws a lot of power [25]. A further drawback is that foundries for MSSW

manufacture are currently limited to research institutions.

The push-push oscillator was proposed by Pavio and Smith [26] as a means of

reducing phase noise in fixed frequency oscillators from 20-40 GHz. This was later

applied to frequency synthesisers [27] using a stepped-impedance split-ring resonator

(SISR) as the common resonant element, and then extended to a more generic

N-push concept [28]. Rohde [29] applied this to wideband VCOs, and showed that



the phase noise of an N-push oscillator is 1/N lower than the phase noise of a single

oscillator. As well as this phase noise advantage, N-push oscillators designed using

SISR coupling elements can have additional low-frequency outputs, which reduce or

even eliminate the need for prescalers, leading to reduced power consumption. The

drawback of N-push oscillators is that the phase interactions between oscillators

make the design more complicated than a single oscillator.

2.1.3 PACKAGING AND INTEGRATION TECHNOLOGY

There are many packaging techniques which offer miniaturisation advantages.

MMIC and low-temperature co-fired ceramic (LTCC) integration methods both have

the potential for substantial volume savings. However, both techniques can be very

costly to implement and, in a commercial manufacturing environment, are best suited

to proven designs which are tolerant of process variations and can be sold in

sufficient volumes to recoup development costs.

The synthesisers designed by Madni et al. [6] and Mondal et al. [7] have already

been discussed in Section 2.1.1.2 with respect to their architectures. These designs

also illuminate potential packaging methods for this work. Madni’s approach is to

use multiple subassemblies. The circuits are predominately microstrip, although

some filters are designed for coaxial combline and lumped element structures.

Subassemblies for GaAs FET and PIN diode circuits are hermetically sealed. This

approach is successful in meeting the high isolation requirements of that particular

work, but at the cost of large size and weight.

In contrast, Mondal’s approach is closer to the packaging style used for most

microwave supercomponents. In this case, a single housing is used for most of the

synthesiser, with isolation walls between the IF (intermediate frequency) divider

paths, the comb generator and their customised synthesiser chip. What this approach

fails to include is supporting DC circuits, and the fixed and variable UHF reference

sources.



Packaging of systems operating in the K and Ka bands is not a trivial exercise.

Drevon [30] demonstrated multi-chip-modules (MCMs) operating at 40 GHz, with

reliable hermetic packages suitable for space flight. As a mid-term development, he

pointed to the System-on-Package (SoP) technique. This is particularly suitable for

high frequency microwave circuits. Whereas a microprocessor or a low frequency

RF circuit could be manufactured entirely on a single technology such as CMOS,

high frequency circuits require a range of different technologies and

substrates: CMOS and bipolar for power supply and control circuits, through to

GaAs, InGaP or InP materials for millimetre-wave performance. In a similar vein,

Kato et al. [31] showed a one sixth size reduction using MCMs for a 30 GHz receiver

system. Menzel’s work [32] included a review of different materials used for

millimetre-wave packaging and interconnects, which highlighted some of the

difficulties unique to higher microwave and millimetre wave frequencies. Packages

need to protect the circuits from mechanical stresses, corrosive and other

contaminant particles, while transferring waste heat away from the semiconductors.

The package needs to be able to do this over a wide operating temperature range,

with reasonable process requirements and costs. For example, materials such as

kovar or tungsten, which have the best thermal expansion match to semiconductors

and ceramics, are expensive, difficult to machine, and have lower thermal

conductivity than copper alloys or aluminium.

Menzel also describes a method of connecting circuits using electromagnetic

coupling instead of physical connectors and feedthroughs. While this method avoids

some of the tolerance and performance problems found in standard interconnects at

high frequency, it has only been applied over narrow bandwidths, and is thus not

suitable for this project.

2.2 PRODUCT REVIEW

The purpose of this project is not only to determine what performance can be

achieved in a wideband synthesiser, but also to demonstrate a manufacturable

product. Consequently, it is important to review existing synthesiser products as



well as the academic literature. This review is in two sections – a comparison of

commercial products with the requirements of this specification and a discussion of

the trade-offs made in each product.

2.2.1 PERFORMANCE COMPARISON

Products for this review were selected from synthesisers openly advertised on

manufacturer websites, based on their similarity with the synthesiser requirements.

The primary selection criteria were bandwidth, size and operating temperature range.

As Figure 2.4 shows, the target bandwidth of low MHz to > 40 GHz is not widely

available in commercial products. The only products available with similar or

greater bandwidth are test equipment, like the Agilent E8257D [33] or the Rohde &

Schwarz SMR-60 [34] signal generators. A comprehensive search found several

companies capable of manufacturing wideband synthesisers with small outlines, but

as can be seen from the figure, none of them operate at frequencies above 24 GHz.

0 10 20 30 40 50 60 70

Project Objective

Rohde & Schwarz

Agilent

VIDA

MicroLambda Wireless

Trak Microwave

Crane Signal Technologies

Spectrum Microwave

Frequency (GHz)

Figure 2.4: Comparison of the bandwidth of commercial synthesisers available from

various companies and the project goal



Specifications for devices from Spectrum Microwave [35], Crane Signal

Technologies [36], Trak Microwave [37], Micro Lambda Wireless [38] and VIDA

Products [39] are compared with the project objectives in Table 2.2.

Table 2.2: Comparison of specifications of commercial products with the project

objectives

Parameter

Sp

ectr

um

Mic

row

ave

Cra

ne

Sig

nal

Tec

hn

olog

ies

Tra

k

Mic

row

ave

Mic

ro L

amb

da

Wir

eles

s

VID

A P

rod

uct

s

Pro

ject

Goa

l

Units

Model No. 310-027

007-002

6139-

6458-00

SYN111 MLSE-

0122

Hammer-

head

Frequency 0.4-18 2-18 2-18 1-22 11-24 Low MHz

to

> 40 GHz

GHz

RF Power +10 +13 +25 +17 +13 > +10 dBm

Speed 0.075 0.1 6 31 30 0.25 ms

Resolution 1 10 1 1 x 10-6 0.2 < 1 MHz

DC Power 10 30 52 41.5 9 15 W

Temperature 0 to +75 -40 to +85 -40 to +90 0 to +70 -10 to +70 -54 to +71 C

Dimensions 235

194.3

33

184.15

114.3

34

152.4

127

68.6

177.8

127

50.8

146

69.85

31

150

100

30

mm

The side-by-side comparison of Table 2.2 highlights the challenging nature of this

work. Although several of the commercial products shown here can out-perform the

project goals for one or more requirements, the combined requirements, and the

additional bandwidth and environmental requirements of this project, are beyond

what any of the existing products are capable of.

Section 2.1.2.2 highlighted phase noise as an important requirement in synthesisers.

Figure 2.5 shows graphically how the phase noise goal for this research compares

with commercially available synthesisers. Note that for this comparison, the phase



noise performance of the Spectrum Microwave synthesiser was excluded, and

performance from the Agilent synthesiser sweeper was added. This was done

because Spectrum Microwave only provided phase noise information at one offset

frequency, and also because the Agilent data is representative of what can be

achieved with test instrumentation.

-150

-140

-130

-120

-110

-100

-90

-80

-70

-60

-50

100 1,000 10,000 100,000 1,000,000

Offset Frequency (Hz)

Ph

ase

No

ise

Lev

el (

dB

c/H

z)

Crane Signal Technologies Trak Microwave MicroLambda Wireless VIDA Agilent Research Goal Figure 2.5: Comparison of the phase noise of commercial products with the project

objective

The phase noise comparison confirms the superior stability of YIG tuned oscillators

over voltage controlled oscillators. Both the Micro Lambda Wireless and Agilent

synthesisers have at least 11 dB less phase noise than the Crane Signal Technologies

synthesiser at 100 Hz offset. Although the VIDA Products synthesiser is not as good

at very close offsets, by 100 kHz it has surpassed all the other synthesisers. As

Figure 2.5 shows, the phase noise goal for this project falls between the two families

of commercial products.

2.2.2 DESIGN TRADE-OFFS

It is a common situation in product development that engineers must make trade-offs

between different parameters. The designer must determine which are more



important among issues such as technical performance, component cost and

manufacturability, and this in turn affects the final product cost. Of particular

interest in this case is the issue of technical performance; whether it is in fact

possible to meet all of the requirements or not. For the sake of this review, wideband

synthesisers will be broadly categorised as being for test and measurement

instrumentation, or being for radar and electronic warfare (EW) systems.

Test and measurement products come from manufacturers such as Agilent and Rohde

& Schwarz. As shown earlier, these products are unsurpassed in terms of bandwidth.

They also exhibit low phase noise, high resolution frequency setting and high

resolution amplitude setting. To achieve this level of performance, DC power

consumption and overall dimensions are sacrificed. Synthesisers for instrumentation

are designed to operate in a stable +25C environment, from 240 V, 60 Hz mains

power, in bench-top or 19” rack unit housings. This is exactly the opposite of an EW

system’s requirements, where the synthesiser may be required to handle temperature

extremes of -54C to +85C, high levels of shock and vibration, limited DC power

supply and limited space [40].

The remaining synthesisers from Table 2.1 can all be categorised as being for EW

systems. Bandwidths range between one octave and one decade and compared to

test and measurement systems, the power consumption requirements are much lower.

This comes at the expense of worse phase noise, larger frequency step sizes, and

fixed output amplitude. EW synthesisers have relatively small packages, particularly

those intended for airborne applications.

2.3 REVIEW SUMMARY

In this chapter various aspects of synthesiser design have been studied. The three

fundamental synthesiser topologies have been reviewed, as well as several examples

from the literature of wideband synthesisers. The review considered oscillator

design, and the relative merits and drawbacks of YIG and varactor tuned oscillators.

Magnetostatic-Surface Wave resonators and N-Push oscillators were addressed



briefly. The MSSW resonator was found to share the same drawbacks as other YIG

tuned oscillators, but with the advantage of planar design, making it more suitable for

integration with MMIC devices.

The cost of using custom MMIC or LTCC integration to reduce system size puts

these two methods beyond the scope of this project. However, the review has

identified multi-chip-module (MCM) and System-on-Package (SOP) as two methods

which have been successfully demonstrated at millimetre-wave frequencies, and still

offer suitable protection of the critical RF circuits in a small volume.

Finally, the objectives for this project were compared with performance

specifications of commercially available synthesisers. The comparison showed that

the objectives are realistic and, as a set of requirements, have not been met in any

single product previously.

From this review of the academic literature and commercial products there are

several questions that can be posed. First, what methods can be found to maximise

bandwidth in a given space? Second, what is a practical way to achieve greater than

40 GHz frequency range using less space and less power than the commercial

products use to cover 2-18 GHz? Implicit in the second question is a requirement

that the design must be manufactured using existing processes, and that it is rugged

enough to withstand environmental conditions more extreme than a laboratory

workbench. These questions will be addressed in this thesis.


CHAPTER 3: SYSTEM DESIGN

In Chapter 1, the stated purpose of this project was to develop a small, low power

frequency synthesiser that also had wide bandwidth and high resolution. In Chapter

2, this was refined to focus on two areas:

1. What methods can be found to maximise bandwidth in a given space?

2. What is a practical, manufacturable way to achieve greater than 40 GHz

frequency range using less space and less power than other commercial

products use to cover 2-18 GHz?

This chapter answers the above questions from the perspective of the electrical

system design. The system architecture is described, highlighting the expected

performance with respect to some of the key parameters identified in Table 1.1 of

Chapter 1. Detailed circuit level descriptions are included for some parts of the

synthesiser, when there is a close link between the circuit design and the synthesiser

performance.

3.1 SYSTEM ARCHITECTURE

The first driver of the system architecture was the goal of maximising performance,

particularly bandwidth, in the package outline specified by the customer. In

developing candidate architectures to meet this goal, the design philosophy was to

use as few components as possible and to capitalise on the processes and resources

available at Micreo Limited. The candidate architectures were thus based

exclusively on direct and indirect synthesis techniques; digital synthesis was not used

in any candidate architectures. The rationale for this decision was that the time

needed to design, prototype, and debug a DDS, and then incorporate it into the larger

system, would distract from the primary task of microwave circuit miniaturisation.

Although it has potential for high performance, the custom MMIC design approach

shown by Mondal [7] and discussed in Section 2.1.1.2 was not used either, because

Micreo Limited does not have the MMIC design experience or foundry access that

this approach requires.

Chapter 3: System Design


Several candidate architectures were considered before settling on the final system

architecture. They are briefly discussed here to provide context and comparison for

the final system architecture.

A block upconverter approach was considered, which has the advantage of being

relatively simple at the system level. One VCO is phase locked to a fixed frequency

and used to generate a comb of local oscillator tones, which are mixed with the

output of a second VCO to cover the whole frequency range. However, this

approach requires an octave bandwidth VCO, and a fourth order comb generator tone

at 50 GHz. The low frequency output is rich in high level harmonics and spurious,

which would require extensive filtering.

A dual upconverter architecture was proposed based on several existing products

manufactured at Micreo Limited. The advantage of this architecture, which uses two

stages of mixers to translate the VCO output across the entire synthesiser frequency

range, is that it allows a focus on system level synthesiser integration, rather than

circuit level design. However, it requires a 2-6 GHz VCO, which would be

challenging to design and integrate with a PLL. The dual upconverter approach will

also need extensive filtering to address the mixer spurious outputs.

A triple upconversion architecture addresses one shortcoming of the dual

upconverter architecture, by replacing the 2-6 GHz VCO with a narrower 4-6 GHz

VCO. Its drawback is its susceptibility to spurious regrowth. Spurious signals from

the first mixer stage will be converted back close to the fundamental output

frequency by the second and third mixer stage. The level of filtering required to

prevent these spurs close to the carrier would increase the synthesiser size and weight

beyond the limits set for this project.

The final architecture that was considered and rejected was a self-mixing oscillator

architecture. Frequencies above the VCO band could be generated by frequency

doubling, frequency tripling, or by mixing the output of the doubler and tripler

circuits. As well as the difficulties of an octave bandwidth VCO, the doubler and



tripler circuits must also function over an octave band. Furthermore, because the

mixer inputs are harmonics of the same fundamental tone, this architecture will also

require significant filtering.

3.1.1 DUAL OSCILLATOR SYNTHESISER ARCHITECTURE

The chosen architecture for this synthesiser is a dual oscillator approach. A

simplified block diagram is shown in Figure 3.1. The dual oscillator architecture is

similar to the self-mixing oscillator, but uses two VCOs, each of which has a

frequency range of around half an octave. The dual oscillator synthesiser is superior

for several reasons. The narrower frequency range simplifies the VCO requirements

and the frequency multiplier requirements. The dual oscillator synthesiser does not

require a frequency tripler, but uses two doublers, which will be easier to design over

the required bandwidth. Also, because the VCO frequencies are set independently,

there is an additional degree of freedom to set the mixer inputs so that high level

spurs are as far away from the output frequency as possible, which simplifies filter

requirements. The synthesiser uses a cascade of divide-by-two prescalers to generate

the low frequency outputs.

This architecture exploits several features of direct and indirect synthesis techniques.

The two VCOs are controlled by PLLs to get high resolution without requiring a

large number of filter stages. The PLL uses a fractional-N circuit which allows for

step sizes less than the PLL reference frequency. This has several advantages over

integer-N circuits which will be discussed further in Section 3.2.1.2.

Chapter 2 highlighted the extended frequency range as one of the benefits of direct

synthesis. The dual oscillator architecture uses this advantage in the prescaler

cascade, the frequency doublers, and the millimetre-wave mixer. If suitable

wideband components are used, the synthesiser’s operating frequency limits will

only be set by the VCO frequencies.



Figure 3.1: A simplified block diagram of the Dual Oscillator Synthesiser [41]



3.2 SYSTEM DESIGN AND PERFORMANCE

The following sections contain a more detailed description of the system design, and

the expected performance levels. There are five sections, which match the functional

blocks of the system: PLL synthesisers, low frequency extension, high frequency

extension, output amplification and level control, and finally, system control.

3.2.1 PLL SYNTHESISERS

The PLL synthesisers are the core of the system and strongly influence many aspects

of system performance such as frequency resolution, phase noise and settling time.

As stated previously, the two PLL synthesisers cover a combined frequency range of

just over one octave. The frequencies range from high C-band to low Ku-band. This

choice of frequency range comes after a series of design trade-offs.

In a direct synthesiser, phase noise increases with multiplication ratio N by a factor

of Nlog20 . The intrinsic noise of real devices means that a frequency doubler will

actually increase phase noise by more than 6 dB, while a divide-by-2 prescaler will

not reduce phase noise by the full theoretical 6 dB. Therefore, the PLL synthesiser

frequencies should be as high as possible in order to reach millimetre-wave

frequencies with only one or two direct synthesis stages. However, high frequency

VCOs are not readily available in MMIC form and at K-band are difficult to design

with sufficiently wide bandwidth. High frequency wideband VCOs also require high

frequency wideband prescalers. An informal survey of MMIC doublers and

prescalers found that frequency multipliers typically achieved higher output power

levels with greater efficiency than prescalers when operating at similar input

frequencies [42-45].

Low frequency VCOs with wide bandwidth can be sourced from several

manufacturers. They require fewer prescaler stages in the system. The prescalers

can be manufactured in technologies such as CMOS Silicon-on-Insulator (SOI)

which consume little DC power. However, they will require several multiplication



and mixing stages to reach millimetre-wave frequencies, all of which require filtering

and high level driver amplifiers, which consume a large amount of DC power.

By choosing a VCO frequency range of 7-16 GHz, the synthesiser can be extended to

millimetre wave frequencies with a single doubler stage, and can reach V-band with

a mixer. This part of the synthesiser will be discussed further in section 3.2.3.

3.2.1.1 PLL RF Feedback Path

The RF feedback path closes the loop between the VCO and the phase/frequency

detector (PFD) circuit of the PLL IC. A wideband 3 dB Wilkinson power divider

splits the VCO signal between the main RF path and the RF feedback path. Although

the maximum input frequency for PLL ICs continues to increase, reaching 7 GHz at

the time of writing, the best ICs available during the design of this synthesiser had

maximum input frequencies of around 3 GHz [46, 47]. Consequently several stages

of RF prescaler are required in the feedback path.

Since the intermediate frequencies generated in the feedback path must also be

available at the output, it is desirable to take a sample of these signals. This could be

done using a wideband coupler or power divider, such as the Wilkinson divider used

at the RF feedback path input in Figure 3.1. However, both the coupler and power

divider will take up some space in the synthesiser. One of the techniques for

reducing the overall size of the synthesiser is to minimise the component count.

Hittite Microwave Corporation has a range of prescaler MMICs with suitable RF

performance which are designed for use in either differential or single ended systems

[42, 43]. Both the output and complimentary output pins are active, even if the input

is only single ended. This feature is exploited and instead of terminating the

complimentary output in a 50 load, it is connected via a switch to the main RF

path. This helps to meet the synthesiser’s functionality requirements and at the same

time reduces the overall size and component count.



3.2.1.2 PLL Control IC

The PLL control IC carries out functions of RF and reference prescaling and

phase/frequency detection. To minimise the number of prescaler stages, the

maximum RF input frequency of the PLL IC should be as high as possible. As stated

in the previous section, the best ICs available during the synthesiser design phase had

an upper frequency limit around 3 GHz. The Peregrine Semiconductor PE97632 IC

was chosen for this synthesiser because of its high RF and reference input

frequencies: 3.2 GHz and 100 MHz respectively. Other advantages include its

delta-sigma modulated fractional-N synthesis architecture and its low additive phase

noise of -205 dBc/Hz2 [46].

The Peregrine IC’s high RF input frequency helps to meet the requirement of

minimal prescaler stages. The high reference input frequency and low additive phase

noise both contribute to lower system phase noise. The additive phase noise is a

limit of the PLL known as the figure of merit (FOM) [48]. Due to timing jitter in the

detector zero-crossing, phase noise increases by 10 dB/decade as the PFD

comparison frequency increases. Although the reference input frequency is often the

comparison frequency, this is not always so. As shown in Equation (3.1) noise also

increases by 20 dB/decade with the output frequency, which means that doubling the

comparison frequency will reduce phase noise by 3 dB.

COMPSSB fNfFOMfL log10log20 , (3.1)

where

fLSSB is the phase noise at an offset frequency f in dBc/Hz,

fFOM is the PFD figure of merit in dB,

N is the PLL divider ratio, and

fCOMP is the PFD comparison frequency in Hz.

As stated in Section 3.1.1, there are advantages to using fractional-N synthesis

instead of integer-N synthesis. Foremost of these advantages is that the step size can



be a fraction of the reference frequency. Egan [1] quotes an example of synthesising

100.007 MHz in steps of 1 kHz. With integer-N synthesis, this requires a 1 kHz

reference and a divide ratio N of 100,007. With a fractional-N synthesiser, this same

output could be achieved with a reference of 100 kHz and a divide ratio of 1000.07.

Over a sequence of 100 cycles, this can be achieved by setting the divider to divide

by 1001 for 7 cycles and 1000 for the remaining 93 cycles, as shown in (3.2).

sequence

lowfractlowfractsequence

N

NNNNNN

1 (3.2)

07.1000100

10017100093

From Equation (3.1), this results in a 20 dB improvement in phase noise over the

equivalent integer-N synthesiser.

The second advantage of fractional-N synthesis is a consequence of the first

advantage. Because the reference frequency can be higher in a fractional-N

synthesiser, the loop bandwidth can also be higher. Higher loop bandwidth is

desirable for shorter settling time, better noise performance, and higher acquisition

range.

There are two rules of thumb that relate to settling time [49];

COMPs f

t50

(3.3)

and

BANDWIDTHLOOPs f

t_

5.2 . (3.4)

Equation (3.3) shows the relationship between settling time ts and fCOMP; Equation

(3.4) shows the relationship between settling time and loop bandwidth. Because both



fCOMP and fLOOP_BANDWIDTH can be greater in a fractional-N synthesiser, the settling

time can be shorter.

A drawback of fractional-N synthesis is that the regular, periodic change in divide

ratio causes a spurious signal to appear in the output. Advanced delta-sigma

modulated (DSM) synthesisers, such as the PE97632 IC used in this system, deal

with this problem through a multi-stage noise shaping algorithm, commonly known

as MASH. In this case, the synthesiser jumps between many different integer steps,

with the MASH algorithm ideally pushing the noise to a frequency where it is

filtered by the loop filter [50].

In the synthesiser architecture of this thesis, fractional-N synthesis is essential in

order to achieve the step size and settling time requirements while still meeting the

phase noise requirement. From (3.3), the minimum comparison frequency for

ts = 250 sec is 200 kHz. From (3.4), the minimum loop bandwidth for ts = 250 sec

is 10 kHz. These are acceptable figures. However, if a 20 MHz fCOMP is used, then

(3.1) shows that fractional-N synthesiser will have 20 dB lower phase noise at

10 GHz than the integer-N equivalence.

A further advantage specific to the PE97632 IC is that its registers can be

programmed in both serial and direct modes. Very few PLL ICs are available with

direct programming but it is beneficial in this synthesiser for two reasons. The first

reason is that new frequencies can be loaded much faster than if the IC is

programmed serially. The second reason is that Micreo Limited’s expertise is in

microwave and photonic component design and packaging, not digital circuit design.

Therefore, by not including a serial communications bus, the control software is

simpler and easier to debug, and testing of individual sub-sections is also easier. The

drawback of direct programming is that there are many more connections to make.

Programming the PE97632 registers requires 4 pins in serial mode, and 38 pins in

direct mode. This is in addition to the connections common to both modes, such as

the RF and reference inputs, DC power and ground.



3.2.1.3 PLL Loop Filter

In Section 3.2.1.2 the impact of loop filter bandwidth on synthesiser performance

was raised. A poorly designed loop filter will have poor noise and poor settling time,

compromising what is an otherwise well designed synthesiser. The applications data

supplied by Peregrine Semiconductor for the PE97632 includes a recommended loop

filter schematic and a spreadsheet for calculating the associated component values.

This is the starting point for developing the loop filter used in this synthesiser.

The loop filter transfer function helps to define two basic characteristics of PLLs:

type and order [1, 51]. Loop type is related to the number of poles at the origin and

determines how the PLL responds to transients. Frequency synthesisers are typically

based on type II loops, with two poles at the origin, although type III loops are used

in applications which must correctly handle constant acceleration, such as deep space

communications. Loop order refers to the highest degree of the characteristic

equation. Most synthesisers are modelled as second order loops, although the loop

may actually be third order or higher.

The loop filter recommended for the PE97632 is shown in Figure 3.2. It consists of a

type II third order integrator with lead-lag, followed by a second order lowpass filter.

As well as the AD797 low noise op-amp [52], pre-assigned values are recommended

for some resistors and capacitors to minimise phase noise.



PE9763 PD Loop Filter:

R11

R11

R12

R12

Cc

CcR2

R2R3 R4

C3 C4

C101

C102

C2

C2

2(-)

3(+)

AD797

Outputto VCO

PD_U

PD_D

Pre-assigned values:R11 = 120 ohms; R12 = 390 ohmsR3 = R4 = 100 ohmsC101 = C102 = 22 pF

Figure 3.2: Recommended loop filter schematic [53]

Generally, components for the loop filter are selected to achieve a certain target

bandwidth, gain margin and phase margin. For a given set of filter component

values, the bandwidth and stability margins will change according to the output

frequency, as divide ratio, N, and VCO tuning gain, KVCO, vary. Stated from a

system performance perspective, the component values needed to achieve a

particular bandwidth and stability margin will change according to output frequency.

Over narrow frequency ranges, the component value changes are relatively small and

will largely be absorbed into the tolerance of the components. Over a wide

frequency range, such as in this project, the component value changes will be much

larger. This is due partly to the wider frequency range, where the divide ratio N at

the upper end of the frequency range is around one and a half times the divide ratio at

lower end of the frequency range, and partly due to the change in VCO tuning gain

KVCO across that frequency range.

As discussed in Section 2.1.2.3, the abrupt and hyperabrupt varactors used in VCOs

are inherently non-linear, and consequently give the VCO a non-linear tuning gain

KVCO. The VCOs used in this synthesiser are HMC587 VCOs from Hittite



Microwave Corporation [54], factory screened to guarantee the required level of

performance for this project. The HMC587 tuning gain is shown in Figure 3.3.

Figure 3.3: HMC587 tuning gain (sensitivity) [54]

The impact of KVCO varying with frequency can be seen graphically in Figure 3.4.

With a fixed fCOMP the divide ratio N (not shown) increases monotonically and

combines with the steadily decreasing KVCO to sharply reduce loop bandwidth at

higher frequencies. In contrast, if fCOMP is allowed to vary then the loop bandwidth

can be maintained at a more consistent frequency, thus improving the stability of the

loop.



0.1

1

10

100

7 8 9 10 11

VCO Output Frequency (GHz)

Lo

op

Ba

nd

wid

th (

kH

z)

050100150200250300350400450500

Kv

co

(M

Hz/

V)

Variable Fcomp Fixed Fcomp Kvco

Figure 3.4: Loop bandwidth is more consistent with variable fCOMP than with fixed fCOMP

The value stored in the R register sets the divide ratio for the fREF prescaler, which

determines the actual comparison frequency fCOMP. To obtain contiguous frequencies

across the full frequency range, the IC input fIN must be limited according to (3.5)

[46, 50].

190

R

ff REF

IN (3.5)

According to (3.5), with a fixed R, the two PLLs in this synthesiser would be limited

to comparison frequencies of 16.667 MHz and 12.5 MHz. However, by allowing R

to vary, two benefits are available for the synthesiser. As has been shown in Figure

3.4, the loop bandwidth can be made more consistent, which improves PLL stability.

Also, fCOMP can be set to higher frequencies than would be possible if (3.5) was

strictly adhered to. As shown in (3.1) and discussed previously in Section 3.2.1.2,

using higher frequencies for fCOMP also lowers the phase noise.

Final component values for the two PLL loop filters are derived by applying these

principles through several iterations. R is made variable and initially set to give the

highest possible fCOMP (50 MHz for the PE97632) over as much of the frequency



range as possible. Ideal component values are calculated for the highest and lowest

output frequency of each R setting. The ideal component values are averaged to give

nominal practical component values for the filter. The actual loop response is then

calculated using these practical values. The R setting frequencies are adjusted and

new component values are calculated, and the process is repeated until the filter

bandwidth is consistent at all settings.

3.2.2 LOW FREQUENCY EXTENSION

The low frequency extension is a simple direct synthesis block for generating output

signals at frequencies below the VCO band, from MHz frequencies up to C-band. It

consists of a cascade of filtered divide-by-2 prescalers, any of which can be switched

in or out of the RF path as needed. This means that division ratios can be selected in

powers of 2 from 2 to 32, or the signal can be passed without any division.

Due to the low operating frequencies, a lumped element topology is the natural

choice for the filters in this block. Distributed circuits are only used twice in the low

frequency extension: a Wilkinson divider as part of the input, and a low-pass filter to

clean up high frequency spurs at the output. Packaged components are used as much

as possible, although there are some bare die components. Both of the distributed

components are reused from other parts of the synthesiser to reduce design time.

These distributed components and the bare die components are also used to limit the

number of unique items on the synthesiser’s bill of materials.

Figure 3.5: A single prescaler stage



The prescaler cascade has five stages of the circuit shown in Figure 3.5. The circuits

for each stage differ only by the filter cutoff frequency, and the DC block capacitor

values.

As stated previously, minimising the component count is one of the methods for

reducing the overall synthesiser size. The prescaler cascade is an example of one of

the exceptions to this rule. Initially, the circuit was designed to have only four

prescaler stages. However, this would have required the filters to have a 20 dB

rejection frequency only 4% higher than the 1 dB passband edge frequency. By

adding a fifth stage, the 20 dB rejection frequency of each filter could be 20% higher

than the 1 dB passband edge frequency. The result is that a Chebyshev filter would

need to be 13th order in the four stage cascade, but only 6th order in the five stage

cascade. Consequently, each filter in the five stage cascade is approximately half the

size of the filters in the four stage cascade. This is more than adequate to

compensate for the space taken by the fifth prescaler stage.

The prescaler stage shown in Figure 3.5 has the gain budget shown in Table 3.1.

Because the prescaler IC’s input power window is -10 to +10 dBm [55], there is no

need to have additional amplifiers to drive the input of following stages. This helps

to minimise the overall component count, saving space in the synthesiser and also

improving performance. Using fewer amplifiers means that less current is required,

and because each prescaler stage has the same components and the same

performance, the final output from the low frequency extension stage is consistent

regardless of which prescaler stages are operating.

Table 3.1: Typical prescaler gain budget

Component Gain (dB) Output Level (dBm)

PE3511 Prescaler - 4

2 dB Pad -2 2

Lowpass Filter -1 1

Switch -1 0



In keeping with the approach of minimising component count, the 2 dB pad was not

in the original RF lineup for the prescaler stage. However, during the testing phase

the low frequency extension module exhibited harmonics that were higher than what

was measured on the prescaler prototype IC. This was traced to the reactive LC filter

design, which reflected the harmonics into the prescaler IC’s output circuit. Adding

the 2 dB pad correctly terminates the prescaler output and the filter input so that the

harmonics are filtered as expected.

Phase noise issues have been raised earlier in this chapter. The effect of the

Nlog20 operator in equation (3.1) is that for every divide-by-two stage in the RF

path, the PLL phase noise will drop by almost 6 dB. Residual phase noise from the

prescalers means that the circuit will not achieve the full 6 dB drop that the equation

suggests, but in the case of the low frequency extension, this is not a concern.

3.2.3 HIGH FREQUENCY EXTENSION

The high frequency extension is a direct synthesis block which generates output

signals at frequencies above the VCO band, ranging from Ku-band to Ka/V-band. It

is more complicated than the low frequency extension, due to the millimetre-wave

operating frequencies, and the use of a mixer as well as doubler ICs to generate those

frequencies.

The high frequency extension has two inputs, one from each of the PLL synthesiser

blocks discussed in Section 3.2.1. In bypass mode, the VCO signals pass through

from the inputs to the output stage unchanged. Each input has a doubler stage which

can be switched into the RF path. The doubler stages extend the frequency range to

low millimetre-wave frequencies in Ka-band, with continuous coverage of the octave

immediately above the VCO frequencies. A double-balanced mixer extends the

output frequency from Ka to V-band. A four channel switched filter bank cleans up

the mixer spurious output.



In contrast to the low frequency extension discussed in Section 3.2.2, the high

frequency extension does not use any packaged components or lumped element

filters in the RF path. To maximise performance, bare die components are used

throughout this block; in some cases because the components are only available as

bare die, and in all cases to allow maximum control over the interface between the

component and the transmission line.

Typically, MMIC components only have a single input and output bonding pad. In

this case, performance is optimised by controlling the number and diameter of bond

wires, and by controlling the length and height of the bond. The longer the wire, the

more inductance it has, which adds mismatch loss to the circuit at higher frequencies.

Some components have a ground – signal – ground (GSG) pad layout. The MMIC

switches used throughout this synthesiser are one example of this. To maximise

performance of these components, it is necessary to bond both of the chip ground

pads to the transmission line ground. Microstrip transmission line is used in this

synthesiser, which has its ground plane below the substrate, and therefore

inaccessible. The solution was to add a microstrip to grounded coplanar waveguide

(GCPW) transition so that there would be a top-side ground to bond to. An example

of this is shown in Figure 3.6. The loss as predicted in the Empire 3D

Electromagnetic solver is shown in Figure 3.7 and is comparable to the loss from a

simple microstrip transmission line of the same length. Note that the apparent

resonance in the response is an artefact of the simulation size and boundary

conditions. The resonance was not examined any further since the anticipated loss is

very low and it occurs at a frequency outside the measurement range of test

equipment available to Micreo.



Figure 3.6: A Microstrip to GCPW transition provides a top-side ground for GSG

wirebonding

Figure 3.7: The Microstrip to GCPW transition has less than 0.25 dB loss at 100 GHz

3.2.3.1 Filters in the High Frequency Extension

Filters in the high frequency extension are all distributed circuits. Because of their

wide passband and stopband requirements, the filters which follow the doubler

circuits are made using suspended stripline substrate (SSS). The four channel

Inse

rtio

n Lo

ss |S

21| i

n dB



switched filter bank uses simple edge-coupled microstrip filters. All of the filters in

the high frequency extension were designed using the S/Filsyn filter synthesis

program, and simulated using the Microwave Office circuit simulator. The results

from Microwave Office were verified with the Empire 3D Electromagnetic solver,

using the Finite Differences Time Domain (FDTD) method.

For wideband filters, it is sometimes necessary to use a cascade of highpass and

lowpass filters to achieve the required performance. A novel approach was used to

reduce the filter size in the high frequency extension. It is well known that

distributed circuits repeat at higher frequencies and that the quarter-wave frequency

of the filter determines the frequency at which it repeats. For example, a lowpass

filter with a 2 GHz cutoff frequency and 4 GHz quarter-wave frequency will have a

repeat passband starting at 6 GHz. So, rather than design a bandpass filter as a

cascade of highpass and lowpass filters, each bandpass filter is designed as a

highpass filter, with the high frequency cutoff set by the repeating nature of the

distributed circuit. The layout and simulation results of one such filter are shown in

Figure 3.8 and Figure 3.9. Because it is designed for SSS technology, the filter has a

higher Q-factor than an equivalent microstrip filter. That is, it has less insertion loss

and steeper rejection slopes. At first glance, the Empire FDTD simulation appears to

predict worse rejection than the Microwave Office simulation and the measured

results. This is a consequence of the 3D mesh density. Simulating with a higher

mesh density would give results that correlate more closely with the Microwave

Office simulation, at the cost of a significant increase in simulation time. The

Empire solver’s default grid size provides a good compromise between simulation

speed and accuracy.



Figure 3.8: A bandpass filter designed using a highpass filter structure

-80

-70

-60

-50

-40

-30

-20

-10

0

Frequency (GHz)

Inse

rtio

n L

oss

(d

B)

Ideal S/Filsyn Model Microwave Office SSS Model

Empire 3D FDTD Model Measured Filter Response

Figure 3.9: Measured results confirm that the bandpass filter performance matches

the simulation

Microstrip filters were identified as offering the best performance and smallest size

for the four channel switched filter bank. Each filter was designed in S/Filsyn as an



8th order highpass filter. The filter was converted from unit elements and series

capacitors to coupled line dimensions using an edge coupled microstrip

post-processor module.

The filters require close coupling on the input and output sections in order to match

to 50. In SSS this can be achieved using broadside coupled lines, but microstrip

can only use edge coupled lines. The gap needed to achieve the required coupling

can be as low as 7 microns, which is physically unrealisable on the soft substrates

used in this project. One solution is to replace the input and output sections with a

quarter-wave impedance match. This approach reduces the filter selectivity. For this

reason the S/Filsyn prototype was designed as an 8th order filter, in order to ensure

that the filter still has the required selectivity after modifying the input and output

sections.

3.2.3.2 Phase Noise in the High Frequency Extension

The effect of the Nlog20 operator means that phase noise is of little concern in the

low frequency extension. That same operator means that the high frequency

extension has a more significant effect on the synthesiser phase noise. The act of

doubling the frequency increases the phase noise by 6 dB. Because the doubler

MMICs are active circuits, each doubler also adds a small amount of phase noise

over and above the theoretical 6 dB.

The mixer’s effect on phase noise is slightly more complicated and depends on the

relative phase noise of the LO and IF input signals. Let the phase noise of the mixer

LO and IF inputs be LO and IF respectively. Since both signals are derived from

the same reference input, the noise is correlated, and the noise voltages will sum

together as shown in (3.6):

1010 1010log20

IFLO

fLSSB

(3.6)



Defining the difference between LO and IF as x, (3.6) can be rearranged to the

form shown in (3.7).

1010 10110log20

x

SSB

LO

fL

(3.7)

Equation (3.7) shows that if the phase noise of the two mixer inputs is equal, x is zero

and the phase noise will be 6 dB higher at the mixer output. As the difference

between LO and IF grows, phase noise at the mixer output will be dominated by

the noise of the larger signal. This effect is shown graphically in Figure 3.10.

0

1

2

3

4

5

6

7

0 5 10 15 20 25 30

Input Phase Noise Difference (dB)

Ou

tpu

t P

has

e N

ois

e In

crea

se (

dB

)

Figure 3.10: The change in mixer output phase noise decreases as the difference

between input phase noise levels increases

From (3.1) and (3.6), the synthesiser phase noise can be calculated. The expected

noise levels are shown in Figure 3.11 for 1 kHz and 10 kHz offset frequencies.



-140

-130

-120

-110

-100

-90

-80

-70

-60

0 5 10 15 20 25 30 35 40

Carrier Frequency (GHz)

Ph

ase

No

ise

(dB

c/H

z)

1 kHz Offset 10 kHz Offset

Figure 3.11: Expected synthesiser phase noise

3.2.3.3 Mixer Spurious Signals

The mixer is a double-balanced hybrid MIC, purchased from Marki Microwave [57].

Like all mixers, it generates high order mixing products. The purpose of the four

channel switched filter bank described in Section 3.2.3.1 is to suppress those

spurious signals to a suitably low level. Table 1.1 identifies the maximum required

spurious signal level as -50 dBc. To achieve this in the synthesiser, the mixer

suppresses the spurious signals to a certain level, and the filters provide the balance

of the required suppression. The suppression levels in Table 3.2 are for the

worst-case downconversion response with an RF input level of -10 dBm. The

upconversion response is typically better, but Marki does not provide data.



Table 3.2: Typical spurious suppression (dBc) of Marki Microwave double-balanced

mixers [58]

RF Input @ -10 dBm

5RF 55 55 55 55 55

4RF 50 50 50 50 50

3RF 45 45 45 45 45

2RF 40 40 40 40 40

RF - 20 10 25 35

LO 2LO 3LO 4LO 5LO

A feature of the dual oscillator synthesiser architecture is that up to Ka and V-bands,

there are at least two different ways to achieve any desired mixer output frequency.

This means that the frequency plan can be optimised to keep high level spurs such as

LONRF or LONRF 2 as far away as possible from the desired output

frequency. In this way the switched filter bank is kept at only four channels, which

helps to minimise component count and overall synthesiser size. Because there are

less channels to switch between, DC power consumption is also kept low.

3.2.4 OUTPUT AMPLIFICATION AND LEVEL CONTROL

The output amplifier is the final RF stage in the synthesiser, and it performs several

important functions. The primary function of this stage is to amplify signals to the

+10 dBm level requirement. Another function is level control; the gain of the output

amplifier is controlled according to frequency and operating temperature, to keep the

output level within a narrow window. The final function of note is that the output

amplifier is a buffer. Changes in the output load condition can change the VCO

frequency, an effect known as frequency pulling. The output amplifier isolates the

VCOs and other sensitive internal circuits so that changes to the load will not affect

the VCO frequency.

The output amplifier is designed as a cascade of three MMIC amplifiers. An LNA

MMIC is used for the first two amplifiers in the cascade, one of which is configured

for variable gain. The final amplifier is a medium power driver amplifier. Both

MMICs are from the same manufacturer and are designed as wideband 0.04-65 GHz



amplifiers. Both designs incorporate 30 dB gain control range and integrated power

detectors.

The original intent when selecting these MMICs for the output amplifier was that the

integrated power detectors could be used as part of an automated level control (ALC)

circuit. A simple analogue feedback loop would control the variable gain amplifier

based on the power detected at the driver amplifier output. However, the level

control scheme was changed to a look-up table (LUT) when the manufacturer

revealed that the detectors on these MMICs had a 20% failure rate, and did not

function at frequencies above 40 GHz.

The LUT is more memory intensive than the analogue ALC and takes longer to

calibrate, but it does not impact the gain control range in any way. A detailed

cascade analysis of the synthesiser showed that the +10 dBm output power level

could be achieved at all frequencies. Figure 3.12 shows the cascade analysis results

for the output amplifier, and highlights the impact of the level control circuit. A

wide range of input power levels is held to a consistent output power level at all

frequencies.



-25

-20

-15

-10

-5

0

5

10

15

20

0 5 10 15 20 25 30 35 40

Frequency (GHz)

Po

wer

Lev

el (

dB

m)

Input OutputMin. Input Min. OutputMax. Input Max. Output

Figure 3.12: Level control in the output amplifier ensures consistent output power at

all frequencies

3.2.5 SYSTEM CONTROL

The system control block is the brain of the synthesiser. In this block, the input

frequency command is translated into frequency setting commands for each VCO

and switch control signals to select the appropriate RF path. Temperature

measurements and the frequency setting command jointly control a DAC which sets

the output signal level. This block has voltage regulators and power management

circuits for the entire synthesiser, and also contains all the bias and logic interfaces

between the synthesiser and the outside world.

The system control block is divided into two functional sections: power and logic.

This functional division is reinforced with a physical separation of the ground planes

for each section, to minimise cross-talk and other sources of interference that could

lead to spurious signals coupling into the synthesiser output.



3.2.5.1 Power

The primary purpose of the power section is to supply all other parts of the

synthesiser with the appropriate voltages and currents. An obvious way to minimise

the synthesiser component count is to minimise the number of regulators. The

synthesiser has three supply rails; +12 V, -12 V and +5 V. These rails are regulated

as follows.

From the +12 V (analogue/RF) rail:

1. +12 V to +6.5 V switching regulator

2. +12 V to +24 V voltage doubler

3. +6.5 V to +5 V linear regulator

From the -12 V rail:

1. -12 V to -5 V linear regulator

From the +5 V (digital/logic) rail:

1. +5 V to +3.3 V linear regulator

2. +5 V to +3 V linear regulator

3. +3.3 V to +1.2 V linear regulator

As part of the power section, each of the two VCOs has a dedicated low dropout 5 V

linear regulator, for improved noise immunity.

Because of their potential for causing high noise levels and spurious signals,

switching regulators are generally avoided in microwave circuit design. However, in

this architecture, with currently available MMICs and VCOs, it is not possible to

meet the 15 W power consumption requirement of this work using only a linear

regulator.

The switching regulator is based around the LM2742 buck controller from National

Semiconductor [59]. This chip has several features which make it attractive for this

application. It has up to 95% conversion efficiency, adjustable switching frequency,

power sequencing functions including shutdown, soft-start and output enable, and it

comes in a surface mount package. This last feature is particularly relevant because



component heights on the system control PCB are restricted to 4.9 mm and all

components must be mounted on the same side of the PCB.

The LM2742 datasheet provides a comprehensive set of equations for calculating

component values that will meet the required performance level. For example, the

choice of regulator switching frequency is a compromise between inductor size and

FET losses. For this circuit, a 27 k resistor sets the switching frequency to

approximately 900 kHz. If the frequency is any lower than this the output inductor

value increases and requires a package that will exceed the 4.9 mm height limit. As

the switching frequency increases, the FET losses increase, reducing the regulator

efficiency.

The synthesiser’s power management circuit shuts down unused RF sections. This

feature is desirable for three reasons:

1. It minimises the synthesiser’s DC power consumption, helping to meet the

15 W requirement.

2. It reduces the worst case regulator load below what it would be if all RF

sections were operating continually, so that less filtering is needed and the

regulator components are physically smaller.

3. Shutting off different sections of the synthesiser can reduce or even eliminate

the need for RF switches [60] without compromising spurious suppression.

The drawback of shutting down unused sections is that the load is variable, and so

the regulator will not operate at maximum efficiency at all times. The circuit is

designed for maximum efficiency at a load of 1.5 A. Table 3.3 shows the estimated

efficiency based on detailed calculations of the load current for different frequency

ranges.



Table 3.3: Synthesiser efficiency varies according to output frequency

Frequency Range Operating RF stages Estimated Efficiency

< 7 GHz One VCO

Low frequency extension

86%

7-16 GHz One VCO 77%

16 GHz – Ka-band One VCO

One High frequency

extension doubler only

80%

Ka-band – V-band Two VCOs

High frequency extension

89%

The +12 V to +24 V voltage doubler is another potential noise source which requires

careful design. This circuit is based on the Linear Technologies LT1054 switched

capacitor voltage converter [61]. Like the switching regulator, this circuit uses

low-profile low-ESR tantalum capacitors for filtering. However, because the voltage

doubler is not required to supply more than a few mA, there are no restrictions on the

filter’s inductor size.

Voltage loss is the most important aspect of the voltage doubler. If the losses are too

high, the PLL described in Section 3.2.1.3 will not be able to tune the VCO to the

correct frequency. The LT1054 has approximately 0.55 V loss at low currents.

When configured as a doubler the circuit has two silicon schottky diodes in series,

which have approximately 1.4 V total drop. This means that the actual output

voltage of the doubler is only 22 V. Since the PLL loop filter amplifier output

cannot swing any closer than 2 V from its supply rails, this leaves the circuit with a

2 V margin when the VCO is at the top of its tuning range.

The power section has a secondary function, which is to protect the synthesiser from

faults on the supply input. Requirements of this type are often included with the

specifications for microwave components and subsystems. In this case, the circuit

must protect against three fault conditions:

1. Input reverse voltage rails



2. Input over-voltage up to +32 V

3. Application of voltage rails in any sequence.

Reverse voltage protection is the first circuit after the external connector. It consists

of a series re-settable fuse and a shunt unidirectional transil. In normal conditions,

the transil acts like a zener diode and is effectively invisible to the circuits that

follow. When reverse voltage is applied, the transil acts as a short circuit. The

surface mount transils in this synthesiser can dissipate 1500 W of power before

overheating and failing. The re-settable fuse protects the transil against this

possibility. When the transil shorts out, the rush of current trips the fuse, which will

only re-set after the voltage is lowered and power is removed.

Input over-voltage protection prevents damage to downstream ICs in the case of

excessive voltage on the input – in this case, voltage levels up to 32 V. The

protection circuit of Figure 3.13 uses a P-channel MOSFET (N-channel for the -12 V

input) as a switch, driven by a high voltage comparator. The input voltage is

measured and scaled using a resistive divider. When the voltage on the comparator’s

non-inverting input reaches the threshold set by the zener diode on the inverting

input, the FET is turned off and with it the synthesiser, until the input voltage falls

below the threshold again.



Figure 3.13: The over-voltage protection circuit shields the synthesiser from

damaging input levels up to 32 V

Voltage rail sequencing is potentially the most important of the three requirements.

If a MMIC or FET has its drain voltage applied before the gate voltage, the device

will sink maximum current until it burns out. In a synthesiser containing dozens of

these components, repairs would be difficult and expensive. However, the solution is

quite straightforward. All MMIC and FET drains are biased from regulated rails. By

adding an NPN transistor switch as shown in Figure 3.14, or making use of built-in

switches if available, the positive supply regulators are forced into a low voltage or

shutdown mode if the negative supply is missing.



Figure 3.14: The supply sequencing circuit prevents damage to MMICs and FETs

when the negative supply is missing

3.2.5.2 Logic

The logic section is mostly implemented within an Altera Cyclone II Field

Programmable Gate Array (FPGA). The other external circuits in the logic section

are the clock buffer/distribution circuit and the temperature sensor.

The clock buffer/distribution circuit uses a 1:4 buffer IC in a 3 mm by 3 mm leadless

package to minimise space. Of the four outputs, one is used in balanced mode as the

FPGA clock signal. Two are used in single-ended mode as the PLL IC reference

inputs. The fourth output is unused. Although the IC is designed for LVPECL

signals, it is equally effective when used with the synthesiser’s 50 sine input.

The temperature sensor is an LM75 digital sensor from National Semiconductor.

Although it is slower and less accurate than analogue temperature sensors, its

advantages in this application are that it comes in a small SOP-8 surface mount

To regulators

To regulators



package, and that the FPGA can read the output directly over the I2C two-wire

interface bus, without needing additional analogue to digital converter ICs.

The Cyclone II family was chosen because it could operate with 100 MHz clock

inputs and because of familiarity, since it has been used in other systems designed by

Micreo. The particular device, the EP2C8Q208I8, was chosen because it had

sufficient I/O ports and because the 208 pin Plastic Quad Flat Package (PQFP) was

compatible with current assembly processes at Micreo. Although the 256 pin

Ball-Grid Array (BGA) package is slightly smaller, the size advantage is not enough

to compensate for the increased layout complexity and assembly process

development.

The frequency setting, level compensation and power management described in

previous sections of this chapter are all controlled by a state machine implemented in

the FPGA. The state machine implementation is shown graphically in Figure 3.15.

When the synthesiser strobe input goes high, the state machine is reset. The

synthesiser output is deactivated, and the 19 bit frequency input is loaded into

memory. This is State 0.

In State 1, the frequency input is converted to register settings for the PLL ICs,

switch settings for the low frequency extension block and the high frequency

extension block, and “shutdown” signals for unused circuits.

In State 2, the FPGA reads the current temperature from the temperature sensor IC.

In State 3, the level correction factor is read from the look-up table, based on the

temperature measurement from State 2 and the frequency input loaded in State 0.

In State 4, the level correction factor is sent to the digital to analogue converter

(DAC), which then controls the variable gain amplifier.



When the PLL ICs are locked and the level control amplifier has been updated, the

synthesiser output is reactivated. This is State 5.

The final state is State 6. In this state the synthesiser waits for 5 minutes and then

returns to State 2 to refresh the temperature reading. The synthesiser will loop from

State 2 through to State 6 until interrupted by the strobe signal.

3.3 SYSTEM DESIGN CONCLUSION

This chapter has illustrated that the synthesiser is a complex system, where design

decisions in one block will affect every other block. By careful technology choice,

performance for each component can be maximised while the overall synthesiser size

is minimised. The system design incorporates both RF and DC considerations,

including power management and supply fault protection circuits. The next chapter

considers packaging of the synthesiser, including the options available and how they

impact on performance.



Figure 3.15: Bubble diagram of states in the FPGA state machine

State 0 (RESET):

Deactivate output

Load input

State 1:

Convert input to

register, switch and

shutdown commands

State 2:

Read temperature

sensor

State 3:

Look up amplitude

correction factor

State 4:

Output correction

factor to DAC

State 5:

Reactivate Output

State 6:

Wait 5 minutes

Strobe


CHAPTER 4: PACKAGING

The previous chapter describes the synthesiser’s electrical design. The system

architecture was designed to require as few RF components as possible. Technology

choices for each component aimed to obtain the best performance from the smallest

available space. Active circuits were all MMIC based – bare die for high frequency

circuits and packaged for low frequency circuits. DC power and control circuits

were designed to use low-profile surface mount components and, like the RF circuits,

to use as few as possible.

In this chapter, the synthesiser’s packaging is discussed. Several different options

with varying levels of integration are considered. Just as choices in one RF block

affect the other RF blocks, the electrical and mechanical designs are intertwined. It

would not work to complete the synthesiser’s electrical design without giving some

consideration to packaging, nor would it work to select a packaging approach before

deciding how to meet the electrical requirements.

As stated in the introduction to this thesis, the package design was done by other

engineers at Micreo, in consultation with the candidate. The candidate’s primary

involvement was with the overall concept and design approach. Specific details such

as thermal and vibration analysis were left to Micreo’s mechanical engineers.

Assembly methods for the final design, such as chip mounting, used standard Micreo

proprietary processes.

4.1 PACKAGING TECHNOLOGIES

Integration density for microwave systems varies widely. At one extreme is the

System On Chip (SOC) method, where an entire microwave system is integrated

onto a single MMIC. At the other extreme is the modular approach, still used in

many designs today. In this method, each amplifier, filter, or other RF component is

packaged as a separate module and the modules are all connected with coaxial cable.

Mobile phones and other handheld wireless devices are an example of the former

Chapter 4: Packaging


method, rack mounted test equipment is an example of the latter method. Although

both of these methods can be readily dismissed as impractical for meeting the goals

of this project, there are a range of options that are worth evaluating.

4.1.1 LOW TEMPERATURE CO-FIRED CERAMIC

Low Temperature Co-fired Ceramic (LTCC) is a highly integrated multi-layer

packaging technique using a ceramic substrate. In this process, metallisation patterns

are made on each layer, along with any films needed for embedded resistors and

capacitors. Cutouts can be made to allow space for ICs, and vias in the substrate

provide electrical connection between the layers. The layers are then stacked

together and fired together in a kiln. LTCC was developed from High Temperature

Co-fired Ceramic (HTCC), but has two distinct advantages. First, the ceramics are

fired at a low temperature of only 850C, compared to firing temperatures over

1500C for HTCC. Second, and a consequence of the lower firing temperature, is

that LTCC can incorporate low loss metals and resistor films. The high firing

temperature of HTCC restricted the metal selection to materials such as molybdenum

and manganese [62].

The ability to integrate passive RF and DC circuits is one of the greatest advantages

of LTCC. Transmission lines, distributed RF filters, lumped RF filters, DC blocks,

bias tees, can all be integrated into one small circuit. As stated previously, cutouts

can be made to allow space for ICs to be soldered in, and metallisation options allow

for wirebonding of bare die ICs. For packages that make use of bare die, LTCC has

further advantages: being ceramic it has good thermal conductivity compared to

other material such as Teflon, and the coefficient of thermal expansion (CTE) of

5.9 ppm/C is well matched to the GaAs CTE of 6 ppm/C.

However, LTCC has some disadvantages which when combined make it unsuitable

for this synthesiser:

1. Filters manufactured in LTCC have lower Q than those manufactured using

methods like suspended stripline substrate (SSS). Filter insertion loss rises as

Q falls, and a filter in low-Q material will need to have a higher order if it is



to have as much rejection as a filter in a high-Q material. Increasing the filter

order leads to increased passband loss, making the problem worse. This is

not insurmountable but it makes LTCC unattractive, since the filters become

larger, negating the advantage of high density integration. More amplifiers

are needed to compensate for loss, which also takes up more area, and

increases the power consumption requirements.

2. LTCC is prone to process variations. The “green tape” shrinks by 15 – 25%

in the z-axis when fired, and by 12 – 16% in the x-axis and y-axis. In a high

performance filter, process variations of that magnitude can be expected to

significantly alter the response. While most other topologies can be tuned to

account for process variation, this is not practical in LTCC. The consequence

of this is that the filters should be low order, and designed with a wide margin

to allow for the process variations. This may also lead to a larger circuit, if it

becomes necessary to use multiple low order filters instead of a single high

performance filter.

3. Like semiconductors, LTCC is a process designed for high volume. For

simple, low value products, production runs may reach millions of units.

When the development and tooling costs are spread over such a large

production run, the efforts needed to account for low-Q and process

variations are worthwhile. However, for complex, high value products,

quantities are only counted in ones and tens, and the development costs of

LTCC make it uneconomical. For these reasons, LTCC was rejected for this

synthesiser.

4.1.2 MULTILAYER PTFE

Multilayer PTFE packaging shares several similarities with LTCC. It is based on a

stack of PTFE circuit boards bonded together. There are resistive films that can be

included to create embedded resistors. Cutouts in the substrate layers allow space for

lumped and active components.



There are differences between LTCC and multilayer PTFE. One of the advantages

of multilayer PTFE is that the processing temperature is much lower. For example,

the 3001 bonding film from Rogers Corporation has a bonding temperature range of

199C to 246C [63]. A consequence of the low processing temperatures for PTFE

is that it allows the use of copper, which is more conductive than the materials such

as gold or tungsten which are used in LTCC. Multilayer PTFE does not experience

the same sort of shrinkage as LTCC, although both techniques require careful

alignment of the layers. Multilayer PTFE is also cheaper to prototype than LTCC,

and can be done in short runs. Although inner layers are inaccessible, circuits on

outer layers of the PTFE package are more easily modified by hand than on an LTCC

package.

Multilayer PTFE also has some disadvantages compared to LTCC. Unlike LTCC,

the final PTFE package is not hermetic. The CTE of PTFE is much higher than

LTCC, so it is not so well matched to GaAs. In particular, the low loss dielectrics

which are most useful at millimetre-wave frequencies have a Z-axis CTE of over

200ppm/C [56]. In a multilayer circuit, where the electrical performance is

dependent on the thickness of each layer, this can lead to significant changes in

performance over the synthesiser’s required operating temperature range. Thermal

conductivity is also much lower in PTFE than in LTCC, at only 0.2 W/m/C. This

may be acceptable in a phased array application where each module has very low

power dissipation, but in this synthesiser such low conductivity would result in

undue thermal stress, especially on components situated several layers above the

synthesiser’s mounting surface.

4.1.3 MICROWAVE SUPERCOMPONENTS

Microwave supercomponents are widely used, particularly in space and airborne EW

applications, where physical area and DC power are limited [64]. Supercomponents

rely heavily on MMICs to achieve a higher level of integration than a purely modular

design. For this reason, a simple supercomponent may also be referred to as a

Multi-Chip-Module (MCM) [30, 31]. Whereas in the modular approach each

component is packaged individually, in the supercomponent approach, a functional



block of components will all be packaged together. Low frequency power and

control circuits will be incorporated into the same package. So for example, rather

than have separately packaged amplifiers, mixers, local oscillator, and filters, a block

downconverter designed as a supercomponent would include all of those functions in

a single package. Instead of connecting the packages with cables, the MMICs are

connected with microstrip or stripline transmission lines.

One of the advantages of microwave supercomponents when compared to LTCC and

multilayer PTFE is flexibility. A supercomponent can include multiple technologies

– perhaps even LTCC. Each technology can be chosen to best suit the application,

for example: SSS or combline for high-Q filters, microstrip for low cost, hybrid MIC

for performance. There is also the flexibility to make changes to circuits “on the fly”

during tests after a supercomponent is built, something which is impossible in LTCC.

There are also drawbacks to using supercomponents. The design of supercomponent

housings requires skilled mechanical engineers using 3D CAD programs to ensure

that all of the constituent parts fit together correctly. Assembly and RF alignment are

labour intensive activities, and will be more or less difficult depending on the

performance requirements and the quality of the design. And because it is integrated

into a single housing, even a well designed component may have unintended

EMC/EMI problems, with signals coupling from one RF cavity to another, or being

conducted down power supply lines.



Table 4.1: Relative performance of different packaging approaches

LTCC Multilayer

PTFE

Supercomponent

(Aluminium housing)

CTE (ppm/C) 5.9

31 (x-axis)

48 (y-axis)

237 (z-axis)

23

Thermal

Conductivity

(W/m/C)

2 – 5 0.2 237

Hermetic? Yes No Yes

Size Smallest Small Medium

RF Design

Complexity

Very High Very High High

Mechanical Design

Complexity

Low Low High

Ease of Modification Very Low Low Very High

RF Performance Moderate Moderate Very High

Despite these drawbacks, the microwave supercomponent approach is more

compatible with the skills and experience of the industry partner Micreo Limited, and

is suitable to the miniaturisation of a complex high-value system like this synthesiser.

Consequently it was chosen over LTCC and multilayer PTFE for this project.

4.2 PACKAGING THE SYNTHESISER

The total space available for this synthesiser is an area 150 mm long, 100 mm wide

and 30 mm high; roughly the size of two DVD cases stacked on top of each other.

Only the 100 MHz reference input, the DC power/control input and the RF output

connector are allowed to protrude outside this envelope. A 3D CAD sketch of the

synthesiser is shown in Figure 4.1.

Three criteria combined to guide the development of the synthesiser packaging

approach: efficiency, performance, and manufacturability. To meet the size



requirements, the packaging must be efficient, with no wasted space. The package

design should support and not hinder the synthesisers’ high performance

requirements. A particular focus for this criterion is the interconnections between the

different functional blocks. Finally, the design should simplify and not complicate

the manufacturing process.

4.2.1 EFFICIENCY

The RF circuits used throughout this synthesiser are mostly planar or very low

profile. In the context of efficient packaging, the low profile of these circuits can be

exploited by separating the synthesiser into layers. The functional architecture

described in Chapter 3 lends itself to separation into four physical modules: the

VCO/PLL module, the Low Frequency module, the High Frequency/Output

Amplifier module, and the Power and Control module.

Figure 4.1: 3D CAD sketch of the synthesiser, showing modules in four layers

Each of the three RF modules contains amplifiers, switches, filters, and control

circuits. Unlike the highly modular approach described previously where each

module contains a single component, each of these modules is a supercomponent in

its own right. The low profile nature of these circuits is further exploited by layering



the RF and DC circuits within each module, as shown in Figure 4.2 and Figure 4.3.

RF circuits are assembled on one side of the chassis, and the DC circuit board is

installed on the other side. To fit taller ICs and tantalum capacitors into the chassis

without increasing the overall height, pockets are machined into the DC side of each

chassis. A good 3D CAD model of the chassis and of the components is essential for

this approach to work properly.

Figure 4.2: Cross-sectional view of the VCO/PLL module, showing layering of the RF

and DC circuits, and the use of pockets to accommodate taller DC components

Not all of the circuits in the synthesiser are low profile. In particular, the lumped

filters used in the Low Frequency module are 6.5 mm tall. To place these

components on the same plane as other components would increase the module

height by about 50%, and the overall height of the synthesiser by more than 10%.

Most of that space would be wasted. To make more efficient use of the available

space, the pocket approach is applied to the RF circuit as well. In this case, the depth

of the RF cavity changes so that the top of the filter is flush with the top of the lids

that cover the microstrip transmission lines. Although this change reduces the

available space for the DC circuit board, the impact is negligible.



Figure 4.3: Cross-sectional view of the Low Frequency module, showing that pockets

can also be used to accommodate taller RF components

4.2.2 PERFORMANCE

Stating that the package design should be conducive to the synthesiser’s high

performance requirements appears vague at first, but there are many aspects of the

design which will either help or hinder performance. Separating the synthesiser into

four separate modules helps meet the performance requirements, since it increases

isolation between the functional blocks. There may still be conducted interference

between modules, but because each RF circuit is fully enclosed in an aluminium

chassis, there will be less radiated interference than if the RF circuits were all in a

single module.

The order of the modules is important to synthesiser performance. From top to

bottom, the modules are arranged:

- High Frequency/Output Amplifier

- Low Frequency

- VCO/PLL

- Power and Control

The VCO/PLL module is placed immediately above the Power and Control module

because it has the most connections. Keeping the signal lines as short as possible

helps to prevent spurious signals from radiating out and protects sensitive signals

such as the 100 MHz reference and the 20 V VCO tuning bias from any external

interference.



However, the most important decision affecting performance is the RF

interconnections. The reason for grouping the High Frequency and Output Amplifier

functional blocks into a single module is to eliminate millimetre-wave

interconnections. Because they share a common chassis, the blocks are connected

with a simple microstrip transmission line, which eliminates the losses associated

with connector interfaces and cables. This means that although the synthesiser

output frequency reaches V-band, connections between the modules only operate up

to Ku-band frequencies. Most connections operate at frequencies in X-band or

lower. A follow-on consequence of this is that the modules are connected using

GPO connectors, which are more rugged than the GPPO connectors which would be

needed for an interface at V-band frequencies.

As well as being efficient, the internal layout of each module is designed to minimise

the RF interconnect length. The modules are laid out in such a way that connections

are all made at the ends of the modules. By doing this, a novel RF backplane

approach as shown in Figure 4.4 can be used, rather than the more traditional

semirigid or coaxial cable approach. Each backplane consists of surface mount

right-angle connectors, soldered onto microstrip transmission line. Each

transmission line runs in a separate RF channel to maintain isolation between the

paths. The backplane approach does not require any cable assembly or forming

tools, and it simplifies synthesiser integration. Rather than installing or removing

multiple cables at each end, connections are made by plugging in a single RF

backplane. Because each backplane is assembled in its own aluminium chassis, it

has inherent structural protection, whereas cables would require an additional cover.

The backplanes also protect the flexi-PCB circuits that transfer power and control

signals throughout the synthesiser.



Figure 4.4: The synthesiser backplane assemblies provide straightforward RF

interconnection between modules and protect the flexi-PCB DC interconnections

4.2.3 MANUFACTURABILITY

The final requirement of the package design is to simplify manufacturing rather than

complicate it. Separating the synthesiser into four layers contributes to meeting this

requirement, because each module can be assembled independently. Once

assembled, each module can be aligned independently so that it meets the necessary

performance requirements. The time benefits of this approach are obvious.

Section 4.2.1 discussed the use of pockets to accommodate larger components on

each module’s power and control PCB. In some cases, it is possible to do a variation

on this approach and design the chassis with a hole above the PCB. When this is

done, the PCB can be laid out so that select-on-test (SOT) components are all located

in the exposed region. Making both DC and RF circuits accessible without having to

constantly turn the module over makes another contribution to manufacturability.

This is illustrated in Figure 4.5 and Figure 4.6 below. Note that both of these images



have been edited to remove commercially sensitive information, however the

principle of simultaneous DC and RF access is still clearly seen.

Figure 4.5: The VCO/PLL module incorporates many different technologies and is

designed to provide easy access to SOT components during manufacturing (image

digitally edited to remove commercially sensitive information)

Figure 4.6: The Low Frequency module incorporates many different technologies and

is designed to provide easy access to SOT components during manufacturing (image

digitally edited to remove commercially sensitive information)



3D CAD programs contribute to manufacturability as well as efficiency. Many

different tools are used to assemble RF circuits, ranging from soldering irons to

tweezers to wire bonding machines. Models of these tools can be used to verify that

there is sufficient clearance around the parts to fit in the appropriate assembly tools.

By applying the concepts discussed in this chapter, the high performance synthesiser

circuits discussed in Chapter 3 can be integrated into a small, efficient package. The

integration density is best illustrated by Figure 4.7. Multiple layers of RF and DC

circuitry are stacked on top of each other. Backplanes provide RF interconnection up

to Ku-band frequencies and protect the flexi-PCB circuits that carry power and

control signals between the modules. By using aluminium for the chassis, heat is

rapidly transferred away from components in each module. Close contact between

modules ensures that the heat is transferred to the base of the synthesiser. Space is

allowed on each module for hermetic sealing to protect bare die and other

non-hermetic RF components.

Figure 4.7: Cross-sectional view through the complete synthesiser assembly

Chapters 3 and 4 have shown the principles and decisions behind the final electrical

and mechanical design of the synthesiser. The finished synthesiser prototype is

shown in Figure 4.8. In the next chapter, the measured performance of the

synthesiser is presented.



Figure 4.8: The finished synthesiser


CHAPTER 5: PERFORMANCE

Chapters 3 and 4 discussed the design of the synthesiser; the system architecture, the

reasons for choosing certain circuit topologies, and the mechanical packaging

approach. All of these design decisions were made in order to meet the performance

requirements set out in Table 1.1.

The strength of the design and its effectiveness in meeting these requirements can

only be judged properly by building and testing a synthesiser. Two synthesisers

were assembled in the Micreo manufacturing department, and this chapter discusses

their measured performance.

5.1 TEST EQUIPMENT AND METHODS

Verifying the synthesiser’s performance obviously needs test equipment that can

make accurate measurements at all of the frequencies and power levels set out in

Table 1.1.

The primary piece of test equipment was the Agilent E4448A spectrum analyser. Its

operating frequency range covers from 3 Hz to 50 GHz under normal conditions, and

can be extended to 110 GHz or higher when used with external mixers. This unit

was used for all RF measurements except phase noise. Phase noise was measured on

an Agilent E4440A 26.5 GHz spectrum analyser fitted with the phase noise

measurement personality, option 226.

For environmental testing, the operating temperature was controlled using a Sigma

Systems Corporation TP294 thermal platform and Model C4 temperature controller.

The random noise vibration was controlled using an LDS/Dactron LAS-200

controller with a HPA-K v2 V780 power amplifier and a V780, M8-CE air cooled

vibrator.

Chapter 5: Performance


5.1.1 FREQUENCY SWEEP

The frequency sweep was the primary measurement on the synthesiser, collecting

data about frequency, output power level, harmonic levels and spurious levels. In

order to see all harmonic and spurious signals, the spectrum analyser was set to its

full span: 3 Hz – 50 GHz. To accurately measure the power level of the

fundamental, the reference amplitude was set to +20 dBm. To have sufficient

dynamic range for accurate measurements of spurious signals at -50 dBc or lower,

the instrument’s resolution bandwidth was set to 1 MHz and the video bandwidth

was set to 300 kHz.

At each frequency setpoint, the measurement started with a marker peak search. The

marker was set to frequency counter mode, which increases measurement time

slightly but gives an accurate reading of the output frequency. In normal marker

mode, the accuracy of the displayed marker frequency is limited by the measurement

span and the number of points in the trace. Frequency and amplitude delta

measurements were recorded for every peak found with amplitude greater than -50

dBc, the maximum spurious signal level.

At 1 MHz intervals, measuring across the full frequency span would result in over

40,000 data points. This would be too many points to measure efficiently by hand,

so the frequency sweep test was automated using Labview. Each full frequency

sweep test collected over 10 MB of raw data, so a MATLAB script was written to

process the data and present the results graphically.

5.1.2 SETTLING TIME

The original settling time test was based on mixing the output of two synthesisers

together in a DC coupled mixer and measuring the time required for the beat note to

disappear, as described in [1, 2]. However, this method requires a lot of equipment

and is time consuming, which makes it unattractive in a manufacturing environment.

It is also limited to measuring frequency steps which are less than the IF bandwidth

of the mixer, which makes it difficult to measure large steps.



An alternate test method was developed which overcomes all of these problems. In

the new method, the spectrum analyser is set to zero span at the target frequency.

The resolution bandwidth sets the accuracy window. For example, if the settling

time is specified for an accuracy of final value 150 Hz, the resolution bandwidth is

set to 300 Hz. The measurement is triggered by the same strobe signal that is sent to

the synthesiser. The settling time is then simply the time for the signal to reach its

final amplitude.

Although this new method does not measure any information about phase, it is

simple and can be done without any changes to the frequency sweep setup of Section

5.1.1. A further advantage of this is that if necessary in the future, the settling time

measurement could be run as part of a single automated test with the frequency

sweep measurement.

5.1.3 PHASE NOISE

As stated previously, the E4440A spectrum analyser was used for phase noise

measurements up to 26.5 GHz. Phase noise at 35 GHz and 40 GHz was calculated

based on manual measurements using the E4448A 50 GHz analyser. The method for

these measurements was similar to the process built into the option 226 phase noise

personality, but obviously much slower.

5.2 FREQUENCY SWEEP RESULTS AND DISCUSSION

The cable between the synthesiser and the spectrum analyser has insertion loss, as

shown in Figure 5.1, which must be accounted for in the measurements.



Figure 5.1: Spectrum analyser input cable insertion loss

5.2.1 OUTPUT POWER

The target output power minimum is +10 dBm. The first synthesiser averages

+13 dBm, while the second synthesiser averages +9 dBm. Plots of the output power

for each synthesiser are shown in Figure 5.2 and Figure 5.3 respectively.



Figure 5.2: Fundamental output from the first synthesiser

Figure 5.3: Fundamental output from the second synthesiser



The performance demonstrated in these two figures shows that the synthesiser should

be able to achieve +10 dBm output power as required. The synthesiser output over

its operating temperature range is shown below in Figure 5.4.

Figure 5.4: The second synthesiser’s output at different operating temperatures

Although the output power reaches the required +10 dBm level for most

combinations of frequency and temperature, there is some variation under different

conditions. In Figure 5.2, the first synthesiser’s slope from 2-5 GHz is due to slope

in the low frequency module output amplifier, and the installation of a 3 dB pad to

reduce the power level going into the output amplifier at low frequencies. This

would have had less effect if the synthesiser had been calibrated for +10 dBm output

power instead of +13 dBm. The null at 25 GHz is due to a fault with one of the

bandpass filters in the high frequency module – most likely a short circuit where

material has been added to ensure continuous electrical contact between the bandpass

filter lid and the adjacent RF trench lids. The second synthesiser output does not



have this null, indicating that the fault is an isolated workmanship issue with this

unit, not a fundamental design flaw.

Both synthesisers show rapid output variation in narrow spans around 35 GHz and

40 GHz. This is due to the switched filter bank after the mixer in the high frequency

module. It is a result of the filter passbands being too narrow, so that one filter’s

passband is rolling off before the next filter’s passband starts.

Figure 5.4 shows that the output of the second synthesiser is generally stable over

temperature. The 3 dB increase in power at some frequencies at -20C is due to an

over-extended tuning screw which affects a filter in the PLL synthesiser module

when operated at -55C. The same filter is fully functional at -20C but because the

change from functional to non-functional is sudden, the MATLAB calibration

routine gives an erroneous output. Although the depth of the tuning screw is the

primary fault which must be prevented in the future, this highlights the potential for

refinements in the calibration routine as well.

The drop in power at +71C is due to lower output signal from one of the VCOs.

The direct VCO output is 2-3 dB lower than the required +10 dBm level. At

frequencies above 35 GHz, the mixer performance also affects signal level, resulting

in the null shown in Figure 5.4.

5.2.2 HARMONICS

The prototype synthesisers’ harmonic output is shown in Figure 5.5 and Figure 5.6.

Both prototypes have high level harmonic output up to the fourth harmonic; the

second harmonic of the second synthesiser is particularly high, on average only

10 dB below the fundamental signal level.



Figure 5.5: Harmonic output from the first synthesiser at +25C

Figure 5.6: Harmonic output from the second synthesiser at +25C



Tests on the individual filters and sub-modules predicted harmonic levels well below

the -20 dB requirement, which indicates that the Output Amplifier stage is raising the

harmonics above the required level.

The Output Amplifier stage is a cascade of MMIC amplifiers. The final amplifier is

a fixed gain power amplifier, but the second last amplifier is used as a variable gain

amplifier to ensure a stable output level. By connecting to the MMIC’s Vg2 pad for

gain control, the 1 dB compression point is lowered by 5-8 dB, even if the gain is set

to maximum. Harmonic output from the MMIC also increases as the gain is

decreased [65], with consequences for this synthesiser as shown in Figure 5.5 and

Figure 5.6.

5.2.3 SPURIOUS SIGNALS

Above 30 GHz, the spectrum analyser noise floor increases by approximately 10 dB.

With the default measurement settings, this makes it difficult to discern actual

spurious output from instrument noise. Although reducing resolution bandwidth and

video bandwidth lowers the noise floor, it comes at the cost of significantly longer

measurement time. Consequently, the data analysis has only considered spurious

frequencies at signals below 30 GHz.



Figure 5.7: Spurious output up to 30 GHz from the first synthesiser

Figure 5.8: Spurious output up to 30 GHz from the second synthesiser



To determine the most appropriate way to address those spurs which are above the

-50 dBc level, the source of the spur must be identified.

At frequencies up to 30 GHz, there are two main sources of spurious signals. If there

is a frequency doubler in the signal path, then the spur may occur at half or 1.5 the

set output frequency. The more significant cause of spurious signals affects all paths,

and occurs when the signal at the set frequency mixes with the pre-scaled signal

which drives the synthesiser IC. Some examples of this are shown in Table 5.1.

Table 5.1: Examples of spurious sources for fundamental frequencies up to 30 GHz

Fundamental Frequency

(GHz)

Spurious Signal

Frequency (GHz)

Spurious Source

5 12.5 2nd harmonic mixed with

DSM IC input

12 10.5 Fundamental mixed with

DSM IC input

15 Fundamental mixed with

intermediate prescaler

output

22.5 Fundamental mixed with

10.5 GHz spur

24 12 Frequency doubler input


DSM IC input


DSM IC input

At frequencies above 30 GHz, the number and magnitude of spurious signals

increases significantly. They are high order output products from the Ka-band mixer

in the High Frequency Module.



5.3 SETTLING TIME RESULTS AND DISCUSSION

From Table 1.1, the synthesiser is required to settle from any frequency to any other

frequency in less than 250 s from the strobe signal.

Using the technique described in Section 5.1.2, the actual settling time was measured

on both synthesisers for several different frequency combinations. These

combinations were selected to cover four general cases:

1. Small frequency steps on a single VCO

2. Large frequency steps on a single VCO

3. Switching from one VCO to the other

4. Steps on both VCOs

The results are collated into the histogram shown in Figure 5.9. Only two samples

fall within the 250 s requirement. Both of these samples are for case 1: small

frequency steps on a single VCO. The remaining samples are for cases 2, 3 and 4,

and all results are 500 s or greater.

0

5

10

15

20

25

<250

251-5

00

501-7

50

751-1

000

1001-1

250

1251-1

500

1501-1

750

1751-2

000

2001-2

250

2251-2

500

2501-2

750

2751-3

000

3001-3

250

3251-3

500

Settling Time (usec)

Figure 5.9: Measured synthesiser settling time, 74 samples, 250 sec bin size



In Chapter 3, the relationship between loop bandwidth and settling time was

discussed. Based on Equation (3.4) and the nominal loop bandwidths plotted in

Figure 3.4 the expected PLL settling time is from 30-60 s. The delay through the

FPGA was measured on both synthesisers and is less than 70 ns, which is not enough

to account for the total switching time measured on the synthesisers.

A typical settling time measurement is shown in Figure 5.10. In the close up view of

Figure 5.11 the signal level increases as the VCO approaches the lock frequency, but

it takes several cycles before it reaches the final value. This is an effect called cycle

slipping. Cycle slipping occurs when the accumulated phase difference in the

synthesiser IC approaches 360. The PLL interprets this as a small phase error

because the signal is almost locked, which causes the loop to lose momentum. At

each peak, the VCO is approaching the lock frequency, but as the phase error reaches

360, the PLL loses momentum and the VCO retreats back toward the start

frequency again [66].

Figure 5.10: Synthesiser settling time



Figure 5.11: Synthesiser settling time – a close up view of the effect of cycle slipping

One of the typical causes of cycle slip is that the PLL loop bandwidth is reduced to a

small fraction of the comparison frequency fCOMP. This causes the VCO to change

frequency more slowly, allowing larger phase errors to accumulate and reach the

critical 360 point.

Cycle Slip Reduction (CSR) circuits are often built directly into synthesiser ICs,

although this is not a feature of the particular IC used for this work. In the circuits

surrounding the IC several measures can be taken to address cycle slip. One measure

is to increase the PLL loop bandwidth, either permanently or for transients only.

This can be achieved by injecting current into the loop when a new frequency is

selected, or by temporarily changing the loop gain. Another measure is to use a

“speed up” circuit, where a DAC provides a coarse tuning signal which brings the

VCO close enough to its final value to lock without slipping. A third measure is to

reduce the comparison frequency, either permanently or for transients only [1].

Due to project funding and schedule requirements, these CSR methods could not be

investigated at this time, but they will be pursued and implemented in the future.

Although these solutions are likely to increase the total component count, the

additional components are not expected to compromise the overall miniaturisation

effort, and will deliver a significant performance improvement.



5.4 PHASE NOISE RESULTS AND DISCUSSION

The synthesiser phase noise requirement at 10 GHz was given in Chapter 1 and is

reproduced here in Table 5.2.

Table 5.2: Synthesiser phase noise requirement at 10 GHz

Offset Frequency (kHz) Maximum Phase Noise (dBc/Hz)

0.1 -60

1 -65

10 -70

100 -75

1000 -80

The actual phase noise at 10 GHz for the two synthesisers is shown in Figure 5.12

and Figure 5.13. This is a typical phase noise result for this synthesiser.

Figure 5.12: First synthesiser phase noise at 10 GHz



Figure 5.13: Second synthesiser phase noise at 10 GHz

The first synthesiser meets the requirements at all offset frequencies, while the

second synthesiser fails the requirements by 1.5 dB at 10 kHz. The figures show that

the phase noise for both synthesisers peaks up at approximately 30 kHz offset,

instead of falling monotonically as would be expected from a typical synthesiser.

These peaks are a consequence of the loop bandwidth being too narrow and allowing

the VCO’s intrinsic phase noise to come through at a higher level.

The amount of peaking in the response varies with frequency, as demonstrated in

Figure 5.14 and Figure 5.15. Figure 5.14 shows the first synthesiser’s phase noise at

1.75 GHz, with a clear peak at approximately 60 kHz offset. Figure 5.15 shows the

first synthesiser’s phase noise at 26.5 GHz. In this case the noise is almost flat from

20 Hz until it starts rolling off at approximately 20 kHz. Although the absolute

phase noise level is affected by the number of prescalers or frequency multipliers

between the VCO and the output, this has little impact on the shape of the noise

curve.



Figure 5.14: The first synthesiser’s phase noise at 1.75 GHz has a clear peak

Figure 5.15: The first synthesiser’s phase noise at 26.5 GHz has no discernible peak

5.5 DC POWER RESULTS AND DISCUSSION

Low DC power consumption is an important part of the synthesiser miniaturisation.

Section 3.2.5.1 discussed this requirement, and the techniques used to achieve it. In

Table 3.4 the estimated power efficiency was presented for four different frequency



ranges. The synthesiser’s estimated and actual power consumption are given in

Table 5.3. The first synthesiser meets the 15 W requirement at all frequencies, while

the second synthesiser uses 200 mW over the required level at the highest output

frequencies. The power consumption at mid-range frequencies was higher than

predicted for both synthesisers. This was traced to higher than expected current draw

from the switching regulator by system blocks which were not fully shut down.

Table 5.3: Estimated and actual DC power consumption

Frequency Range Power Consumption (W)

Requirement Estimated Actual

First

Synthesiser

Second

Synthesiser

< 7 GHz 15 13.8 13.9 13.2

7 – 16 GHz 15 10.7 12.6 14.9

16 GHz – Ka-band 15 11.5 13.7 14.0

Ka-band – V-band 15 16.3 14.5 15.2

The shut down circuits in this synthesiser typically operate in one of two ways. For

amplifiers with gate and drain bias, the shutdown circuit changes the gate bias from a

nominal 50% Idss level in normal operating conditions to the “pinch-off” voltage,

where the amplifier draws almost no current. For self biased amplifiers, the

shutdown circuit controls the gate of a series FET to cut off current supply in the

shutdown mode.

As well as shutting down individual amplifiers, another potential improvement is to

isolate the supply rails at the input of each physical block. This would eliminate the

leakage current that still flows into the amplifiers even when they are in RF

shutdown mode. It would also eliminate the current drawn by switch circuits when

there is no RF signal to direct.



5.6 ENVIRONMENTAL RESULTS AND DISCUSSIONS

The second synthesiser was tested in different environmental conditions, as well as

the nominal laboratory condition of +25C. The primary purpose of environmental

testing was to validate the design and show that the techniques used to miniaturise

the synthesiser did not compromise its capacity to operate outside a controlled

laboratory environment.

The fundamental output power has already been shown at different operating

temperatures in Figure 5.4. Although the calibration routine can be improved, it is

generally effective in maintaining constant output power at different temperatures.

Spurious and harmonic signal levels both show changes over temperature. The

typical spurious level is relatively stable; it is the frequency of the highest peak

which changes. This does not mean that different spurious signals are only present at

some temperatures. It is an artefact of the MATLAB analysis routine, which only

searches for the highest non-harmonic spur and disregards all others. In many cases

there are additional spurious signals, such as those listed in Table 5.1, which are less

than 1 dB lower than the highest spur.

Harmonic levels show a clear trend over temperature. The harmonics are highest at

-20C, and the level steadily decreases as the temperature increases. This is shown

in Figure 5.16 for the third harmonic at fundamental frequencies up to 5 GHz.



Figure 5.16: Harmonic rejection improves as the operating temperature increases

The effect of temperature on settling time is less clear than the effect on harmonic

levels. At +55C, the settling time is an average 28 s faster than at +25C. At

-54C the settling time is an average 2.4 s slower than at +25C. However, these

figures only apply for relatively fast settling times. For frequency steps which are

severely affected by cycle slip and have settling times in the millisecond range, the

settling time varies unpredictably. For example, a 500 MHz step from 15.25 GHz to

14.75 GHz takes 3 ms at +25C, 2 ms at -54C, but only 1 ms at +55C.

Phase noise measurements do not show any discernable trend over the operating

temperature range. As shown in Table 5.4, there is typically less than 3 dB variation

in noise at any given offset. The fact that the results do not have a clear trend

suggests that the differences are a result of random measurement noise.



Table 5.4: The synthesiser’s phase noise at 10 GHz does not change significantly

with changes in temperature

Offset (kHz) Phase Noise (dBc/Hz)

-54C +25C +55C

0.1 -73.2 -76.7 -74.0

1 -70.9 -73.5 -70.9

10 -66.2 -68.5 -67.5

100 -81.8 -82.8 -81.8

1000 -122.6 -122.2 -121.0

As part of the environmental tests, the second synthesiser was tested to a vibration

level of 7.3 grms in all three axes, such as the example shown in Figure 5.17. The test

was primarily an endurance test, with the profile running for 4 hours in each axis.

The synthesiser was tested at several representative frequencies before, during and

after the vibration and functioned continually with no observed change in

performance. The time required to test every frequency point meant that it was not

possible to measure the performance during vibration at every single frequency.

profile(f)

high-abort(f)

low-abort(f)

high-alarm(f)

low-alarm(f)

control(f)

500.0010.00 100.00

0.1413

0.0002

0.0010

0.0100

Frequency (Hz)

(gn)²/Hz

Figure 5.17: A typical random vibration profile for the synthesiser



5.7 SUMMARY OF SYNTHESISER PERFORMANCE

The results presented in this chapter lead to two conclusions about this miniaturised

synthesiser.

The first conclusion is that the synthesiser is a successful demonstration of the

miniaturisation techniques used in this project. It generates output signals from low

MHz frequencies to > 40 GHz, at a resolution less than 1 MHz. The synthesiser does

this in a small, lightweight package which is still sufficiently rugged to withstand

operation from -54C to +71C and vibration up to 7.3 grms.

The second conclusion is that performance in some key areas can be improved with

further engineering development work, particularly fundamental output power,

output harmonic levels, output spurious levels and settling time. Reasons for the

non-ideal measurements have been given, and there is a way forward that will result

in a synthesiser which meets all the requirements of Table 1.1. In most cases the

changes are relatively minor and in no case will a change compromise the

synthesiser’s performance for those requirements which it already meets.


CHAPTER 6: CONCLUSION

In Chapter 1, the need for miniaturised wideband frequency synthesisers was

established, and performance criteria were determined for this particular project.

Although the requirements are all straightforward when taken individually, the

challenge for this project was identified as meeting all requirements in a miniaturised

package.

The literature review section of Chapter 2 identified several circuit design and

packaging techniques that could be applied to solve the problem. Some of these

techniques, such as hybrid direct/indirect architectures and varactor tuned oscillators,

were more suitable than others and were integrated into the final design. The product

review section confirmed that the synthesiser requirements were not simply

duplicating existing products. In fact, achieving all of the requirements of this

project is a clear advance in the state of the art for synthesiser design.

In Chapter 3, attention turned to the synthesiser system architecture and details of the

electronic circuit design. Different system architectures were presented and the

advantages and drawbacks were discussed for each one. The dual oscillator

synthesiser architecture was chosen for the way it takes advantage of different

aspects of both direct and indirect synthesiser topologies to meet the overall

requirements.

Following the synthesiser architecture, Chapter 3 progressed to circuit design

techniques. Minimising component count was highlighted as a means to

miniaturising the synthesiser’s overall size and weight. The RF circuit designs also

rely on a wide range of topologies and substrates in order to extract maximum

performance from each circuit in as little space as possible. The chapter concluded

with a discussion of the system’s power and control circuits.

Chapter 4 addressed the synthesiser package design. Different packaging methods

were considered, but the Microwave Supercomponent approach was finally selected

Chapter 6: Conclusion


because of a combination of performance advantages and compatibility with existing

Micreo processes. The remainder of Chapter 4 was spent demonstrating design

techniques which could be used to maximise the space efficiency, the electrical and

thermal performance and the manufacturability of the synthesiser.

Finally, Chapter 5 presented results for two prototype synthesisers. These results

confirmed that the project had accomplished all of its primary and secondary

performance requirements:

- Wide frequency range from low MHz to > 40 GHz?

- Maximum package size 150 100 30 mm?

- Frequency resolution better than 1 MHz?

- Power Consumption less than 15 W?

In those areas where the synthesiser performance did not meet the requirements, the

discrepancy was investigated further and a root cause established. With further

engineering development work, the synthesiser will meet these requirements as well,

without compromising any of the primary and secondary performance requirements.

Table 6.1 repeats the comparison first shown in Table 2.2, but with actual results for

this project.


97 D. Enchelmaier: A Wideband Frequency Synthesiser for High Reliability Applications

Table 6.1: Comparison of commercial products’ specifications with the project results

Parameter S

pec

tru

m

Mic

row

ave

Cra

ne

Sig

nal

Tec

hn

olog

ies

Tra

k

Mic

row

ave

Mic

ro L

amb

da

Wir

eles

s

VID

A P

rod

uct

s

Pro

ject

Res

ult

s

Units

Model No. 310-027

007-002

6139-

6458-00

SYN111 MLSE-

0122

Hammer-

head

Frequency 0.4-18 2-18 2-18 1-22 11-24 Low MHz

to

> 40 GHz

GHz

RF Power +10 +13 +25 +17 +13 +10 dBm

Speed 0.075 0.1 6 31 30 0.75 ms

Resolution 1 10 1 1 x 10-6 0.2 < 1 MHz

DC Power 10 30 52 41.5 9 14.7 W

Temperature 0 to +75 -40 to +85 -40 to +90 0 to +70 -10 to +70 -54 to +71 C

Dimensions 235

194.3

33

184.15

114.3

34

152.4

127

68.6

177.8

127

50.8

146

69.85

31

150

100

30

mm

This thesis is not the last word in wideband frequency synthesiser miniaturisation.

Already, engineering development areas have been identified to improve RF

performance. As fundamental research leads to material and circuit technology

advances, there will be scope to improve the synthesiser’s performance, efficiency,

or size – maybe even all three at once. However, for the moment, the synthesiser

presented in this thesis is state of the art, and sets a new benchmark for future

miniaturised designs to be compared with.


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