a flexible simulator for control- dominated distributed real-time systems johannes petersson...
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A flexible simulator for control-A flexible simulator for control-dominated distributed real-time dominated distributed real-time
systemssystems
A flexible simulator for control-A flexible simulator for control-dominated distributed real-time dominated distributed real-time
systemssystems
Johannes PeterssonIDA/SaS/ESLAB
Johannes PeterssonIDA/SaS/ESLAB
Master’s Thesis presentationMaster’s Thesis presentation
ExaminerPetru ElesExaminerPetru Eles
SupervisorPaul PopSupervisorPaul Pop
22Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
OutlineOutline
Introduction Control-dominated systems Modelling Embedded system design Simulation A simulator for control-dominated systems Experimental results Conclusion and future work
Introduction Control-dominated systems Modelling Embedded system design Simulation A simulator for control-dominated systems Experimental results Conclusion and future work
33Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
IntroductionIntroduction
Embedded systems
Motivation Test for correctness Validate timing behaviour Cost, size and power reduction
Embedded systems
Motivation Test for correctness Validate timing behaviour Cost, size and power reduction
44Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Control-dominated systemsControl-dominated systems
Embedded systemsEmbedded systems
Real-time systemsHomogeneous or heterogeneous
Real-time systemsHomogeneous or heterogeneous
Distributed R-T SystemsDistributed R-T Systems
Control-dominated systemsControl-dominated systems
55Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Control-dominated systemsControl-dominated systems
System overview System overview Control function Control function
Modes
Controller
Physicalenvironment
User
Actuators Sensors
Switches Instruments
Desired outputDesired output Actual outputActual output
Leads to the need of iterative design stepsLeads to the need of iterative design steps
66Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
ModellingModelling
System model System model
CA
N
TT
PCAN C
AN
TTP CA
N
TTPTasks Tasks
Tasks
Tas
ksT
asks
Distributed Heterogeneous Mapped WCET Scheduled
Distributed Heterogeneous Mapped WCET Scheduled
77Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
ModellingModelling
Application model Application model
Conditional Process Graph• Processes
• Conditions
• Mapping
• Resources
• Sensors
• Actuators
• Functionality
Conditional Process Graph• Processes
• Conditions
• Mapping
• Resources
• Sensors
• Actuators
• Functionality
P0
Sensor
Actuator
P1
P3P2
P4
Resource 1
Resource 2
while (0!=1) { ...}
A -A
88Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
P4P4 P5P5
P7P7
P13P13
P15P15
First processor Second processor ASIC
CC
DD
P0
P18
P1P1
P2P2 P3P3
P6P6
P8P8 P9P9
P10P10
P11P11
P12P12
P14P14 P16P16
P17P17
C
KK
P0
P18
P1
P2 P3
P6
P8 P9
P10
P11
P12
P14 P16
P17
Subgraph corresponding to DCK
Conditional Process GraphConditional Process Graph
99Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Embedded system designEmbedded system design
Design flow Design transformations
Functional partitioning Allocation and mapping
Scheduling
Design flow Design transformations
Functional partitioning Allocation and mapping
Scheduling
1010Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Design flowDesign flow
Design steps Design steps
Systemspecification
Architectureselection
Partitioning
Scheduling
Hardwaresynthesis
Softwaresynthesis
Integration
Simulation
1111Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Design transformationsDesign transformations
Functional partitioning Functional partitioning
Split processes Split processes
Merge processes Merge processes
1212Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Design transformationsDesign transformations
Allocation and mapping Allocation and mapping
Allocating resources Mapping processes
Allocating resources Mapping processes
Resource
Resource
Resource
Tasks
P1
P2 P3
P4
1313Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Design tasksDesign tasks
Scheduling Scheduling
Tasks
Resources
Schedule table
Decide on a scheduling algorithm and perform the scheduling
Pre-emptive / non pre-emptive
Dynamic / static
Decide on a scheduling algorithm and perform the scheduling
Pre-emptive / non pre-emptive
Dynamic / static
1414Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Simulation introductionSimulation introduction
Discrete- and continuous-time Discrete- and continuous-time
ActuatorsSensors
Tasks
Discrete-time
Continuous-time Vehicle
Evaluate-update Discrete events Evaluate phase Update phase
Evaluate-update Discrete events Evaluate phase Update phase
ActuatorP1 P2Senso
rP1 P2 ActuatorSensor
1515Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Related workRelated work
Simulators reviewed True Time The Network Simulator SystemC’s simulator engine Etc.
Extended Task Graphs (eTG) Process graph with conditional constructs eTG to SystemC translator
• Stephan Klaus, Automatic generation of scheduled SystemC models
• Doesn’t consider the conditional constructs• Inspirational source
Simulators reviewed True Time The Network Simulator SystemC’s simulator engine Etc.
Extended Task Graphs (eTG) Process graph with conditional constructs eTG to SystemC translator
• Stephan Klaus, Automatic generation of scheduled SystemC models
• Doesn’t consider the conditional constructs• Inspirational source
1616Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
SystemCSystemC
Basics Basics
Provides an evaluate-update simulation engine Possible to implement any scheduling policy Models both hardware and software Work at different abstraction levels
Provides an evaluate-update simulation engine Possible to implement any scheduling policy Models both hardware and software Work at different abstraction levels
A C/C++ library A C/C++ library
A de facto open source standard A modelling platform and language for system-
level co-design Spans from concept to implementation
A de facto open source standard A modelling platform and language for system-
level co-design Spans from concept to implementation
1717Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Module 1 Module 2
SystemC ConceptsSystemC Concepts
Hierarchical modules Hierarchical modules May contain processes and other modules
• SC_MODULE
May contain processes and other modules• SC_MODULE
Communication Communication The modules and processes communicate
through signals passed through ports The modules and processes communicate
through signals passed through ports
Three types of processes Three types of processes Asynchronous-function (SC_METHOD)
Asynchronous-thread (SC_THREAD)
Synchronous-thread (SC_CTHREAD)
Asynchronous-function (SC_METHOD)
Asynchronous-thread (SC_THREAD)
Synchronous-thread (SC_CTHREAD)
1818Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
A simulator for control-dominated systemsA simulator for control-dominated systems
Overview Overview
Schedulingprogram
P0
Sensor
Actuator
P1
P3P2
P4
Resource 1
Resource 2
while (0!=1) { ...}
graph.xml
tasks.xmlallocation.xml graph.xml
allocation.xml
schedule.xml
schedule.xml
cpg2scThe SystemC
generator
ExecutableSystemC
code
1919Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
A simulator for control-dominated systemsA simulator for control-dominated systems
Representation Representation
P0
Sensor
Actuator
P1
P3P2
P4
Resource 1
Resource 2
while (0!=1) { ...}
Tasks.xml<task>
<name>Task_01</name>
<wcet>5</wcet>
<condition>Cond_A</condition>
<sensor>Sensor_01</sensor>
<actuator>null</actuator>
<code>
<![CDATA[ while (0!=1) { ... } ]]>
</code>
</task>
Tasks.xml<task>
<name>Task_01</name>
<wcet>5</wcet>
<condition>Cond_A</condition>
<sensor>Sensor_01</sensor>
<actuator>null</actuator>
<code>
<![CDATA[ while (0!=1) { ... } ]]>
</code>
</task>
Graph.xml<task>
<name>Task_01</name>
<wcet>5</wcet>
</task>
<edge>
<name>Arc_01</name>
<wcet>1</wcet>
<connects>
<from>Task_01</from>
<to>Task_02</to>
</connects>
</edge>
Graph.xml<task>
<name>Task_01</name>
<wcet>5</wcet>
</task>
<edge>
<name>Arc_01</name>
<wcet>1</wcet>
<connects>
<from>Task_01</from>
<to>Task_02</to>
</connects>
</edge>graph.xml
tasks.xmlallocation.xml
Allocation.xml<processor>
<name>PR2</name>
<tasks>
<task>Task_01</task>
</tasks>
</processor>
<bus>
<name>B1</name>
<edges>
<edge>Arc_01</edge>
</edges>
</bus>
Allocation.xml<processor>
<name>PR2</name>
<tasks>
<task>Task_01</task>
</tasks>
</processor>
<bus>
<name>B1</name>
<edges>
<edge>Arc_01</edge>
</edges>
</bus>
2020Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
A simulator for control-dominated systemsA simulator for control-dominated systems
Scheduling Scheduling
Schedulingprogram
graph.xml
allocation.xml
schedule.xml
Schedule.xml<column>
<start_time unit=”ms”>10
</start_time>
<conditions>
<cond>!Cond_A</cond>
<cond>Cond_B</cond>
<tasks>
<task>Task_03</task>
</tasks>
</conditions>
</column>
Schedule.xml<column>
<start_time unit=”ms”>10
</start_time>
<conditions>
<cond>!Cond_A</cond>
<cond>Cond_B</cond>
<tasks>
<task>Task_03</task>
</tasks>
</conditions>
</column>
process True C C & D C & -D
P1 0
P2 5
P4 14 14
P5 45 45
P6 51 50
P7 3
2121Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
A simulator for control-dominated systemsA simulator for control-dominated systems
cpg2sc cpg2sc
graph.xml
tasks.xmlallocation.xml
schedule.xml
cpg2scThe SystemC
generator
ExecutableSystemC
code
Tasks Stored in one SC_Module
• Consist of several SC_Thread
Controller Stored in one SC_Module
• Consist of one SC_Thread
Main program One SC_Main function
• Binds all ports to signals
• Starts the simulation
Tasks Stored in one SC_Module
• Consist of several SC_Thread
Controller Stored in one SC_Module
• Consist of one SC_Thread
Main program One SC_Main function
• Binds all ports to signals
• Starts the simulation
2222Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
ImplementationImplementation
A day at work.
A day at work.
2323Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Simulation resultsSimulation results
Basic setup: Part of a Cruise Controller Basic setup: Part of a Cruise Controller
P1
P3
P7
P11
P13
P15
P2
P5
P9
P6
P14
P4
P0A A
P12
P10P8
Sensor
Actuator1 Actuator4
Actuator3
Actuator2
Resource 1 Resource 2
2424Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Simulation resultsSimulation results
Functional partitioning Functional partitioning
P1
P3
P7
P11
P13
P15
P2
P5
P9
P6
P14
P4
P0A A
P12
P10P8
Sensor
Actuator1 Actuator4
Actuator3
Actuator2
Resource 1 Resource 2
P1
P7
P9
P2
P8
P0A A
Sensor
Actuator1 Actuator4
Actuator3
Actuator2
Resource 1 Resource 2
P4
P3 P5
P6
Throttle angleThrottle angle Fuel injectionFuel injection
2525Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Simulation resultsSimulation results
Conditions and resource allocation Conditions and resource allocation
P1
P3
P7
P11
P13
P15
P2
P5
P9
P6
P14
P4
P0
P12
P10P8
Sensor
Actuator1 Actuator4
Actuator3
Actuator2
Resource 1 Resource 2
P1
P3
P7
P11
P13
P15
P2
P5
P9
P6
P14
P4
P0A A
P12
P10P8
Sensor
Actuator1 Actuator4
Actuator3
Actuator2
Resource 1
P1
P3
P7
P11
P13
P15
P2
P5
P9
P6
P14
P4
P0
P12
P10P8
Sensor
Actuator1 Actuator4
Actuator3
Actuator2
Resource 1
Fuel injectionFuel injection
2626Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Simulation resultsSimulation results
Mapping Mapping
P1
P3
P7
P11
P13
P15
P2
P5
P9
P6
P14
P4
P0A A
P12
P10P8
Sensor
Actuator1 Actuator4
Actuator3
Actuator2
Resource 1
P1
P3
P7
P11
P13
P15
P2
P5
P9
P6
P14
P4
P0
P12
P10P8
Sensor
Actuator1 Actuator4
Actuator3
Actuator2
Resource 1 Resource 2
P1
P3
P7
P11
P13
P15
P2
P5
P9
P6
P14
P4
P0A A
P12
P10P8
Sensor
Actuator1 Actuator4
Actuator3
Actuator2
Resource 1 Resource 2
Resource 1 Resource 2
Fuel injectionFuel injection
2727Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Simulation resultsSimulation results Waveform diagram Waveform diagram
2828Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Conclusion and future workConclusion and future work
Conclusion Implemented a simulator for control
dominated distributed real-time systems SystemC used as the simulator’s engine Successfully used in evaluating several design
transformations Future work
Add more scheduling policies• Fixed-priority pre-emptive scheduling
Refine communication• TTP, CAN, etc.
Conclusion Implemented a simulator for control
dominated distributed real-time systems SystemC used as the simulator’s engine Successfully used in evaluating several design
transformations Future work
Add more scheduling policies• Fixed-priority pre-emptive scheduling
Refine communication• TTP, CAN, etc.
2929Johannes Petersson, IDA/SaS/ESLABJohannes Petersson, IDA/SaS/ESLAB Master’s Thesis presentation 2003.04.10Master’s Thesis presentation 2003.04.10
Thank youThank you
Thanks to everybody for listening
Thanks to Petru Eles and Paul Pop
Thanks to everybody for listening
Thanks to Petru Eles and Paul Pop