7 asynchronous counter: realization of 4-bit counter · to design and setup asynchronous up...

7 Asynchronous Counter: Realization of 4-bit counter

Aim:To design and setup asynchronous Up Counter/Down Counter.

Components required:Digital IC trainer kit,IC 7473 dual JK master slave flipflop with reset, IC 7400 quad 2 input NAND,IC7486 Quad 2 input EXOR.

Toggle Flip-Flop:

Another type of digital device that can be used for frequency division is the T-type or Toggleflip-flop. With a slight modification to a standard JK flip-flop, we can construct a new type of flip-flopcalled a Toggle flip-flop. Toggle flip flops can be made from D-type flip-flops as shown above, or fromstandard JK flip-flops such as the 74LS73. The result is a device with only two inputs, the Toggle inputitself and the negative controlling Clock input as shown.

A Toggle flip-flop gets its name from the fact that the flip-flop has the ability to toggle or switchbetween its two different states, the toggle state and the memory state. Since there are only two states,a T-type flip-flop is ideal for use in frequency division and binary counter design.

Binary ripple counters can be built using Toggle or T-type flip-flops by connecting the output of oneto the clock input of the next. Toggle flip-flops are ideal for building ripple counters as it toggles fromone state to the next, (HIGH to LOW or LOW to HIGH) at every clock cycle so simple frequencydivider and ripple counter circuits can easily be constructed using standard T-type flip-flop circuits.Ifwe connect together in series, two T-type flip-flops the initial input frequency will be divided-by-two bythe first flip-flop ( f 2 ) and then divided-by-two again by the second flip-flop ( f 2 ) 2, giving anoutput frequency which has effectively been divided four times, then its output frequency becomes onequarter value (25%) of the original clock frequency, ( f 4 ).Each time we add another toggle or T-typeflip-flop to the chain, the output clock frequency is halved or divided-by-2 again and so on, giving anoutput frequency of 2n where n is the number of flip-flops used in the sequence.

Then the Toggle or T-type flip-flop is an edge triggered divide-by-2 device based upon the standardJK-type flip flop and which is triggered on the rising edge of the clock signal. The result is that each bitmoves right by one flip-flop. All the flip-flops can be asynchronously reset and can be triggered toswitch on either the leading or trailing edge of the input clock signal making it ideal for FrequencyDivision.This type of counter circuit used for frequency division is commonly known as anAsynchronous 3-bit Binary Counter as the output on QA to QC, which is 3 bits wide, is a binary countfrom 0 to 7 for each clock pulse. In an asynchronous counter, the clock is applied only to the first stagewith the output of one flip-flop stage providing the clocking signal for the next flip-flop stage andsubsequent stages derive the clock from the previous stage with the clock pulse being halved by eachstage.

Logic Circuit Design Lab www.electronicsforktu.com Page 1

Fig. 7.1: A two-bit asynchronouscounter is shown on the right. Theexternal clock is connected to theclock input of the first flip-flop (FF0)only. So, FF0 changes state atthe falling edge of each clock pulse,but FF1 changes only when triggeredby the falling edge of the Q outputof FF0. Because of the inherentpropagation delay through a flip-flop,the transition of the input clock pulseand a transition of the Q output of FF0can never occur at exactly the sametime. Therefore, the flip-flops cannotbe triggered simultaneously, producingan asynchronous operation.

Fig. 7.2: Frequency division using 4bit asynchronous counter


This arrangement is commonly known as Asynchronous as each clocking event occurs independentlyas all the bits in the counter do not all change at the same time. As the counter counts sequentially inan upwards direction from 0 to 7. This type of counter is also known as an up or forward counter(CTU) or a 3-bit Asynchronous Up Counter. The three-bit asynchronous counter shown is typical anduses flip-flops in the toggle mode. Asynchronous Down counters (CTD) are also available.

Binary Counters:

Then we can see that a counter is nothing more than a specialized register or pattern generator thatproduces a specified output pattern or sequence of binary values (or states) upon the application of aninput pulse signal called the Clock.The clock is actually used for data transfer in these applications.Typically, counters are logic circuits that can increment or decrement a count by one but when used asasynchronous divide-by-n counters they are able to divide these input pulses producing a clock divisionsignal.

Counters are formed by connecting flip-flops together and any number of flip-flops can be connectedor cascaded together to form a divide-by-n binary counter where n is the number of counter stages usedand which is called the Modulus. The modulus or simply MOD of a counter is the number of outputstates the counter goes through before returning itself back to zero, ie, one complete cycle.Then acounter with three flip-flops like the circuit above will count from 0 to 7 ie, 23-1. It has eight differentoutput states representing the decimal numbers 0 to 7 and is called a Modulo-8 or MOD-8 counter. Acounter with four flip-flops will count from 0 to 15 and is therefore called a Modulo-16counter and soon.

An example of this is given as.

3-bit Binary Counter = 23 = 8 (modulo-8 or MOD-8)



The Modulo number can be increased by adding more flip-flops to the counter and cascading is amethod of achieving higher modulus counters. Then the modulo or MOD number can simply be writtenas: MOD number = 2n.

4-bit Modulo-16 Counter.

Multi-bit asynchronous counters connected in this manner are also called Ripple Counters or rippledividers because the change of state at each stage appears to ripple itself through the counter from theLSB output to its MSB output connection. Ripple counters are available in standard IC form, from the74LS393 Dual 4-bit counter to the 74HC4060, which is a 14-bit ripple counter with its own built inclock oscillator and produce excellent frequency division of the fundamental frequency.


Fig. 7.3:


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7.1 4bit asynchronous up counter.

Fig. 7.4: Consider a 3 bit up countsequence after 7 the counter is reset to0.D represents the clock pulse. Notethat A(LSB) Toggles for every clockpulse.SO we can keep it in toggle mode.Now B toggles whenever A changes from1 to 0.Since we have -ve edge triggeredflipfops we can connect the output offirst flipflop(A) to clock input of nextflipflop(B).

Procedure:

Assemble the circuit neatly on the breadboard.

Connect the switch SW1 to ground (logic 0). Since SW1 is connected to R of all flip-flops all theflip-flop outputs gets reset(Q=0).

Now to resume normal operation we need to make R high. So flip the switch to high (logic1).

Now apply the clock pulse and verify the output patterns.


Fig. 7.5:


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7.2 4bit asynchronous down counter.

Fig. 7.6: Consider a 3 bit up countsequence after 7 the counter is reset to0.D represents the clock pulse. Notethat A(LSB) Toggles for every clockpulse.SO we can keep it in toggle mode.Now B toggles whenever A changes from1 to 0.Since we have -ve edge triggeredflipfops we can connect the output offirst flipflop(A) to clock input of nextflipflop(B).

Procedure:

Assemble the circuit neatly on the breadboard.

Connect the switch SW1 to ground (logic 0). Since SW1 is connected to R of all flip-flops all theflip-flop outputs gets reset(Q=0).

Now to resume normal operation we need to make R high. So flip the switch to high (logic1).

Now apply the clock pulse and verify the output patterns.

Result:

Designed and setup asynchronous up/down counter and obtained the result.


A Answers to Additional Questions:

A.1 Asynchronous counters:

1. Advantages of Asynchronous Counters:

Asynchronous Counters can easily be made from Toggle or D-type flip-flops. They are called Asynchronous Counters because the clock input of the flip-flops are not all

driven by the same clock signal.

Each output in the chain depends on a change in state from the previous flip-flops output. Asynchronous counters are sometimes called ripple counters because the data appears to ripple

from the output of one flip-flop to the input of the next.

They can be implemented using divide-by-n counter circuits. Truncated counters can produce any modulus number count.

Disadvantages of Asynchronous Counters:

An extra re-synchronizing output flip-flop may be required. To count a truncated sequence not equal to 2n, extra feedback logic is required. Counting a large number of bits, propagation delay by successive stages may become

undesirably large.

This delay gives them the nickname of Propagation Counters. Counting errors occur at high clocking frequencies. Synchronous Counters are faster and more reliable as they use the same clock signal for all

flip-flops.

Counting errors occur at high clocking frequencies.

Following diagram shows how errors can occur at high frequencies. We have already seen how anasynchronous counter worked perfect at low frequencies. But as frequencies approached MHz (thetime period of clock signals approached that of propagation delay of flipflops the counter becomesunusable). Shows below the case of 10MHz and as it reaches 20MHz the counter pretty muchbecomes unusable.


Fig. A.1: Asynchronous counter with delay:


2. Design a MOD-10 asynchronous counter using D flipflops.

We can use a D Flip flop instead of JK flipflop as long as each flip flop works in toggle mode. Nowto connect a D flip flop in toggle mode connect the Q input to D input of flip flop. This willconvert D flipflop to toggle mode. Now proceed as in a mod-10 decade counter using JK flipflop.

Fig. A.2: Asynchronous counter using D flip flops:


B LTspice Simulations.

B.1 Asynchronous Counter: Realization of 4-bit up and down counter:

Fig. B.1: 4bit asynchronous up counter.

Fig. B.2: Timing diagram for 4bit asynchronous up counter:

LTspice Simulation File:


Version 4SHEET 1 1376 680WIRE -128 -128 -128 -160WIRE 240 -128 -128 -128WIRE 592 -128 240 -128WIRE 960 -128 592 -128WIRE -384 -112 -416 -112WIRE -272 -112 -304 -112WIRE -256 -112 -272 -112WIRE -272 -64 -272 -112WIRE 496 -48 480 -48WIRE 848 -48 832 -48WIRE 1280 -48 1248 -48WIRE 144 -32 128 -32WIRE 240 -16 240 -128WIRE 288 -16 240 -16WIRE 592 -16 592 -128WIRE 640 -16 592 -16WIRE 960 -16 960 -128WIRE 1024 -16 960 -16WIRE -128 0 -128 -128WIRE -64 0 -128 0WIRE 480 0 480 -48WIRE 560 0 480 0WIRE 832 0 832 -48WIRE 880 0 832 0WIRE 1248 0 1248 -48WIRE 1248 0 1216 0WIRE 128 16 128 -32WIRE 176 16 128 16WIRE -272 32 -272 0WIRE 176 32 176 16WIRE 288 32 176 32WIRE 560 32 560 0WIRE 640 32 560 32WIRE 880 32 880 0WIRE 1024 32 880 32WIRE -464 48 -464 16WIRE -64 48 -96 48WIRE 240 80 240 -16WIRE 288 80 240 80WIRE 592 80 592 -16WIRE 640 80 592 80WIRE 960 80 960 -16WIRE 1024 80 960 80WIRE -128 96 -128 0WIRE -64 96 -128 96WIRE -464 160 -464 128WIRE 384 160 384 144WIRE 384 160 32 160WIRE 736 160 736 144WIRE 736 160 384 160WIRE 1120 160 1120 144WIRE 1120 160 736 160WIRE 1120 192 1120 160WIRE 656 256 608 256WIRE 768 256 736 256WIRE -464 272 -464 256WIRE -96 272 -96 48WIRE -96 272 -464 272WIRE 656 288 608 288WIRE 768 288 736 288WIRE -464 304 -464 272WIRE 656 320 608 320WIRE 768 320 736 320WIRE 656 352 608 352WIRE 768 352 736 352WIRE 656 384 608 384WIRE 768 384 736 384WIRE -464 416 -464 384FLAG -464 160 0FLAG -464 16 HFLAG -464 416 0FLAG -464 256 CLKFLAG -416 -112 HIOPIN -416 -112 InFLAG -272 32 0FLAG -256 -112 SET/PREFLAG 144 -32 Q0IOPIN 144 -32 BiDirFLAG 496 -48 Q1IOPIN 496 -48 BiDirFLAG 848 -48 Q2IOPIN 848 -48 BiDirFLAG 608 288 Q0IOPIN 608 288 InFLAG 608 320 Q1IOPIN 608 320 InFLAG 608 352 Q2IOPIN 608 352 InFLAG 608 256 CLKIOPIN 608 256 InFLAG 768 256 CLKo/pIOPIN 768 256 OutFLAG 768 288 Q0o/pIOPIN 768 288 OutFLAG 768 320 Q1o/pIOPIN 768 320 OutFLAG 768 352 Q2o/pIOPIN 768 352 OutFLAG 1120 192 SET/PREFLAG 1280 -48 Q3IOPIN 1280 -48 BiDirFLAG 608 384 Q3IOPIN 608 384 InFLAG 768 384 Q3o/pIOPIN 768 384 OutFLAG -128 -160 HIOPIN -128 -160 InSYMBOL voltage -464 288 R0WINDOW 123 0 0 Left 2WINDOW 39 0 0 Left 2SYMATTR InstName V1SYMATTR Value PULSE(5V 0V 0 1ns 1ns 0.5ms 1ms)SYMBOL voltage -464 32 R0SYMATTR InstName V2SYMATTR Value 5VSYMBOL res -288 -128 R90WINDOW 0 0 56 VBottom 2WINDOW 3 32 56 VTop 2SYMATTR InstName R1SYMATTR Value 1kSYMBOL cap -288 -64 R0SYMATTR InstName C1SYMATTR Value 1FSYMBOL dview5 672 400 R0SYMATTR InstName U4SYMBOL Digital\ Lab\\74HC\\74hc107 32 -64 R0SYMATTR InstName U1SYMBOL Digital\ Lab\\74HC\\74hc107 384 -80 R0SYMATTR InstName U2SYMBOL Digital\ Lab\\74HC\\74hc107 736 -80 R0SYMATTR InstName U3SYMBOL Digital\ Lab\\74HC\\74hc107 1120 -80 R0SYMATTR InstName U5TEXT 80 408 Left 2 !.tran 20ms uicTEXT 80 272 Left 2 !.lib 74hc.libTEXT 80 304 Left 2 !.lib dview.lib

4bit up counter illustrating the delay problem.As the frequency approaches very high around MHzrange.

Fig. B.3: 4bit asynchronous up counter.

Fig. B.4: Timing diagram for 4bit asynchronous up counter:



Version 4SHEET 1 1376 680WIRE -128 -128 -128 -160WIRE 240 -128 -128 -128WIRE 592 -128 240 -128WIRE 960 -128 592 -128WIRE -384 -112 -416 -112WIRE -272 -112 -304 -112WIRE -256 -112 -272 -112WIRE -272 -64 -272 -112WIRE 496 -48 480 -48WIRE 848 -48 832 -48WIRE 1280 -48 1248 -48WIRE 144 -32 128 -32WIRE 240 -16 240 -128WIRE 288 -16 240 -16WIRE 592 -16 592 -128WIRE 640 -16 592 -16WIRE 960 -16 960 -128WIRE 1024 -16 960 -16WIRE -128 0 -128 -128WIRE -64 0 -128 0WIRE 480 0 480 -48WIRE 560 0 480 0WIRE 832 0 832 -48WIRE 880 0 832 0WIRE 1248 0 1248 -48WIRE 1248 0 1216 0WIRE 128 16 128 -32WIRE 176 16 128 16WIRE -272 32 -272 0WIRE 176 32 176 16WIRE 288 32 176 32WIRE 560 32 560 0WIRE 640 32 560 32WIRE 880 32 880 0WIRE 1024 32 880 32WIRE -464 48 -464 16WIRE -64 48 -96 48WIRE 240 80 240 -16WIRE 288 80 240 80WIRE 592 80 592 -16WIRE 640 80 592 80WIRE 960 80 960 -16WIRE 1024 80 960 80WIRE -128 96 -128 0WIRE -64 96 -128 96WIRE -464 160 -464 128WIRE 384 160 384 144WIRE 384 160 32 160WIRE 736 160 736 144WIRE 736 160 384 160WIRE 1120 160 1120 144WIRE 1120 160 736 160WIRE 1120 192 1120 160WIRE 656 256 608 256WIRE 768 256 736 256WIRE -464 272 -464 256WIRE -96 272 -96 48WIRE -96 272 -464 272WIRE 656 288 608 288WIRE 768 288 736 288WIRE -464 304 -464 272WIRE 656 320 608 320WIRE 768 320 736 320WIRE 656 352 608 352WIRE 768 352 736 352WIRE 656 384 608 384WIRE 768 384 736 384WIRE -464 416 -464 384FLAG -464 160 0FLAG -464 16 HFLAG -464 416 0FLAG -464 256 CLKFLAG -416 -112 HIOPIN -416 -112 InFLAG -272 32 0FLAG -256 -112 SET/PREFLAG 144 -32 Q0IOPIN 144 -32 BiDirFLAG 496 -48 Q1IOPIN 496 -48 BiDirFLAG 848 -48 Q2IOPIN 848 -48 BiDirFLAG 608 288 Q0IOPIN 608 288 InFLAG 608 320 Q1IOPIN 608 320 InFLAG 608 352 Q2IOPIN 608 352 InFLAG 608 256 CLKIOPIN 608 256 InFLAG 768 256 CLKo/pIOPIN 768 256 OutFLAG 768 288 Q0o/pIOPIN 768 288 OutFLAG 768 320 Q1o/pIOPIN 768 320 OutFLAG 768 352 Q2o/pIOPIN 768 352 OutFLAG 1120 192 SET/PREFLAG 1280 -48 Q3IOPIN 1280 -48 BiDirFLAG 608 384 Q3IOPIN 608 384 InFLAG 768 384 Q3o/pIOPIN 768 384 OutFLAG -128 -160 HIOPIN -128 -160 InSYMBOL voltage -464 288 R0WINDOW 123 0 0 Left 2WINDOW 39 0 0 Left 2SYMATTR InstName V1SYMATTR Value PULSE(5V 0V 0 1ns 1ns .05us 0.1us)SYMBOL voltage -464 32 R0SYMATTR InstName V2SYMATTR Value 5VSYMBOL res -288 -128 R90WINDOW 0 0 56 VBottom 2WINDOW 3 32 56 VTop 2SYMATTR InstName R1SYMATTR Value 1kSYMBOL cap -288 -64 R0SYMATTR InstName C1SYMATTR Value 1pFSYMBOL dview5 672 400 R0SYMATTR InstName U4SYMBOL Digital\ Lab\\74HC\\74hc107 32 -64 R0SYMATTR InstName U1SYMBOL Digital\ Lab\\74HC\\74hc107 384 -80 R0SYMATTR InstName U2SYMBOL Digital\ Lab\\74HC\\74hc107 736 -80 R0SYMATTR InstName U3SYMBOL Digital\ Lab\\74HC\\74hc107 1120 -80 R0SYMATTR InstName U5TEXT 80 408 Left 2 !.tran 2us uicTEXT 80 272 Left 2 !.lib 74hc.libTEXT 80 304 Left 2 !.lib dview.lib

Fig. B.5: 4bit asynchronous down counter.

Fig. B.6: Timing diagram for 4bit asynchronous down counter:



Version 4SHEET 1 1376 680WIRE -128 -128 -128 -160WIRE 240 -128 -128 -128WIRE 592 -128 240 -128WIRE 960 -128 592 -128WIRE -384 -112 -416 -112WIRE -272 -112 -304 -112WIRE -256 -112 -272 -112WIRE -272 -64 -272 -112WIRE 496 -48 480 -48WIRE 848 -48 832 -48WIRE 144 -32 128 -32WIRE 1280 -32 1248 -32WIRE 240 -16 240 -128WIRE 288 -16 240 -16WIRE 592 -16 592 -128WIRE 640 -16 592 -16WIRE 960 -16 960 -128WIRE 1024 -16 960 -16WIRE -128 0 -128 -128WIRE -64 0 -128 0WIRE 480 0 480 -48WIRE 832 0 832 -48WIRE 1248 0 1248 -32WIRE 1248 0 1216 0WIRE 128 16 128 -32WIRE -272 32 -272 0WIRE 288 32 192 32WIRE 640 32 560 32WIRE 1024 32 912 32WIRE -464 48 -464 16WIRE -64 48 -96 48WIRE 560 64 560 32WIRE 560 64 480 64WIRE 912 64 912 32WIRE 912 64 832 64WIRE 192 80 192 32WIRE 192 80 128 80WIRE 240 80 240 -16WIRE 288 80 240 80WIRE 592 80 592 -16WIRE 640 80 592 80WIRE 960 80 960 -16WIRE 1024 80 960 80WIRE -128 96 -128 0WIRE -64 96 -128 96WIRE -464 160 -464 128WIRE 384 160 384 144WIRE 384 160 32 160WIRE 736 160 736 144WIRE 736 160 384 160WIRE 1120 160 1120 144WIRE 1120 160 736 160WIRE 1120 192 1120 160WIRE 656 256 608 256WIRE 768 256 736 256WIRE -464 272 -464 256WIRE -96 272 -96 48WIRE -96 272 -464 272WIRE 656 288 608 288WIRE 768 288 736 288WIRE -464 304 -464 272WIRE 656 320 608 320WIRE 768 320 736 320WIRE 656 352 608 352WIRE 768 352 736 352WIRE 656 384 608 384WIRE 768 384 736 384WIRE -464 416 -464 384FLAG -464 160 0FLAG -464 16 HFLAG -464 416 0FLAG -464 256 CLKFLAG -416 -112 HIOPIN -416 -112 InFLAG -272 32 0FLAG -256 -112 SET/PREFLAG 144 -32 Q0IOPIN 144 -32 BiDirFLAG 496 -48 Q1IOPIN 496 -48 BiDirFLAG 848 -48 Q2IOPIN 848 -48 BiDirFLAG 608 288 Q0IOPIN 608 288 InFLAG 608 320 Q1IOPIN 608 320 InFLAG 608 352 Q2IOPIN 608 352 InFLAG 608 256 CLKIOPIN 608 256 InFLAG 768 256 CLKo/pIOPIN 768 256 OutFLAG 768 288 Q0o/pIOPIN 768 288 OutFLAG 768 320 Q1o/pIOPIN 768 320 OutFLAG 768 352 Q2o/pIOPIN 768 352 OutFLAG 1120 192 SET/PREFLAG 1280 -32 Q3IOPIN 1280 -32 BiDirFLAG 608 384 Q3IOPIN 608 384 InFLAG 768 384 Q3o/pIOPIN 768 384 OutFLAG -128 -160 HIOPIN -128 -160 InSYMBOL voltage -464 288 R0WINDOW 123 0 0 Left 2WINDOW 39 0 0 Left 2SYMATTR InstName V1SYMATTR Value PULSE(5V 0V 0 1ns 1ns 0.5ms 1ms)SYMBOL voltage -464 32 R0SYMATTR InstName V2SYMATTR Value 5VSYMBOL res -288 -128 R90WINDOW 0 0 56 VBottom 2WINDOW 3 32 56 VTop 2SYMATTR InstName R1SYMATTR Value 1kSYMBOL cap -288 -64 R0SYMATTR InstName C1SYMATTR Value 1FSYMBOL dview5 672 400 R0SYMATTR InstName U4SYMBOL Digital\ Lab\\74HC\\74hc107 32 -64 R0SYMATTR InstName U1SYMBOL Digital\ Lab\\74HC\\74hc107 384 -80 R0SYMATTR InstName U2SYMBOL Digital\ Lab\\74HC\\74hc107 736 -80 R0SYMATTR InstName U3SYMBOL Digital\ Lab\\74HC\\74hc107 1120 -80 R0SYMATTR InstName U5TEXT 80 408 Left 2 !.tran 20ms uicTEXT 80 272 Left 2 !.lib 74hc.libTEXT 80 304 Left 2 !.lib dview.lib

C Everycircuit Simulations.

C.1 4bit Asynchronous UP/DOWN Counter:

(a) 4bit asynchronous Up Counter (b) 4bit asynchronous Down Counter

Fig. C.1: 4bit asynchronous Up/Down Counter


http://everycircuit.com/circuit/4892083472564224http://everycircuit.com/circuit/4892083472564224

Asynchronous Counter: Realization of 4-bit counter4bit asynchronous up counter.4bit asynchronous down counter.

Appendix Answers to Additional Questions:Asynchronous counters:

Appendix LTspice Simulations.Asynchronous Counter: Realization of 4-bit up and down counter:

Appendix Everycircuit Simulations.4bit Asynchronous UP/DOWN Counter:

7 asynchronous counter: realization of 4-bit counter · to design and setup asynchronous up...

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