Electronic Counters

AbstractElectronic counters come in two flavors: asynchronous and synchronous.

Asynchronous counter encode a count sequence by directly connecting flip-flops and allowing the clock-pulse to ripple through the cascade. Synchronous counters use a common clock and logic between flip-flops to encode the count sequence. Asynchronous counters are simpler because they do not require logic gates, but any latency will scale linearly with respect to the number of bits. Synchronous counters are more complex but constrain the latency. If the cumulative latency is greater than the maximum allowable cycle time, then a synchronous architecture is preferable. If the application is not sensitive to false errors produced by latency, however, an asynchronous counter alone or with over-clocking (in the event that cumulative latency is greater than the cycle time) may be feasible. Alternatively filters, such as a strobing circuit, can be used to remove erroneous outputs caused by latency from the output.

Solid State

Physics

NN PP

+-

Transistors And

diodes

Logic gates

Memory devices : Flip flops

Systems : CountersFlip Flop

FlipFlopFlipFlop

Output

Clock

Clock

Input

Output’Input 2

Counter

Electronic counter

Memory deviceFlip flop

AddressableI/O signals

Wires

ArchitectureAsynchronous Synchronous

Electronic flip-flop

0 1

State

A bit is a two-state object, such as a flip-flop.

0 1State 0

000 001 010 011 100 101 110 111 All possible information

levels for three bits

A collection of n bits can encode 2^n information

levels (states).

0 1State 0

000 001 010 011 100 101 110 111 All possible information

levels for three bits

1 2 3 4 5 6 7 8

Each information level can represent a number.

000 001 010 011 100 101 110 111

Bits oscillating with proportional frequencies encode count sequence.

Bit1

Bit2

Bit3

1 2 3 4 5 6 7 8

Counter system architecture connects bits (JK flip-flops) to produce this frequency pattern.

Bit2

Bit3

Bit1

Asynchronous

Couple two two bits so that inverse output from bit 1 is

trigger for bit 2.

“Trigger”

Inverter

Output 1 Output 2

“Trigger”Bit 1 Bit 2

Output 1

Trigger 1

Output 1

Inverted

Bit 1 output and inverted output

Output 2

Output 1

Inverted

Trigger 2

Bit 1 inverse output serves as clock for bit 2. Triggers state change at positive

going transitions.

Output 1

Output 2

2 outputs of proportional frequency produce the

count sequence

01

2

10

3

11

4

00

1

“Trigger”

“Enable”

Latency

Delay, D

But if there is a delay between command to

toggle and response …

“Trigger”

BitState

Toggle:Change State

AND

AND

JK Flip-Flop

… latency scales linearly wrt # of bits

Clock 1

Bit 1

Bit 2

Clock 2

D

D

Ideal Observed

Accumulated latency = n*d, for counter of n bits

And results in an erroneous count.

Clock 1

Bit 1

Bit 2

Clock 2

D

D

01 (2) 10 (3) 01 01 00 (1) 10

Ideal Observed

But if accumulated delay occurs before clock returns

to low state …Clock 1

Bit n

Clock n

Accumulated delay = (n-1)*d

Accumulated delay = (n)*d

… let error ripple through the system when clock is high, then read output when the

clock is low.

Clock 1

Bit 1

Bit 2

Clock 2

01 10

Low enable is

True

Then read bits to produce correct output

“Strobing” circuit

Problem: delay limits clock speed …

Clock 1

Bit n

Clock n

Cumulative delay = (n)*d

Clock frequency must be set allow cumulative delay to ripple through cascade of bits during the high level of the trigger. Thus, the length of ½ cycle > length of cumulative delay

In applications where false outputs from propagation delay produces errors and where speed is important,synchronous counter that

avoids “rippling” is preferable.

Synchronous

Couple enable to logic gate that processes output from prior bits : when all prior

bits are high, then 1 passed to bit and output toggles.

“Trigger”

PriorBits

ToggleOutput

“Inputs”

AND

AND

JK Flip-Flop

Synchronous counter: each bit holds its state until all

preceding bits are high and positive clock pulse.High

11Cloc

kCloc

k 22 33

Q2 Q3And

Clock

Q2

Q1

Q3

0 1

1

0 1 1 0 10

0 1 0 1

0

Q1

000 001 010 011 100 101 110 111 1 2 3 4 5 6 7 8

Bits flip simultaneously, with same latency :

no false outputsClock

Bit 2

Bit 3

Bit 4

Bit 1 1

1

1

0

0

Bit 4 enable:Logic gate

inputs

Bit 4 state

Time 1

1

1

1

1

1

Time 2: Flip

D: latency of flip-flop

Bit 4 trigger

Compare synchronous to asynchronous …

Clock

Bit 2

Bit 3

D

Bit 4

Bit 1

Latency for synchronous fixed and no false outputs but is synchronous is 4*D by 4th flip-flop, necessitating measures

(“strobing circuit”) to prevent errors and thus limiting speed.

Grows to 4*D

Knowing …

Clock

Bit n

Clock n

Clock

1. Cumulative latency for

asynchronous counter

2. Minimum acceptable clock speed

Maximum acceptable cycle time

Latency

Synchronous

Architecture

Is cumulative latency > maximum

cycle time? Yes

No

Do false outputs

resulting from latency cause

errors? No

Yes

Is cumulative latency < ½ maximum

cycle time?

Yes With strobing circuit to “block” output during high

level in clock cycle.

No

Asynchronous

Architecture

Decision …