42 service manual - supertvservis.cz · cabinet, on the chassis or picture tube. 3. to avoid a...

PDP4210EA

Model:

SERVICE MANUAL

Safety PrecautionTechnical SpecificationsBlock DiagramCircuit DiagramBasic Operations & Circuit DescriptionMain IC SpecificationsProduct Specification of PDP ModuleTrouble Shooting Manual of PDP ModuleSpare Part ListExploded ViewIf you forget your V-Chip PasswordSoftware Upgrade

This manual is the latest at the time of printing, and does notinclude the modification which may be made after the printing,by the constant improvement of product.

Safety Precaution

PRECAUTIONS DURINGSERVICING

1. In addition to safety, other parts and

assemblies are specified for conformance with

such regulations as those applying to spurious

radiation. These must also be replaced only

with specified replacements.

Examples: RF converters, tuner units, antenna

selection switches, RF cables, noise-blocking

capacitors, noise-blocking filters, etc.

2. Use specified internal Wiring. Note especially:

1) Wires covered with PVC tubing

2) Double insulated wires

3) High voltage leads

3. Use specified insulating materials for hazardous

live parts. Note especially:

1) Insulating Tape

2) PVC tubing

3) Spacers (insulating barriers)

4) Insulating sheets for transistors

5) Plastic screws for fixing micro switches

4. When replacing AC primary side components

(transformers, power cords, noise blocking

capacitors, etc.), wrap ends of wires securely

about the terminals before soldering.

5. Make sure that wires do not contact heat

generating parts (heat sinks, oxide metal film

resistors, fusible resistors, etc.)

6. Check if replaced wires do not contact sharply

edged or pointed parts.

7. Make sure that foreign objects (screws, solder

droplets, etc.) do not remain inside the set.

The lightning flash with arrowhead symbol,within an equilateral triangle, is intended toalert the user to the presence of uninsulated“dangerous voltage” within the product’s enclosure that may be of sufficient magnitude toconstitute a risk of electric shock to persons.

The exclamation point within an equilateraltriangle is intended to alert the user to thepresence of important operating andmaintenance (servicing) instructions in theliterature accompanying the appliance.

CAUTION: TO REDUCE THE RISK OFELECTRIC SHOCK, DO NOT REMOVE COVER(OR BACK). NO USER-SERVICEABLE PARTSINSIDE. REFER SERVICING TO QUALIFIEDSERVICE PERSONNEL ONLY.

CAUTION

RISK OF ELECTRIC SHOCKDO NOT OPEN

MAKE YOUR CONTRIBUTIONTO PROTECT THE

ENVIRONMENTUsed batteries with the ISO symbol

for recycling as well as small accumulators

(rechargeable batteries), mini-batteries (cells) and

starter batteries should not be thrown into the

garbage can.

Please leave them at an appropriate depot.

WARNING:

Before servicing this TV receiver, read the

SAFETY INSTRUCTION and PRODUCT

SAFETY NOTICE.

SAFETY INSTRUCTIONThe service should not be attempted by anyone

unfamiliar with the necessary instructions on this

apparatus. The following are the necessary

instructions to be observed before servicing.

1. An isolation transformer should be connected in

the power line between the receiver and the

AC line when a service is performed on the

primary of the converter transformer of the set.

2. Comply with all caution and safety related

provided on the back of the cabinet, inside the

cabinet, on the chassis or picture tube.

3. To avoid a shock hazard, always discharge the

picture tube's anode to the chassis ground

before removing the anode cap.

4. Completely discharge the high potential voltage

of the picture tube before handling. The picture

tube is a vacuum and if broken, the glass will

explode.

PRODUCT SAFETY NOTICE

Many electrical and mechanical parts in this

apparatus have special safety-related

characteristics.

These characteristics are offer passed

unnoticed by visual spection and the protection

afforded by them cannot necessarily be obtained

by using replacement components rates for a

higher voltage, wattage, etc.

The replacement parts which have these

special safety characteristics are identified by

marks on the schematic diagram and on the parts

list.

Before replacing any of these components,

read the parts list in this manual carefully. The

use of substitute replacement parts which do not

have the same safety characteristics as specified

in the parts list may create shock, fire, or other

hazards.

9. Must be sure that the ground wire of the AC

inlet is connected with the ground of the

apparatus properly.

5. When replacing a MAIN PCB in the cabinet,

always be certain that all protective are

installed properly such as control knobs,

adjustment covers or shields, barriers, isolation

resistor networks etc.

6. When servicing is required, observe the original

lead dressing. Extra precaution should be given

to assure correct lead dressing in the high

voltage area.

7. Keep wires away from high voltage or high

tempera ture components.

8. Before returning the set to the customer,

always perform an AC leakage current check

on the exposed metallic parts of the cabinet,

such as antennas, terminals, screwheads,metal

overlay, control shafts, etc., to be sure the set

is safe to operate without danger of electrical

shock. Plug the AC line cord directly to the

AC outlet (do not use a line isolation

transformer during this check). Use an AC

voltmeter having 5K ohms volt sensitivity or

more in the following manner.

Connect a 1.5K ohm 10 watt resistor paralleled

by a 0.15µF AC type capacitor, between a

good earth ground (water pipe, conductor etc.,)

and the exposed metallic parts, one at a time.

Measure the AC voltage across the combination

of the 1.5K ohm resistor and 0.15 uF

capacitor. Reverse the AC plug at the AC

outlet and repeat the AC voltage measurements

for each exposed metallic part.

The measured voltage must not exceed 0.3V

RMS.

This corresponds to 0.5mA AC. Any value

exceeding this limit constitutes a potential

shock hazard and must be corrected

immediately.

The resistance measurement should be done

between accessible exposed metal parts and

power cord plug prongs with the power switch

"ON". The resistance should be more than

6M ohms.

Good earth groundsuch as the waterpipe, conductor,etc.

Place this probeon each exposedmetallic part

AC VOLTMETER

AC Leakage Current Check

Technical Specifications

MODEL : PDP4210EA

42” Plasma Display

DATE FIRST ISSUED

ISSUE

1

RAISED BY

CHECKED BY

NUMBER OF PAGES

10

REVISIONS ISSUED DATE DESCRIPTION RAISED BY :

SPECIFICATION AGREED : SIGNATURE DATE

R & D DEPARTMENT

COMMERCIAL DEPARTMENT

PRODUCTION DEPARTMENT

Q/A DEPARTMENT

CUSTOMER

......................................................................................

......

............................................................................................

.............................................................................................

.............................................................................................

.............................................................................................

..............................

..............................

..............................

..............................

..............................

SPECIFICATION APPROVED : .

SIGNATURE :

DATE :

NOTE : Only documents stamped “Controlled Document” to be used for manufacture of production parts.


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NUMBER 2 OF 10 PAGES

1. Standard Test Conditions All tests shall be performed under the following conditions, unless otherwise specified. 1.1 Ambient light : 150ux (When measuring IB, the ambient luminance ≦0.1Cd/m2)

1.2 Viewing distance : 50cm in front of PDP

1.3 Warm up time : 30 minutes 1.4 PDP Panel facing : no restricted 1.5 Measuring Equipment : PC, Chroma 2225 signal generator (with Chroma digital additional card) or equivalent, Minolta CA100 photometer 1.6 Magnetic field : no restricted 1.7 Control settings : Brightness, Contrast, Tint, Color set at Center(50) 1.8 Power input : 110~120Vac,60Hz 1.9 Ambient temperature : 20°C ± 5°C (68°F ± 9°F) 1.10 Display mode : 31.5KHz/60Hz (Resolution 852 x 480) 1.11 Other conditions : 1.11.1 With image sticking protection of PDP module, the luminance will descend

by time on a same still screen and rapidly go down in 5 minutes. When measuring the color tracking and luminance of a same still screen, be sure to accomplish the measurement in one minute to ensure its accuracy. 1.11.2 Due to the structure of PDP, the extra-high-bright same screen should not hold over 5 minutes for fear of branding on the panel.


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ELECTRICAL CHARACTERISTICS 2. Power Input 2.1 Voltage : 110 ~120VAC 2.2 Input Current : 3.5A 2.3 Maximum Inrush Current : <30 A (FOR AC110V ONLY) Test condition : Measured when switched off for at least 20 mins 2.4 Frequency : 60Hz(±3Hz) 2.5 Power Consumption : ≤ 330W Test condition : full white display with maximum brightness and contrast 2.6 Power Factor : Meets IEC1000-3-2 2.7 Withstanding voltage : 1.5kVac or 2.2kVdc for 1 sec 3. Display

3.1 Screen Size : 42” Plasma display 3.2 Aspect Ratio : 16:9 3.3 Pixel Resolution : 852x480 3.4 Peak Brightness : 1000 cd/m² (Panel module without filter) 3.5 Contrast Ratio (Dark room) : 3000:1 (Panel module without filter) 3.6 Viewing Angle : Over 160° 3.7 OSD language : English,Spaish,French

4. Signal 4.1 AV & Graphic input 4.1.1 TV standard : NTSC/ATSC 4.1.2 TV Tuning system : 181CH (for NTSC), 2~69CH (for ATSC) 4.1.3 CATV : 125CH (for NTSC)

4.1.4 Composite signal : AV 4.1.5 Y,C Signal : S-Video 4.1.6 Component signal : Y, Pb/Cb, Pr/Cr, HDTV compatible 4.1.7 Graphic I/P : Analog: D-sub 15pin detachable cable Digital: DVI 4.1.8 PnP compatibility : DDC 1.0

4.1.9 I/P frequency : fH: 31.5kHz to 60kHz/fV: 56.25Hz to 75Hz (640x480 recommended)


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4.2 Audio input Audio I/P(L/Rx5) : 1 for DVI 1 for D-Sub 2 for YPbPr

1 for S-Video /AV

4.3 Audio output Audio O/P(L/Rx1) : Monitor out(L/R)

SPDIF : Optical x 1

5. Environment 5.1 Operating environment 5.1.1 Temperature : 5º to 33°C 5.1.2 Relative humidity: 20% to 85%(non-condensing) 5.2 Storage and Transport 5.2.1 Temperature : -20°C to 60°C(-4º to 140°F) 5.2.2 Relative humidity: 5% to 95% 6. Panel Characteristics 6.1 Type : LG V6 6.2 Size : 42”, 1005mm(width)x597mm(height)x61mm(depth)±1 mm) 6.3 Aspect ratio : 16:9 6.4 Viewing angle : Over 160° 6.5 Resolution : 852x480 6.6 Weight : 14.8kg ±0.5 kg (Net) 6.7 Color : 16.77 million colors by combination of 8 bits R,G,B digital

6.8 Contrast : Average 60:1 (In a bright room with 150Lux at center) Typical 3000:1 (In a dark room 1/25 White Window

pattern at center). 6.9 Peak brightness : Typical 1000cd/ (1/25 White Window) 6.10 Color Coordinate Uniformity : Contrast; Brightness and Color control

at normal setting Test Pattern : Full white pattern Average of point A,B,C,D and E +/- 0.01


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6.11 Color temperature : Contrast at center (50); Brightness center (50); Color temperature set at Natural x=0.285±0.02 y=0.293±0.02

6.12 Cell Defect Specifications Subject to Panel supplier specification as appends. 7. Front Panel Control Button 7.1 CH Up / Down Button : Push the key to changing the channel up or down. When selecting the item on OSD menu. Volume Up/ Down Button : Push the key to increase the volume up or down. When selecting the adjusting item on OSD menu increase or decrease the data-bar.

Menu Button : Enter to the OSD menu. Input Select Button : Push the key to select the input signals source.

7.2 Stand by Button : Switch on main power, or switch off to enter power Saving modes. 7.3 Main Power Switch : Turn on or off the unit. 8. OSD Function Full on screen display


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9. Agency Approvals Safety UL60950 Emissions FCC class B 10. Reliability

11.1 MTBF : 20,000 hours(Use moving picture signal at 25°C ambient) 11. Accessories : User manual x1, Remote control x1, Stand x1, Power cord x1, Battery x 2.


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NUMBER 6

13. Support the Signal Mode A. VGA and DVI mode

B. HDTV Mode (YPbPr)

- When the signal received by the Display exceeds the allowed range, a warning message “Main Not Support!” shall appear on the screen. - You can confirm the input signal format from the on-screen.

NO. ResolutionHorizontal Frequency

(KHz)

VerticalFrequency

(Hz)

Dot Clock Frequency

(MHz)1 640 x 400 31.47 70.08 25.172 640 x 480 31.50 60.00 25.183 640 x 480 37.50 75.00 31.504 640 x 480 37.86 72.81 31.505 720 x 400 31.47 70.08 28.326 800 x 600 35.16 56.25 36.007 800 x 600 37.90 60.32 40.008 800 x 600 46.90 75.00 49.509 800 x 600 48.08 72.19 50.0010 832 x 624 49.00 75.00 57.2711 1024 x 768 48.40 60.00 65.0012 1024 x 768 56.50 70.00 75.0013 1024 x 768 60.00 75.00 78.7514 1152 x 864 63.86 70.02 94.5115 1152 x 864 67.52 75.02 108.0316 1280 x 720 45.00 60.00 74.2517 1280 x 960 60.02 60.02 108.0418 1280 x 1024 64.00 60.01 108.00

NO. ResolutionHorizontal Frequency

(KHz)

VerticalFrequency

(Hz)

Dot Clock Frequency

(MHz)1 480i 15.734 59.94 13.502 480p(720x480) 31.468 59.94 27.003 576p(720x576) 31.25 50.00 27.004 720p(1280x720) 37.50 50.00 74.255 720p(1280x720) 45.00 60.00 74.256 1080i(1920x1080) 33.75 60.00 74.25


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NUMBER 6 OF 9 PAGES

OF 10 PAGES


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NUMBER 7

user

文本框

- DVI could not support some PC Graphic cards.

Remote Control

1 Standby ( ): Press to turn on and off. 2 Mute ( ): Press to mute the sound. Press again to restore the sound. 3 0~9 Number Buttons: Press 0~9 to select a channel, and used to input the password; the channel changes after 2 seconds. 4 EPG: Press to display EPG mode. Press it again to exit EPG mode. 5 Input: Press to select the signal source, such as TV, AV, S-Video, Component 1, Component 2, VGA, DVI or DTV. 6 DTV: Press to choose DTV directly. 7 Dot: Press number buttons with it to select the channels directly in DTV. 8 VOL +/-: Press to adjust the volume. 9 CH +/- : Press to select the channel forward or backward. 10 MTS: Press repeatedly to cycle through the Multi-channel TV sound (MTS) options: Mono, Stereo and SAP (Second Audio Program). 11 ,,,, Enter: Press ,,, to move the on-screen cursor. To select an item, press Enter to confirm. And it can also press or to select channels, press or to adjust the volume. 12 Exit: Press this button to exit. 13 Menu: Press to enter into the on-screen setup menu, press again to exit. 14 V-Chip: Press to select the child protect mode. 15 CCD: Press to select the Closed Caption mode. 16 Freeze: Press to freeze the picture, press again to restore the picture. 17 Display: Press to display the channel information and it disappear after 3 seconds. 18 Favorite: Press repeatedly to cycle through the favorite channel list. 19 Add/Erase: Press to add or delete favorite or dislike channels. 20 S.Mode: Press repeatedly to cycle through the sound mode: Normal, News, Cinema, Flat and User. 21 PIC Size: Press repeatedly to cycle through the picture size that best corresponds your viewing requirements: Normal, Full, Wide1, Wide2, Wide3, 4:3, No Scale and Panoramic.

(Continued on next page)

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Note: Press CH +/- on the remote control can turn on TV set from standby mode.

Insertion of Batteries: - Turn the remote control upside down, press and slide off the battery cover. - Insert two 1.5V (AAA) batteries into the compartment, take care to observe the and markings indicated inside. - Replace the cover and slide in reverse until the lock snaps.

22 P.Mode: Press repeatedly to cycle through the picture mode: Normal, Vivid, Hi-Bright, User and Dark. 23 System: Press repeatedly to cycle through the system options: AUTO, and NTSC3.58. 24 Recall: Press to return to previous channel. 25 Sleep: Press repeatedly until it displays the time in minutes (5 Min, 10 Min, 15 Min, 30 Min, 60 Min, 90 Min, 120 Min and, OFF) that you want the TV to remain on before shutting off. To cancel sleep time, press SLEEP repeatedly until sleep OFF appears. 26 Red: Press this button to access the red item or page. 27 Blue: Press this button to access the blue item or page. 28 Green: Press this button to access the green item or page. 29 Yellow: Press this button to access the yellow item or page.

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PHYSICAL CHARACTERISTICS 14. Power Cord Length : 1.8m nominal Type : optional

15. Cabinet 15.1 Color : “Black” colour as defined by colour plaque reference number 15.2 Weight Net weight : 36.2 kg(with stand) /34.0kg(without stand) Gross weight : 41.0 kg 15.3 Dimensions(with stand) Width : 1040 mm Height : 690 mm Depth : 290 mm

Product Specification of PDP Module

Color Plasma Display Panel852 X 480 pixels

Address Driver

Scan

Driv

er

Com

mon

sust

ain

driv

er

Display data, Driver timing

MemoryController

DriverTimingController

InputInterfaceController Vcc(+5V)

Va(55V~65V)

Vs(180V~190V)

Control Signal (Serial Interface)

APL Data

LVDS Input

Applied Voltage level is specified at the time when Full-White pattern is displayed on the panel.

Block Diagram

74HC74(U12)

UPC3218AGC Amplifier

(U10)

X6965DSAW Filter

(U9)

MT5111DTV Front-end

(U11)

MT5351DTV Back-end

(U14)

TD1336Tuner(U8)

256Mb DDR(U15)

256Mb DDR(U18)

TS[0...7]

Coaxial

I2C

2nd_IF+ & 2nd_IF-Differential Data Stream

EEPROM24C16(U13)

I2C

32MbFlash(U17)

Video D

ata[0...23]Audio D

ata Con

trol

Sign

als

SPD

Connect withMT8205

Block Diagram

EEPOROM24C02(U14)

LP2996(U12)

IDTQ

S3V

H257

(U25)

IDTQ

S3

VH

257(U

16) YPbPr

BA

7612F(U

23)

EEPROM24C02(U19)

MT8205(U7)

CS4334(U22)

MT8776(U20)

DDR128Mb(U11)

Power Connector(Supplied by PDP)

EEPROM24C16(U2)

Flash16M-BIT(U9)

DDR128Mb(U10)

PDP Connector

SiI161B(SiI169)DVI Reciver

(U18)

YpbPr×2

DVI Video[0...23]

Vedio[0...23]

74LVC

244AU

30-U33

Audio

From M

T 5351

Control Signals

DVI Audio in

Din

Dou

t Bypa

ss O

ut

Audio L

& A

udio R

Audio B

ypassLV

DS

Dat

a

RG

B O

utpu

t

TV

PD

P C

ontro

l Sig

nals

VGA

I2C (MT8205 I2C) 3.3V

2.5V

1.25V

2.5V1.25V

5V

5V

5V

3.3V

1.8V

2.5V

3.3V

1.8V

2.5V

1.25

V

5V

3.3V

Data[0...31]Address[0...11]

I2C

MT8205 I2C

I2C

CVBS×2 (CVBS0 is from tuner.)

To PDP

To P

DP

MX232A(U1)

RS232Signals

TTL Signals(Used by MT8205)

VGAI2C

DVII2C

AVV_BYPASS

5V

5V

3.3V

UART0 (Communication with MT5351)

UART2 (MT5351 DownLoad)From

MT3551

YPbPr Audio in

AV Audio in

CD

4052(U

17)

AV1 Audio

AV2 Audio

S-Video

Block Diagram

Circuit Diagram

- Power supply board of PDP Module, DGP-420WXGA - Power supply board of PDP Module, USP490M-42LP - Main (Video) board - Audio/Tuner board - ATSC board - Keypad board - Remote control receiver board - External L/R Speakers board - Remote control board

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2004/07/28 FEP30JPPH967C6

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R11010KF

R1750

45.3KFR716

D208BYV26EGP

3.3KFR509

F101250VAC 8A

R148100KF

Q200KTA1281

R13610KF

18KFR615

R14410F

35V 47uFC120

R153100KF

R3065W6.8

C202 35V 47uF

35V 47uFC215

1uFC203

CN801

171825-7

1

2

3

4

5

6

7

R125

75KF

R406

1K

FC408 50V 0.1uF

SPW20N60C3*3Q102,Q103,Q109

R603

1W4R7

10KFR236

LL4148D204

C110470pF

PC

201

PC

-17K

1C

Q209SPW11N80C3

120KFR613

C222630V 0.1uF

C104630V 1uF

630V 0.047uFC206

R5191.5KF

Q206KTA1281

1W 47RR243

D102FEP30JP

R150100KF

C550~C55410V 2200uF*5

R526

2W 100KR620

IC400KIA7045AP

3

2

1 OUT

GN

DVCC

TNR10214D 621K

PC-17K1CPC202

R401 1KF

R21210KF

120KFR628

C2140.01uF

R1091W 4.7

PC100

R5132.7KF

IC200KA7552A

8

1

2

4

3

5

6

7

CS

RT

FB

GN

D

IS +

OUT

VC

C

CT

L103CH108200S

Q105KTA1281

250V 820uFC602

C2260.001uF

D1091N5236B

R2281W 4.7

Q203,204SPW11N80C3*2

1uFC216

R19856KF

PC-17K1CPC204

R600

1W4R7

R1462W 100

C5051KV 0.001uF

PC101

R5142KF

U101 UC3854N

1

2 345

6

7

8

9

10

11

1213 14 15

16

GN

D

PK

CAISMO

IA

VO

VR

RE

EN

VS

RS

SS

CT

VC

GT

R1426.8KF

C221630V 0.1uF

IC401HMS87C1304A

653 421 7 8 9 10 11 12131415161718192021222324

RD

0

VD

D

AN

6/R

A6

AN

6/R

A6

AN

5/R

A5

AN

4/R

A4

RD

1

AN

0/A

Vre

f/RB

0

BU

Z/R

B1

INT0

/RB

2

INT1

/RB

3

PW

M0/

CO

MP

0/R

B4

RD

2

RD

3

Xin

Xou

t

|RE

SE

T

Vss

RC

0

RC

1

RA

0/E

C0

RA

1/A

N1

RA

2/A

N2

RA

3/A

N3 C

411

50V0.01uF

Q300FQP17N40

STBY EE1927T100

D2121N5234B

C2010.01uF

18KFR710

R118180KF

FSF10A60D700

R135

10K

F

FSF10A60D601

Q104KTC3209

R418

1K

F

R1061W 4.7

L301

27uH

PC201

D202BYV26EGP

35V 47uFC123

11KFR711

50V 1

0uF

C115

CN013-176976-2

12

R111100F

130KFR607

18KFR719

R1035W 20

C700

1KV 100pF

R19556KF

45.3KFR715

R2304.7KF

T204,205VS EER4042

U1005M0280R-YDTU

12 3

4

GN

DD

RAI

N

VC

CFB

R3021.02KF

2W 240KR226

0.001uFC211

R190200KF

5KVR700

R140

7.5KF

R1414.7KF

R5105W 1K

SELCABLE

35V 470uFC128

470FR520

C40150V 0.1uF

R121160KF

R13133KF

Q207KRC103M

D107US1M

R422

10K

F

R1085W 15

R130240KF

Q201SPW11N80C3

1uFC530

56KFR525

C108680pF

33KFR702

1uFC209

PC205PC-17K1C

R152100KF

R51115KF

D206LL4148

C30450V 4.7uF

MULTI EER4042T207

0.01uFC219

BD101D25XB60

R119180KF

R611300KF

2.4KFR260

D301US1M

R1561KF

C5001KV0.001uF

50V 220uFC506

4.7KFR218

R2315W 0.05

R303

1KF

R12218KF

R421

10K

F

R2465W 0.2

R2232.2M

CN803

1-171825-2

1

2

3

4

5

6

7

8

9

10

11

12

C519

C213630V 0.01uF

R11610KF

R2251M

R1071W 4.7

LL4148D203

LL4148D209

C121

630V 0

.01uF

R151100KF

R503

1KF

R2321K

CN805

1-1123723-4

1

3

4

2

0.001uFC217

CN807

1-1123723-8

1

2

3

4

5

6

7

8

18KFR712

R129150KF PC-17K1C

PC102

R24510KF

R2532W 240K

D108

1N

5236B

1/4W 100RR220

IC500KA317

1 2

3

Adj Output

Inpu

t

R19256KF

R2092W 240K

VS_ON

+5V D

ET

9VSC

+12V D

ET

5VCTRL

60VA

RYC

ACD

5VSC

PFC +

RLY_ON

RLY O

N

SB5V

AC

D O

UT

VI

5VCTRL

190VS 5VCTRL

AC

DET

VI

60VA

9VSC

190VS

+5VSTB

Y

VS D

ET

24V/30V

+30V D

ET

+9V D

ET

VS O

N

RY O

N/O

FF

RYC

12VSC

VA

DET

VA VCC

PFC

ON

/O

FF

5VSC

5VD

PFC+

MU

LTI O

N/O

FF

60VA

PFC+

VA DET

5VD

OU

T

GND

MULTI VCC

PFC +

+12V /1.0A

GND

+9V DET

+12V DET

9VSC

PFC +

VA VCC

VS DET

190VS

190VS

GND

VA

,VS O

N/O

FF

PFC VCC

VA ON/OFF

60VA

GND

GN

D

GND

GN

D

방전

CTL

VA

AC-1

PFC+

PFC VCC

AC DET

PFC GND

+5VSTBY

PFC ON/OFF

방전 CTL

GND

VS

+5V DET

5VCTRL

+30V/1.0A (+24V/1.25A)

5VSC

GND

MULTI ON/OFF

+5VCTRL

+30V DET

DGP-420WXGA

carrie

Rectangle

carrie

Rectangle

user

附注

“user”设置的“Marked”

user

附注


USP490M-42LP

carrie

Rectangle

user

附注


A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

SCLSDA

TxD

INVERTER_PWR

8205UP3_1PWR_GND

+12V

SCLSDA

TUNER_12V

TUNER_12V

TXDRXD

R xD

RSRXD

PCRXD

PCTXD

SYS_PWR

8205UP3_1

PCRXDPCTXD

RSRXDRSTXD

RSTXD

INVERTER_PWR

PWR_GND

PWR_GND

GPIO_DVD1

GPIO_DVD1

DV33A URST#

URST#

DV18A

5VSB5VSB

INVERTER_PWR

VCC

DV33A

+12V

+12V

5VSB

5VSB

5VSB

5VSBDV33A

5VSB

VCC

+12V

DV18A

SDA 7,10SCL 7,10

INVERTER_PWR 11

8205UP3_1 3

+12V 7,10,13,14TUNER_12V 7

TXD 3,13RXD 3,13

PWR_GND 11

PCTXD 13

RSTXD 6RSRXD 6

GPIO_DVD1 3

URST# 3

DV18A 2,3

PCRXD 13

Title

Size Doc Number R ev

Date: Sheet o f

INDEX V1.2

C

1 15Wednesday, October 12, 2005

12.WM8776 & A/V BYPASS

2. LDO

14.PDP INTERFACE

For Tuner

5. DDR MEMORY & FLASH6. VGA IN & PC AUDIO IN

RS-232

7. VIDEO IN & TUNER IO

3. MT8205E PBGA388

1. INDEX

4. MT8205 ANALOG DECOUPLING

DIGITAL GND

8. AUDIO/VIDEO IN CIRCUIT9. DVI INPUT

10.LVDS/CRT/TTL OUT11.BACK LIGHT / KEYPAD

SYSTEM EEPROM

AUIO IN/OUT GND

MT8205E (PBGA388) LCDTV BOARD 4 LAYERS

13.ATSC INTERFACE

From Power board.

8205UP3_1 HIGH :POWER OFF8205UP3_1 LOW :POWER ON

ANALOG INPUT GND

ADD BY MTK

Add by MTK

Add by MTK

Power down Reset circuit

ADD BY MTK

Q14

2N3904

1

3 2

R33710k R6

10kU2

EEPROM 24C16SOP8/SMD

NC1NC2NC3GND4 SDA 5SCL 6WP 7VCC 8

R110k

R3420

+ CE347uF/16v

C40.1uF

C13320pF

M21

R3350/NC

R310K

R2

4.7k

R341 10

R73 10/NC

C3 0.1uF

C13220pF

M31

H4HOLE/GND

2 23 34 45 5

99887766

11

J1

5x1 W/HOUSINGPH5/2.0

12345

J21

CON10

123456789

10

J2

DIP11/P2.54

1234567891011

C5 0.1uF

J3

8x1 W/HOUSINGDIP8/W/H/P2.54

12345678

C1 0.1uF

+

CE88

47uF/16v

R410K

H1HOLE/GND

2 23 34 45 5

99887766

11

V11

L50

FBBEAD/SMD/1206

L1

FBBEAD/SMD/0805

D281N4148

H3HOLE/GND

2 23 34 45 5

99887766

11

H2HOLE/GND

2 23 34 45 5

99887766

11

V21

CB1

0.1uF

CB1360.1uF

C2 0.1uF

V31

R112RR0603/SMD R5

10k

+ CE2220uF/16vC220UF16V/D6H11

M11

L44

FBBEAD/SMD/1206

Q1

2N3904SOT23/SMD

1

32

V41

U1

MAX232A

R1IN13R2IN8T1IN11T2IN10

C+1C1-3C2+4C2-5V+2V-6

R1OUT 12R2OUT 9T1OUT 14T2OUT 7

VCC 16

GND 15

R3360

J4


1234

+ CE1220uF/16vC220UF16V/D6H11

CB20.1uF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

AV33

DV33

DV33A

DV18A

DV18A

AV33

DV33VCC 5VSB

DV33A

DV18A

DV18A 1,3

Title


Date: Sheet o f

LDO V1.2

C


Vout

Power ON alive source

CB50.1uF

+ CE8220uF/16v

U3 CM1117-3.3V

SOT223/SMD

AD

J/G

ND

1

OUT 2IN3

U5 CM1117-3.3V

SOT223/SMD

AD

J/G

ND

1

OUT 2IN3

+ CE10220uF/16v

CB70.1uF

CB90.1uF

+CE4

220uF/16vCB30.1uF

TP2

R96 0/NC

R0805/SMD

C610uF/10v L5

FBBEAD/SMD/0805

+ CE6220uF/16v

+ CE7220uF/16v

L4

FBBEAD/SMD/0805

R99 0/NC

R0805/SMD

+ CE5220uF/16v

U6 CM1117-1.8V

SOT223/SMD

AD

J/G

ND

1

OUT 2IN3

CB80.1uF

TP1TEST POINT DIP1.0

CB40.1uF

+ CE9100uF/16v

L2

FBBEAD/SMD/0805

L3

FBBEAD/SMD/0805

CB60.1uF

U4 CM1117-3.3V

SOT223/SMD

AD

J/G

ND

1

OUT 2IN3

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

A_CLK

A_DQM[0..1]A_BA[0..1]

A_WE#

A_CKEA_CLK#

A_DQ[0..31]

A_RA[0..11]

A_CAS#

A_DQS[0..3]

SDV25

A_CS#A_RAS#

F_A[0..20]

F_OE#F_D[0..7]

8205UP3_0

VS YNCH SYNC

GREEN-BLUE+BLUE-

RED+

VGASOG

RED-

VGAVSYNC#

Y -

SY+

CB-

SC-

CVBS0-

Y+

CB+

SC+

C R-

S Y-

CR+

CVBS0+

AP[0..7]AN[0..6]

CLK1-CLK1+

SCL_8205SDA_8205

CVBS1-CVBS1+

MPX1MPX2

PWM0

DACVREFDACFS

LVDDADACVDD

VREFN4VREFP4

AVCMVOCMVICM

ADCVDD0

REXTAAPLL_CAP

XTALIXTALO

ADCPLLVDD1ADCPLLVDD

VPLLVDDAPLLVDD

PWM2VREF

AUXTOPAUXBOTTOM

ADCVDD

GND

OBO7

GND

OB

O4

OBO5OBO6

MPX2

ADCVDD4MPX1

DACVREF

VREFN4

GNDVREFP4

GND

AUXTOP

GND

PWM2VREFADCVDD

VPLLVDD

AUXBOTTOM

VPLLVDDGND

REXTA

LVDDAVPLLVDD

GND

AP7

AP6GND

AN6AP5

AP4AN4

AN5LVDDA

AP2

GNDCLK1+

AN3AP3

CLK1-

H SYNC

LVDDAAN2

DACVDD

AP0

R

AN0

DV33A

AP1

VS YNC

DACVDDGND

G

BGND

GND

DACVDD

AN1

GND

DACFS

DV

33A

F_A

16

F_A

17

F_A

6

GN

DF_A

19F_

A20

F_A

18

GN

DOR

O6

F_A

15

F_A

14

OG

O1

GN

DOB

O2

OG

O2

F_D

5

OB

O0

F_A

8

OG

O6

OG

O5

OR

O7

DV

18A

F_A

10

F_D

3

OB

O3

OB

O1

F_D

1

F_A

12

F_D

6

F_A

13

GN

DF_A

9

OG

O0

F_D

7

F_D

4

F_A

3

F_A

5

F_D

0

F_D

2

DV

33A

OG

O3

F_A

4

F_A

1F_

A2

F_A

0

F_A

11

8205

UP

1_3

8205

UP

1_2

PC

E#

F_O

E#

WE

#

F_A

21

RxD

IRPW

M0

GN

D HW

SC

L

TxD

HW

SD

A

GP

IO

A_DQ0

8205

UP

3_0

UR

ST#

GN

D8205

UP

3_1

UP

3_4

UP

3_5

DV

33A

A_CS#

A_DQ8

A_RA0

A_CKE

A_BA0

A_DQ11

DV18A

SDV25

GND

GND

A_DQ10

GND

A_RA10

A_RA3

A_DQ17

A_RA5

A_DQM1

SDV25

A_DQ13

A_DQ25

A_DQ5

GND

A_RA6

SDV25

GND

A_DQ29

SDV25

A_DQ12

A_RA2

A_DQ15

A_DQ9

GND

DV18A

A_RA1

GND

A_DQ18

A_DQS3

A_DQ7

A_RAS#

A_RA7

A_DQS1

GND

A_DQ19

GND

A_DQ1

SDV25

A_DQ28

A_DQ22

GNDA_DQ24

A_CLK

GND

A_DQ3

A_DQ2

SDV25

A_RA8

A_DQM0

A_DQ21

A_DQ6

GND

A_DQ20

A_WE#

A_BA1

A_DQ23

A_DQ27

VREF

A_DQ30

A_DQ4

A_DQ14

A_RA11

A_DQ26

A_CLK#

SDV25

A_DQ31

A_DQS2

DV18A

A_RA9

SDV25

GND

A_CAS#

A_DQ16A_RA4

DACMCLKDACLRCDACBCLKDOUT

DV18A

DV33A

DV

IOD

CK

GN

D

GN

D

HS

YN

C_V

GA

BLU

E+

GN

DBLU

E-

DV

18A

AD

CP

LLV

DD

GN

D

VG

AV

SY

NC

#

VI1

3V

I12

VI2

3

VI1

4V

I15DV

18A

VI1

VI8

GN

D

VI6

VI4

VI1

1

VI5

VI3

VI7

VI0

VI9

VI2

VI1

0

VG

AS

OG

AD

CV

DD

0

GR

EE

N-

RE

D+

GR

EE

N+

RE

D-

XTAL

I

AP

LL_C

AP

GN

DXTAL

O

AN

ALO

GV

DD

AP

LLV

DD

AN

ALO

GV

DD

AN

ALO

GV

DD

GN

D

VI1

7

VI2

0

VI2

2

VI1

8V

I19

VI1

6

VI2

1

GN

D

AD

CP

LLV

DD

1G

ND

ADCVDD4

GN

D

GN

D

AD

CV

DD

0A

VC

M

CV

BS

2+

CV

BS

1+C

VB

S1-

CV

BS

2-

CV

BS

0+G

ND

CV

BS

0-

AD

CV

DD

0S

C-

SC

+S

Y-

GN

DS

Y+

VO

CM

CB

+

GN

D

CB

-

Y+

VIC

M

Y-

AD

CV

DD

0

SO

Y

CR

-C

R+

ANALOGVDD

GN

D

DACBCLK

AD

CV

DD

0

DV18A

DV18A

OBO[0..7]

GREEN+

HSYNC_VGA

DV IHSYNCDVIVSYNC

DVIDEDVIODCK

DVIDEDVIVSYNCDV IHSYNC

OG

O7

F_A

7

A_DQS0

VREF

8205

UP

1_4

PW

M1

CVBS2-CVBS2+

VI[0..23]

SOY

MUTE

MU

TE

OR

O5

OR

O4

OR

O2

ORO2ORO4

OGO[0..6]

ADCVDD4

ORO7

DV

18A

OR

O3

AOSDATA3

SW

OR

O1

WE#PCE#

TXDRXD

DOUT

DACMCLKDACLRC

DACBCLK

READY#REQUEST#

SCL_8205

UP3_5

SDA_8205HWSCL

UP3_4

HWSDA

AOSDATA1

AOSDATA1AOSDATA3

ORO1ORO3ORO58205UP1_4

SW

8205UP1_3

I R

8205UP3_1

GPIOORO6

GP

IO_D

VD

0

GPIO_DVD1

OG

O4

ICE

DV

ISC

LD

VIS

DA

RE

QU

ES

T#R

EA

DY

#

DV33A

DV33A

RGB

8205UP1_2

OGO7PWM1OGO4

DVISDADVISCL

GP

IO_D

VD

1D

V18

A

GP

IO_D

VD

2

GPIO_DVD0

GPIO_DVD2

F_A21

ADIN4

ADIN4URST#

ADIN3

ADIN0

ADIN3ADIN2ADIN1ADIN0

ADIN2ADIN1

DV18A

URST#

GND

RSTVCC URST#

DV33A DV18A

DV33A

DV33A

DV33A

5VSB

A_CKE 5

A_CAS# 5

A_DQS[0..3] 5

A_CLK 5

A_WE# 5

A_BA[0..1] 5A_RA[0..11] 5

A_CS# 5

A_DQ[0..31] 5

SDV25 5

A_RAS# 5

A_DQM[0..1] 5

A_CLK# 5

F_D[0..7] 5F_OE# 5

F_A[0..20] 5

OBO[0..7] 11

VSYNC 10HSYNC 10

RED- 8

BLUE+ 8BLUE- 8

RED+ 8

VGASOG 8

GREEN- 8

VGAVSYNC# 6

SC+ 8

CR+ 8

SC- 8

SY+ 8

CR- 8

Y- 8

SY- 8

CVBS0+ 8

CB+ 8

CVBS0- 8

CB- 8

Y+ 8

AP[0..7] 10AN[0..6] 10

CLK1+ 10CLK1- 10

SDA_8205 10SCL_8205 10

CVBS1+ 8CVBS1- 8

PWM0 11

DACVREF 4DACFS 4

LVDDA 4DACVDD 4

VREFP4 4VREFN4 4

VOCM 4AVCM 4

VICM 4

ADCVDD0 4

REXTA 4APLL_CAP 4

XTALO 4XTALI 4

ADCPLLVDD 4ADCPLLVDD1 4

APLLVDD 4VPLLVDD 4

PWM2VREF 4

AUXTOP 4AUXBOTTOM 4

ADCVDD 4

MPX2 8MPX1 8

ANALOGVDD 4

GREEN+ 8

HSYNC_VGA 6

DVIHSYNC 9,13DVIVSYNC 9,13

DVIODCK 9,13DVIDE 9,13

VREF 5

VI[0..23] 9,13

SOY 7

MUTE 12

ORO2 7ORO4 12

OGO[0..6] 7,9,13

ADCVDD4 4

ORO7 12

SW 13

WE# 13PCE# 5

RXD 1,13TXD 1,13

DOUT 12

DACMCLK 12

AOSDATA3 12

DACBCLK 12

DACLRC 12

AOSDATA1 12

READY# 13REQUEST# 13

ORO1 10,14ORO3 10,14ORO5 108205UP1_4 10

8205UP1_3 13

IR 7,11

CVBS2- 8CVBS2+ 8

8205UP3_1 1

GPIO 7,10ORO6 10

GPIO_DVD1 1

8205UP3_0 11

R 10G 10B 10

8205UP1_2 9,11

OGO4 9,13PWM1 12

DVISDA 9DVISCL 9

OGO7 12

GPIO_DVD2 7

GPIO_DVD0 7

F_A21 9ADIN4 14URST# 1DV18A 1,2

Title


Date: Sheet o f

MT5205BGA388 V1.2

C


UP3_5 FOR S/W SDAUP3_4 FOR S/W SCL

PDP power cotrol GPIO.

PDP signal cotrol GPIO.

DVD GPIO PORTS

Internal Reset Circuit

External Reset Circuit

Change by MTKR91k

CB135

0.1uF

R368 10K

R16 R/NC

R270100K

R1040

R17 0

R710K/NC

R106 0

R367 10K

+ CE81

22uF/25v

R18 0

+ CE11

10uF/25v/NC

R366 10K

U27LM809

SOT23/SMD

GN

D1

OUT 2IN3

R365 10K

R847k

MT8205

U7

MT8205BGA388/SOCKET

A2PP2

DVSS3R11ERO1AD1

HIG

HA

6A

E9

HIG

HA

5A

F9H

IGH

A4

AE

10H

IGH

A3

AF1

0

SC

L0A

F26

DV

DD

18A

D18

EBO7V2EBO6V3EBO5W1EBO4W2DVDD3IAC9EBO3W3EBO2W4

CLK1PN2

A4NL1

CLK2PH2

VREFM4

LVDDCM3

RV4

HSYNCOU2

GU4

RWE# U24

DQ10 V26DQ9 V25DQ8 W26

RAS# T24

CAS# T23DVSS2 R15

DVDD2I U23

DQ11 U25

DQ13 T25

OR

O3

AE

7

SD

A0

AE

26

OR

O6

AF6

OR

O2

AF7

OR

O1

AC

8O

RO

0A

D8

HIG

HA

7A

F8

HIG

HA

1A

D11

HIG

HA

0A

F12

AD

0A

E15

AD

1A

D15

DV

DD

18A

C19

AD

2A

C15

AD

3A

F16

AD

4A

E16

DV

SS

3R

12

AD

7A

F17

AD

5A

D16

IOA

0A

D17

IOA

3A

F14

IOA

4A

F13

IOA

5A

E13

IOA

6A

D13

IOA

7A

C13

DV

DD

3IA

C10

A16

AE

8

A17

AC

17

IOA

20A

E11

DV

SS

18T1

2IO

A21

AF1

1IO

ALE

AE

17

EBO1Y1

OB

O1

AE

3

DV

SS

18T1

1

OB

O0

AF3

ERO5AC1

OG

O1

AC

6D

VD

D3

AD

9

OR

O7

AE

6O

GO

0A

D6

OBO6AD4

ERO6AB4

OBO5AE1

OG

O4

AD

5

ERO7AB3

EGO1AB1

EGO5AA1

ERO4AC2

OB

O4

AE

2

OG

O3

AE

5O

GO

2A

F5

EGO0AB2

EGO2AA4

DVDD18AC18

EGO4AA2

DVSS18P11 EGO7Y3

VCLKV1

OG

O5

AC

5

EGO3AA3

IOC

S#

AC

14

AUXVTOPF3

VPLLVDDG4

ADIN2E2

ADCVSSF2

RA2 N23

AUXVBOTTOMG3

TES

TPB

14

ADIN1E3ADIN0E4

AFC2

A3PM2

DVSS2 R16RA5 J24RA6 K23

DVDD18 AA23

DVDD2 H23

DVSS18 R14RA8 L23

RA9 L24RA11 M23

RCLK P26

OR

O4

AD

7

DACVSSBR3

SVMT4 DACVSSCN11

BGVDDH4

BGVSSK4 DLLVSSK3

REXTAJ4

A4PL2

A5NK1

LVSSAM12

A2NP1

DACVDDBP3

LVDDBL4

REFP4D1REFN4D2

ADCVDDF1

DLLVDDH3

RCLKB P25DVSS2 P15

RA3 M24

RA0 R26RA1 N24

BU3 DACVSSAR4

DACVDDAP4

ADCVDD4D3

DQ18 M25DQ17 M26

RA4 J23

RA10 P24

DQ16 N25

BA0 R24

DV

DD

18A

D19

UP

30A

E21

PR

ST#

AC

21U

P34

AD

22U

P35

AC

22

WR

#A

F18

DQ3 AC26DVDD2 W24

DQ2 AC25

RX

DA

E24

IRA

F24

PW

M1

AC

23P

WM

0A

D23

TES

TNA

14

FCIC

MD

AE

22FC

ICLK

AF2

2

DQ7 AA26

DVSS18 T16

DQ6 AA25

DVSS2 T14DQ4 AB25

SD

A1

AB

24S

CL1

AB

23

SC

LA

F25

UP

12A

E19

INT0

#A

F19

DV

DD

3A

D10

AVDD18 Y23RVREF G23

RD

#A

E18

DQ14 T26

AVSS18 W23DQS1 W25DQ15 R25

UP

17A

F21

DVDD2 V24

DVDD2 H24

SIFC1

ADCVSS4L11

ADIN4D4ADIN3E1

PWM2VREFF4

VPLLVSSJ3

A0NT1 A0PT2

LVDDAL3

A1NR1

CLK1NN1

A3NM1

A1PR2

A5PK2 A6NJ1 A6PJ2

UP

15A

D20

OG

O7

AE

4

EGO6Y4

LVSSBM11

FSN4

DACVDDCN3

A7PG2

CLK2NH1

ERO0AD2

OB

O2

AF2

EBO0Y2

OG

O6

AF4

RCS# R23

BA1 P23

RA7 K24

CKE N26

DVSS18 T13

DVSS2 T15

DQ12 U26

SD

AA

E25

FCID

AT

AF2

3

UP

31A

D21

UP

13A

F20

IOA

18A

E12

IOO

E#

AF1

5

AD

6A

C16

IOA

1A

D14

OR

O5

AC

7

DET3

ERO3AC3

DVDD2 V23

UP

14A

E20

A7NG1

LVSSCN12

TXD

AD

24

ICE

AC

24

DQ0 AD25

DQS0 Y25

DQ5 AB26

DV

SS

18P

12

VSYNCOU1

ERO2AC4

OBO7AD3

OB

O3

AF1

HIG

HA

2A

C11

DV

SS

18P

13

UP

16A

C20

GP

IO0

AE

23

IOW

R#

AC

12

IOA

2A

E14

DV

SS

3R

13

DQM0 Y26

IOA

19A

D12

DQ1 AD26

DQ19 L26DVDD18 AA24DQ20 L25DQ21 K26DVSS2 P16DQ22 K25DQ23 J26DQS2 J25

DQM1 H26

DVDD2 G24

DQS3 H25DQ31 D25DQ30 D26

DVSS2 N16DQ29 E25

DVSS18 P14

DQ28 E26DQ27 F25DVDD2 F24DQ26 F26DQ25 G25DQ24 G26DVSS3 N15AOMCLK E24AOLRCK C25AOBCK C26LIN B24AOSDATA3 B25DVDD3I F23AOSDATA2 B26AOSDATA1 A26AOSDATA0 A25DVDD18 Y24HSYNC_DVI A24VSYNC_DVI D24DE_DVI C24VC

LK_D

VI

B23

VI2

3A

23V

I22

D23

VI2

1C

23V

I20

B22

VI1

9A

22V

I18

D22

VI1

7C

22V

I16

B21

DV

SS

18M

16V

I15

A21

VI1

4D

21V

I13

C21

VI1

2B

20D

VS

S3

L16

VI1

1A

20V

I10

D20

VI9

C20

VI8

B19

VI7

A19

DV

DD

18E

23V

I6D

19V

I5C

19V

I4B

18V

I3A

18V

I2B

17V

I1A

17V

I0B

16D

MP

LLV

SS

C18

DM

PLL

VD

DC

17A

PLL

VD

DD

17A

PLL

VS

SD

18A

PLL

_CA

PA

16X

TALV

SS

M15

XTA

LIA

15X

TALO

B15

XTA

LVD

DC

16

SY

SP

LLV

DD

D16

SY

SP

LLV

SS

L15

AD

CP

LLV

SS

M14

AD

CP

LLV

DD

C15

AD

CP

LLV

DD

1D

15A

DC

PLL

VS

S1

L14

DV

DD

D14

DV

SS

N14

HS

YN

CC

14V

SY

NC

C13

RE

FN3

C12

RE

FP3

D12

AD

CV

SS

3C

10B

PA

13B

NB

13S

OG

D13

GP

A12

GN

B12

RP

A11

RN

B11

AD

CV

DD

3D

8M

ON

1C

11M

ON

0D

11R

EFN

2C

9R

EFP

2D

9A

DC

VS

S2

D10

CR

PA

8C

RN

B8

CB

PA

9C

BN

B9

SO

YC

8Y

PA

10Y

NB

10

AD

CV

DD

2C

7V

ICM

A7

VFE

VS

S0

N13

VO

CM

B7

VFE

VD

D0

D7

RE

FN1

C6

RE

FP1

D6

AD

CV

SS

1M

13S

YP

A6

SY

NB

6S

CP

A5

SC

NB

5A

DC

VD

D1

C5

RE

FN0

A4

RE

FP0

B4

AD

CV

SS

0L1

3C

VB

S0P

A3

CV

BS

0NB

3C

VB

S1P

A2

CV

BS

1NB

2C

VB

S2P

A1

CV

BS

2NB

1A

DC

VD

D0

C4

AV

CM

D5

VFE

VS

S1

L12

VFEVDD1C3

D1

1N4148/SMD

R15 R/NC

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

ADC_VDD

DACVDD

DACVDD

DACVDD

GND

VICM

VOCM

ADCVDD

DACVREF

VPLLVDD

VPLLVDD

AUXTOP

AUXBOTTOM

ANALOGVDD

ADCPLLVDD

ANALOGVDD

XTALO

ADCPLLVDD1DV18A

ADCPLLVDD1ADCPLLVDDAPLLVDD

APLL_CAPXTALIXTALO

APLLVDD

VPLLVDD

REXTA

AUXTOPAUXBOTTOM

LVDDA

PWM2VREF

ADCVDD

ADCVDD0

DACVDDAVCMVOCMVICM

VREFN4VREFP4

DACVREFDACFS

VPLLVDD

ANALOGVDD

AVCM

GND

GND

VREFN4

GND

VREFP4

LVDDA

APLL_CAP

ANALOGVDD

GND

ADCVDD4

ADCVDD0

ADCVDD0

ADCVDD0

GND

GND

ADCVDD4

XTALI

ADCVDD0

PWM2VREF

GND

GND

GND

AV33

GND

LVDDA

GND

LVDDA

GND

GND

LVDDA

GND

GND

GND

GNDGND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GND

GNDREXTA

DACFS GND

DV18AAV33

VCC

ADC_VDD

DV33A

DV18A

AV33

DV33A

DV18A

ADC_VDD

AV33

ADCPLLVDD1 3ADCPLLVDD 3APLLVDD 3

APLL_CAP 3XTALI 3XTALO 3

VPLLVDD 3

REXTA 3

AUXTOP 3AUXBOTTOM 3

LVDDA 3

PWM2VREF 3

ADCVDD 3

ADCVDD0 3

DACVDD 3AVCM 3VOCM 3VICM 3

VREFN4 3VREFP4 3

DACVREF 3DACFS 3

ANALOGVDD 3

ADCVDD4 3

DV18A 1,2,3

Title


Date: Sheet o f

MT8205 DECOUPOMG--ANALOG V1.2

C


FOR DACVDD

Vout

FOR ADCVDD

MT8205 ANALOG DECOUPLING&DIGITAL DECOUPLING

0603 PUT ON NEARLY BGA

0603 PUT ON NEARLY BGA

DIGITAL DECOUPLING

C264.7uFC0603/SMD

C233300pF

L15 FB

CB21 0.1uFC0603/SMD

CB400.1uFC0603/SMD

L14

FB

R26 50/47R

L8

FBBEAD/SMD/0805

R101 0/NC

R0805/SMD

L12

FBBEAD/SMD/0603

CB330.1uF

+ CE2147uF/16v

CB290.1uFC0603/SMD

R19

100k

C32 1500pF

L7

FBBEAD/SMD/0603

CB310.1uF

C184.7uF

C0603/SMD

C283300pFC0603/SMD

L9

FBBEAD/SMD/0603

C254.7uF

C0603/SMD

R230

C1233pF

+ CE1547uF/16v

C33 0.1uF/NC

Y1 27MHz

CB410.1uF

C100.1uF

CB23 0.1uFC0603/SMD

U8 CM1117-3.3V

SOT223/SMDA

DJ/

GN

D1

OUT 2IN3

C220.01uF

CB16

0.1uF

+ CE1810uF/25vCB46

0.1uF

TP6

C293300pFC0603/SMD

CB200.1uFC0603/SMD

+ CE1422uF/25v

CB454.7uF

C174.7uF

C0603/SMD

+CE19

47uF/16v

CB470.1uF

L11

FBBEAD/SMD/0603

CB270.1uFC0603/SMD

CB484.7uFC0603/SMD

CB17

0.1uF+ CE22

47uF/16v

CB120.1uFC0603/SMD

CB140.1uFC0603/SMD

CB100.1uFC0603/SMD

+

CE16100uF/16v

C303300pFC0603/SMD

+CE12

10uF/25v

C160.1uF

CB150.1uFC0603/SMD

C274.7uF

C0603/SMD

CB130.1uFC0603/SMD

CB360.1uFC0603/SMD

C154.7uF

C0603/SMD

L10

FBBEAD/SMD/0805

C134.7uF

C0603/SMD

CB320.1uFC0603/SMD

TP5

C84.7uF

C0603/SMDC74.7uF

C0603/SMD C244.7uF

C0603/SMD

C94.7uF

C0603/SMD

CB44 4.7uFC0603/SMD

C214.7uF

C0603/SMD

C144.7uF

C0603/SMD

CB370.1uFC0603/SMD

CB420.1uFC0603/SMD

CB220.1uFC0603/SMD

CB250.1uF

C313300pFC0603/SMD

CB11

0.1uF

R24 3.3kC1133pF

R210

R25 50/47R

CB340.1uFC0603/SMD

CB49 4.7uFC0603/SMD

L6

FBBEAD/SMD/0603

CB380.1uFC0603/SMD

CB19 0.1uFC0603/SMD

CB260.1uF

CB240.1uFC0603/SMD

CB280.1uF

+ CE17220uF/16v

+ CE2022uF/25v

L13

FBBEAD/SMD/0603

R20

0

R22

0

CB350.1uF

C200.1uF

CB430.1uF

CB390.1uFC0603/SMD

CB180.1uF

C194.7uF

C0603/SMD

R27 560

CB300.1uF

+CE13

10uF/25v

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

A_RA[0..11]A_BA[0..1]

A_CLK

A_CKE

A_RAS#A_CS#

A_WE#A_CAS#

A_DQM[0..1]A_DQ[0..31]

F_D[0..7]F_OE#

A_DQS[0..3]

A_CLK#

SDV25VREF

F_D3

F_A14

F_A20

F_A17

F_A2F_A3

F_A9

F_A11

F_A7

F_A12

PWR#

F_D4

F_A8

F_A0

F_A5

F_D6

F_D1

F_A13

F_A4

F_A10

F_A18

F_A1

F_D2

F_D5

F_A16F_A15

F_A19

PCE#F_OE#

F_D0

F_D7

F_A[0..20] FLASHVCC

SDV25

D1V25

D1V25

D1V25

D1V25

SDV25

SDV25

SDV25

SDV25

VREF

A_DQ19

A_CLK

A_DQ17

D_CLK

D_DQ14

D_CAS#

D_RA6

D_DQ23

A_DQ8

D_DQ20

D_RA4

D_DQS1

D_DQM1

A_DQ25

A_RA5

D_DQ17

A_DQ1

D_RA8

D_DQ29

D_DQ24

D_DQS2

D_RA3

D_DQ3

D_DQM1

D_DQ8

D_RA7

D_CKE

D_DQ13

D_DQ1

A_RA2

D_RA9

A_DQM0

A_DQ4

D_DQ8

A_DQ16

D_DQ6

D_RA5

A_DQ14

D_WE#

A_DQS1

D_DQ15

A_DQ26

A_RA4

D_CKE

D_CLK

A_DQS2

D_DQS3

D_DQ30

D_BA1

A_DQ13

A_CKE

D_RA6

A_DQ3

D_DQ6

A_RA3

D_RA2

D_RA3

D_DQS1

D_DQ15

D_DQ4

D_RA7

A_BA1

D_DQ5

A_DQ21

D_CLK#

D_CS#

D_DQ14

D_DQM1

D_DQ0

D_BA0

D_DQ22

A_DQS0

A_RA8

D_DQ22

A_DQ24

A_RA6

D_RA5

A_DQ0

D_DQ5

A_DQ29

A_DQ15

A_RAS#

D_DQ11A_DQ10

D_CS#

D_CLK#

D_DQS2

D_DQ24

D_DQ7

D_DQ13

D_RA1

D_DQ20

A_RA0

A_WE#

D_BA1

D_DQ23

A_RA9

A_BA0

A_DQ22

D_RA4

D_CAS#

A_DQM1

D_RA3

D_DQ4

A_CLK#

A_DQ27

D_CAS#

D_DQ19

D_DQS3

D_RAS#

A_DQ6

D_RA11

D_DQ25

VREFD_DQ28

D_RA2

D_RA8

A_DQ12

D_BA0

D_DQ25

D_CS#

A_DQ9

D_DQ18

D_DQ12

D_DQ26

D_RA0

A_CAS#

D_DQ26

VREF

A_RA11

D_RA4

D_WE#

D_DQ17

D_DQ12

D_RA11D_RA9

A_DQ20

D_RA2

D_WE#

D_CLK

D_DQ31

D_DQ18

D_DQ11

A_RA1

D_RA10

A_DQ30

D_DQ2

D_DQ31

A_RA10

D_DQ16

D_RA10

D_DQ27

A_DQ5

D_RA1

D_BA0

D_DQ28

D_DQ27

A_DQ18

D_CKE

D_RAS#

D_RA7

D_BA1

D_DQ2

A_DQ11

D_RA10

D_DQ10

D_DQM0

D_DQ29

D_DQ19

D_RAS#

D_RA6A_RA7

A_CS#

D_RA9

A_DQ31

A_DQ2

D_DQ21

A_DQS3

D_RA8

D_DQ16

D_RA1

D_CLK#

D_DQ10

D1V25

A_DQ23

D_DQM0

D_DQS0

D_RA0

D_DQ1

D_DQ9

D_RA5

D_DQS0

D_DQ30

D_DQ21

A_DQ28

A_DQ7

D_DQ9

D_DQ3

D_RA11

D_RA0

D_DQ7

VREF

D_RA2

D_DQ6

D_DQ12

D_DQS3

D_DQM1

D_DQ11

D_BA1

D_DQS1

D_CAS#

D_RA1

D_DQ3

D_DQ24

D_DQ23

D_DQ28

D_DQS2

D_DQM0

D_DQ20

D_RA7

D_DQ30

D_DQ5

D_DQ16

D_RA0

D_RA5D_RA4

D_WE#

D_RAS#

D_RA6

D_DQ19

D_DQ22

D_RA11

D_DQ1

D_DQ13

D_DQS0

D_DQ18

D_DQ26

D_DQ14

D_DQ21

D_RA8

D_DQ15

D_DQ17

D_DQ31

D_RA3

D_CS#

D_DQ7

D_DQ4

D_RA10

D_DQ2

D_DQ8

D_DQ27

D_DQ29

D_DQ25

D_DQ10

D_BA0

D_DQ9

D_DQ0

D_RA9

PCE#RWR#

F_A6

D_DQ0

D_DQM0

VREF

DV33A

DV33A

DV33A

SDV25

DV33A

D1V25

VCCSDV25

VREF

SDV25

VREF

SDV25

SDV25 SDV25

D1V25

SDV25 SDV25

D1V25

A_RA[0..11] 3A_BA[0..1] 3

A_CLK 3

A_CKE 3

A_RAS# 3A_CS# 3

A_WE# 3A_CAS# 3

A_DQM[0..1] 3A_DQ[0..31] 3

F_D[0..7] 3F_OE# 3

A_DQS[0..3] 3

A_CLK# 3

SDV25 3VREF 3

F_A[0..20] 3

PCE# 3PWR# 13

Title


Date: Sheet o f

DDR MEMORY&FLASH V1.2

C


TSOP 48 pin

VREF DECOUPLING

Del By Ada

R32 75

CB560.1uF

CB680.1uF

C453300pF

CB650.1uF

RN20

47x4

1 23 45 67 8

RN9

47x4

1 23 45 67 8

CB114

0.1uF

R46 75

C403300pF

CB850.1uF

CB740.1uF

RN24

22x4

1 23 45 67 8

CB760.1uF

R48 75

R51 22

R290

CB630.1uF

CB580.1uF

RN18

47x4

1 23 45 67 8

C383300pF

R52 75

CB840.1uF

R41 4.7k

+ CE28

220uF/16v

CB970.1uF

R31 22CB50

0.1uF

CB1010.1uF

CB640.1uF

U9

MX29LV160BT

A025A124A223A322A421A520A619A718A88

A199

OE28

BYTE 47

A18 16

D0 29D1 31D2 33D3 35

A97

CE26

D4 38D5 40D6 42D7 44D8 30D9 32

A2010

D11 36D12 39D13 41D14 43D15 45

VCC 37

GND1 27WE11

RY/BY15

D10 34

GND2 46

A106

A124 A115

A133A142A151A1648A1717 NC 13

RESET12

WP/ACC 14

+ CE24

220uF/16v

CB111

0.1uF

RN7

47x4

1 23 45 67 8

CB770.1uF

R40 22

C433300pF

R45 22

C353300pF

CB530.1uF

CB94

0.1uF

CB110

0.1uF

RN12

47x4

1 23 45 67 8

C393300pF

CB600.1uF

CB710.1uF

R34 47

CB520.1uF

RN14

75x4

1 23 45 67 8

TP7

8M x 16DDR

U11

M13L128168 8Mx16-6/NC FOR ENTRY

VDD1DQ02VDDQ3DQ14DQ25VSSQ6DQ37DQ48VDDQ9DQ510DQ611VSSQ12DQ713NC14VDDQ15LDQS16NC17VDD18DNU19LDM20WE21CAS22RAS23CS24NC25BA026BA127A10/AP28A029A130A231A332VDD33

VSS 66DQ15 65VSSQ 64DQ14 63DQ13 62

VDDQ 61DQ12 60DQ11 59VSSQ 58DQ10 57DQ9 56

VDDQ 55DQ8 54

NC 53VSSQ 52UDQS 51

NC 50VREF 49

VSS 48UDM 47

CK 46CK 45

CKE 44NC 43

A12 42A11 41A9 40A8 39A7 38A6 37A5 36A4 35

VSS 34

CB830.1uF

+ CE31

220uF/16v

+ CE29

220uF/16v

CB96

0.1uF

CB1020.1uF

RN13

75x4

1 23 45 67 8

RN19

75x4

12345678

RN5

22x4

1 23 45 67 8

R30

10k

CB79

0.1uF

CB720.1uF

R42 75

+ CE27

220uF/16v

CB610.1uF

RN16

47x4

1 23 45 67 8

CB570.1uF

R50 75

CB105

0.1uF

C473300pF

R33 47

CB820.1uF

CB107

0.1uF

CB510.1uF

C443300pF

CB730.1uF

R38 22

C493300pF

C483300pF

CB890.1uF

R43 22

C343300pF

CB980.1uF

R36 47

CB810.1uF

R28

10k

RN10

47x4

1 23 45 67 8

RN15

47x4

1 23 45 67 8

L16

FBBEAD/SMD/0805 + CE30

220uF/16v

R39 75

CB1030.1uF

CB106

0.1uF

C463300pF

CB540.1uF

CB800.1uF

CB550.1uF

U12

IC LP2996 DDR Termination SOP8

SD2 GND1

VSENSE3VREF4 VDDQ 5AVIN 6PVIN 7VTT 8

CB112

0.1uF

CB91

0.1uFCB900.1uF

C363300pF

RN2

75x4

1 23 45 67 8

CB880.1uF

RN22

75x4

1 23 45 67 8

RN1

22x4

1 23 45 67 8

+ CE2547uF/16v

CB108

0.1uF

C373300pF

RN4

75x4

12345678

RN23

75x4

1 23 45 67 8

CB780.1uF

RN8

75x4

1 23 45 67 8

CB690.1uF

CB990.1uF

CB660.1uF

CB92

0.1uF

CB860.1uF

RN3

22x4

1 23 45 67 8

R49 22

CB620.1uF

RN21

75x4

1 23 45 67 8

CB109

0.1uF

R44 75

CB870.1uF

R35 47

CB750.1uF

CB113

0.1uF

CB590.1uF

U13 CM1117-2.5V

SOT223/SMD

IN3

AD

J/G

ND

1

OUT 2

RN11

75x4

1 23 45 67 8

R37 75

8M x 16DDR

U10

M13L128168 8Mx16-6

VDD1DQ02VDDQ3DQ14DQ25VSSQ6DQ37DQ48VDDQ9DQ510DQ611VSSQ12DQ713NC14VDDQ15LDQS16NC17VDD18DNU19LDM20WE21CAS22RAS23CS24NC25BA026BA127A10/AP28A029A130A231A332VDD33

VSS 66DQ15 65VSSQ 64DQ14 63DQ13 62

VDDQ 61DQ12 60DQ11 59VSSQ 58DQ10 57DQ9 56

VDDQ 55DQ8 54

NC 53VSSQ 52UDQS 51

NC 50VREF 49

VSS 48UDM 47

CK 46CK 45

CKE 44NC 43

A12 42A11 41A9 40A8 39A7 38A6 37A5 36A4 35

VSS 34

C423300pF

CB95

0.1uF

CB93

0.1uF

CB700.1uF

+ CE26220uF/16v

CB1040.1uF

C413300pF

RN17

75x4

12345678

CB1000.1uF

CB670.1uF

RN6

75x4

12345678

R47 22

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

VGASDA

BLU_GND

HSYNC_VGA

GRN_GND

VGAVSYNC#RED_GND

VGASCL

VGA_PLUGPWR

VGA_PLUGPWRVGA_PWR

VGA_IN_LVGA_IN_R

VGASDA

VGASCL

VGA_SDA

GND

RED_GND

GRN_GND

BLU_GND

VGA_SCL

RED

GREEN

BLUEHSYNC#

VSYNC#

HSYNC#

VSYNC# VGAVSYNC#

HSYNC_VGA

VGA_R

BLUE

REDGREENVGA_L VGA_IN_L

RSRXDRSTXD

RSRXD

RSTXD

VGA_IN_R

RED

RED_GND

GREEN

GRN_GND

BLU_GND

BLUE

GND

GND

VSYNC#

HSYNC#

VCC

VGA_PLUGPWR

VGA_PLUGPWR

VCC

VCC

VCC

VCC

VCC

BLU_GND 8

RED_GND 8VGAVSYNC# 3HSYNC_VGA 3

GRN_GND 8

VGA_IN_R 12VGA_IN_L 12

RED 8GREEN 8BLUE 8

RSTXD 1RSRXD 1

Title

Size Doc Number Rev

Date: Sheet o f

VGA IN&PC AUDIO IN V1.2

B


Modified by Bin_wang.22/7/05

Change by MICO

Change by MICO

R56 15K

C500.1uF

R58 15K

D15SOT23/SMD

1 3

2

D2

DIODE SMD1N4148/SMD

C515pF

D16

SOT23/SMD

1 3

2

R60

75K

L17

FBBEAD/SMD/0603

R5410k

D17

SOT23/SMD

1 3

2

R

L

P2

PHONEJACK STEREO

PHONEJACK/DIP

1234G

K1 K2 K3 K4 K5

D3

DIODE SMD1N4148/SMD

L18

FBBEAD/SMD/0603

CB115

0.1uF

R59

75K

R612.2k

D13

SOT23/SMD

1 3

2

R57 100

R5310k

P3

D-SUB15 FEMALEDSUB15/DIP/F

1617

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

R622.2k

R55 100

D14

SOT23/SMD

1 3

2

U14

EEPROM 24C02


A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CB2SWB

CR2SWB

Y2_GNDB

CB2_GNDB

CR2_GNDB

TU_VCC

CB1SWB

CBQ

GNDSY QY2SWBY1SWB

CB2SWBGNDS

CR1SWB

CRQCR2SWB

YPBPR2_LYPBPR2_R

AF1_OUTSIF1_OUT

CB_GND

Y_G ND

SOY

Y

CR_GNDC R

CB

SDASCL

Y_G ND

CB_GND

CR_GND

CB1_INB

AF1_OUT

TV_GNDTV

TUNER_12V

Y1_GNDB

CB1_GNDB

CR1_GNDB

AV_LAV_R

CR1_INB

Y1SWB

CB1SWB

CR1SWB

ORO2

YPBPR1_LYPBPR1_R

SIF1_OUT

YPBPR1_R

CR2B

Y1_GNDB

Y1_GNDB

CR1_GNDB

Y2_INB

CR2_INB

CB1_GNDB

CR1_GNDB

CR2_GNDB

YPBPR1/R YPBPR1/L

YPBPR2/R YPBPR2/L

SC_INSC_GND1 SY_GND1

S Y_IN

ORO2

CB2_GNDB

CB1_GNDB

Y2_GNDB

OGO6

DVI_LDVI_R

AV2_INAV2_GND

AV2_RAV2_L

CB3B

Y3_GNDB

CB3_GNDB

CR3_GNDB

Y3B Y3SWB

CR3SWB

CB3SWB

CBQ

CB

GNDSYY3SWBY Q

CB3SWBGNDS

CRQ

C RCR3SWB

GPIO_DVD0GPIO

CB1B

OGO[0..6]

SDASCL

AV/LAV/R

TU_12V

+12V

S Y_INSY_GND1SC_INSC_GND1

DVI/R

AV/L

YPBPR1_LYPBPR1/L

YPBPR1/R

AV/R AV_R

DVI/L

YPBPR2/R

Y1_INB Y1B

AV1_GND

AV1_R

AV1_IN

CR2_INB

CB2B

Y2_INB Y2B Y2SWB

CB1_GNDB

CR3B

Y1_GNDB

Y3 SOY

Y2 SOY

Y1 SOY

Y1 SOYY2 SOYSOYQ SOY

Y3 SOYSOYQ

AV2_R

AV1_L

D VD/R

DVD/L

AV2_L

AV1_R

DVD+5VDVD/CR_IN

GPIO_DVD0

DVD/CB_IN

DVD+5V

GNDGND

DVI/R

DVI/L

DVD/CB_IN

DVD/Y_GND

DV D/Y_IN

DVD/CB_GND

DVD/CR_GND

Y1_GNDB

DV D/Y_INDVD/CR_GND

CR1_GNDB

D VD/R

DVD/CR_IN

DVD/Y_GND

DVD/L

YPBPR2/L YPBPR2_L

TVTV_GNDAV1_INAV1_GND

AV2_GNDAV2_IN

CR1B

DVD/CB_GND

AV1_L

AV_L

DVI_L

DVI_R

YPBPR2_R

CB2_INB

CR1_GNDB

CB1_GNDB

DVD+5V

GPIO_DVD2

DVD_IR

CB2_INB

Y1_INB

CB1_INB

CR1_INB

I R

I R

GPIO_DVD2

GPIO_DVD0OGO6

SOYQ SOY

Y Q Y

CBQ CB

CRQ C R

GPIO

AV1_L

AV1_R

AV/L

AV/R

DVI/RGNDDVI/LGND

TUNER_12V

VCC

VCC

VCC

TU_VCC

TU_12V

VCC

VCC

VCC

VCCVCC

VCC

VCC

VCCVCC

VCC

VCC VCC

+12V

VCC

VCC

VCC

VCC

VCC

VCC

VCC VCC

VCC

VCC

VCC

CB 8

SOY 3CR_GND 8

Y 8

CR 8CB_GND 8

Y_GND 8

SDA 1,10SCL 1,10

TUNER_12V 1

YPBPR2_R 12YPBPR2_L 12

SIF1_OUT 8AF1_OUT 8

AV_L 12AV_R 12

ORO2 3

YPBPR1_L 12YPBPR1_R 12

OGO6 3

DVI_L 12DVI_R 12

GPIO_DVD0 3GPIO 3,10

OGO[0..6] 3,9,13

+12V 1,10,13,14

SY_IN 8SY_GND1 8

SC_GND1 8SC_IN 8

TV 8,12TV_GND 8AV1_IN 8,12AV1_GND 8

AV2_GND 8AV2_IN 8,12

GPIO_DVD2 3IR 3,11

Title


Date: Sheet o f

VIDEO IN & TUNER IO V1.2

C


NEARLY YPBPR2-CON.

TUNER IN

NEARLY YPBPR1-CON.

COMPONENTS SWITCH.

AV1 & S-VIDEO AUDIO IN

EMC Ready

8/18 modify by steven

9/05

Change by MTK

Change by MICO

ADD BY MICO

+

CE85

22uF/25v

P4

RCA1X3RCA5/9P/Y

31

46

79

2

5

8

R12375K

R312 0

U26

IR7314S11 G12 S23 G24 D2 5

D2 6D1 7D1 8

D9BAV99

1 3

2

J6


1234

R78 0

R28547k

D8BAV99

1 3

2

R27647k

+ CE421000uF/16v

C52100pF

FB7 0

R95

4.7k

J8


1234

FB4 0

R269

10K

R7975

R1210k

FB11 0

R27947k

R12175K

R313 0

+

CE87

22uF/25v

D7BAV99

1 3

2

R107 4.7K

R8615K

+

CE83

22uF/25v

R9415K

L19FB

C117100pF

JP1CON\SVHS

21

34

5

6

7

L22

FB

FB10 0

R69 0

P7

RCA2RCA2/4P/DIP

3

2

1

45

R351 0/NC

FB3 0

L21FB

R10075

D5BAV99

1 3

2

FB12 0

R28247k

J9

5x1 W/HOUSING R.A.PH5/2.5

12345

R11875K

R9715K

U17

CD 4052BCSOP16/SMD

3X11

0X12

2Y2

0Y1

1Y5 Y 31X14

A10B9

X 13

3Y4VEE 7

INH 6

VCC 16

VSS 8

2X15

R28347k

R8415K

R27547k

J7

10x1 W/HOUSING

PH10/2.0

123456789

10

C127100pF

P5

RCA2RCA2X2/6P/DIP

3

2

1

4

56

+CE39 22uF/10V

+CE34 22uF/10V

R6710K

R65 0

R71 0

C122 4.7nF

FB13 0

C124 4.7nF

U16

IDTQS3VH257/TIV330TSSOP16/SMD

I1B6

I0A2I1A3

S1

YA4I0B5

YB7GND8

I0D 14E# 15

I1D 13

I0C 11YD 12

VCC 16

I1C 10YC 9

+

CE86

22uF/25v

R6475

R8975

R11975K

R27447k

D6BAV99

1 3

2

R10315K

L23

FB

C128100pF

+CE36 22uF/10V

R63 0

R74 0

R10215K

+CE40 22uF/10V

R350 0/NC

L48

FBBEAD/SMD/1206

C530.1uF

R28147k

+CE32 22uF/10V

+

CE82

22uF/25v

R27847k

FB5 0

R6810K

R72

75

R12075K

R7075

+CE38 22uF/10V

R26722KR9215K

C129100pF

R30010K

R299

10K

C540.1uF

R1110k/NC

R98 0

+CE33 22uF/10V

+

CE84

22uF/25v

R27247k

C123 4.7nF

R8715K

+CE41

1000uF/16v

Q22N3904SOT-23

1

23

D12BAV99

1 3

2

R6675

R26822K

R12475K

C130100pF

R76 0

D10BAV99

1 3

2

D11BAV99

1 3

2

J5

CON12PH12/2.0

123456789101112

R28047k

R311 0

FB6 0

R12275K

R314 0

D4BAV99

1 3

2

U15

IDTQS3VH257/TIV330TSSOP16/SMD

I1B6

I0A2I1A3

S1

YA4I0B5

YB7GND8

I0D 14E# 15

I1D 13

I0C 11YD 12

VCC 16

I1C 10YC 9

+CE35 22uF/10V

R85 0

CB1160.1uF

R27747k

+CE37 22uF/10V

P6

RCA1X3RCA2X2/6P/DIP

12

34

56

R7575

Q32N3904SOT-23

1

23

L20FB

R7775

C131100pF

R12575K

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

CVBS1+CVBS1

CVBS1-

BLUE

RED

GREEN

CB-

CB+

CR+

Y -

Y+

C R-

RED+

BLUE+

GREEN-

RED-

GREEN+

BLUE-

S Y-

SY+

SC-

SC+

CVBS0+

CVBS0-

CVBS1+

CVBS1-

TV

AF1_OUT

SIF1_OUT

SIF1_OUT

MPX1

MPX2

VGASOG

GRN_GND

BLU_GND

RED_GND

Y

C R

CB

SOY

SC+

SC-

S Y-

Y

C R

S Y

CB

SY+

BLUE+

GREEN+

GREEN-

BLUE-

RED+

RED-

CVBS1_GND

TV_GND

AV1_IN

AV1_GND

CB_GND

Y_G ND

CB_GND

CR_GND

AF1_OUT

CB+

CB-

CR+

Y+

C R-

Y -

MPX2

MPX1

VGASOG

SC_GND

SY_GND

CVBS0+CVBS0

CVBS0-

RED RED_IN

BLUE

RED_GND

GREEN

GRN_GND

BLU_GND

BLUE_IN

GREEN_IN

CVBS2+CVBS2

CVBS2-

CVBS2+

CVBS2-

AV2_GND

AV2_IN

Y_G ND

CR_GND

SY_GND1

SC_GND1

SC_IN

S Y_IN

SC

S Y_IN

SY_GND1

SC_IN

SC_GND1

AV1_IN

AV1_GND

TV

TV_GND CVBS0_GND

AV2_IN

AV2_GND CVBS2_GND

RED 6

GREEN 6

BLUE 6

CB+ 3

CB- 3

CR+ 3

CR- 3

Y- 3

Y+ 3

BLUE+ 3

GREEN- 3

RED+ 3

RED- 3

GREEN+ 3

BLUE- 3

SY- 3

SY+ 3

SC- 3

SC+ 3

CVBS0+ 3

CVBS0- 3

CVBS1+ 3

CVBS1- 3

TV 7,12

AF1_OUT 7

SIF1_OUT 7

MPX2 3

MPX1 3

VGASOG 3

BLU_GND 6

GRN_GND 6

RED_GND 6

CR 7

CB 7

Y 7

SOY 3,7

TV_GND 7

AV1_IN 7,12

AV1_GND 7

Y_GND 7

CB_GND 7

CR_GND 7

CVBS2+ 3

CVBS2- 3

AV2_GND 7

AV2_IN 7,12

SY_IN 7

SY_GND1 7

SC_GND1 7

SC_IN 7

Title


Date: Sheet o f

AUDIO/VIDEO IN CIRCUIT V1.2

C


FROM TunerOUTPUT

INPUT

Close VGA input interface Close to MT8205

Close to 8205.

Close to 8205.

R131

100

FB8

0

L24

FBBEAD/SMD/0603

FB1

0 C70

47nF

C72

47nF

FB9

0

L25

FB

R146 0

C5615pF

R152

75

R90 18

R154 0

C6815pF

R128

100

R108

0

R158 68

R156

75

R147 8.2K

C865pF

C71330pF

R11156

C8515pF

C66

47nF

C6215pF

R143

22

R8256

C905pF

C60

47nF

C8415pF

C69

47nF

C8015pF/NC

R155 68

R151 68

R11075

R105

18

C935pF

C55

47nF

R132

0

C8115pF/NC

+

CE44

47uF/16v

C88

4.7nF

C64

47nF

C57

47nF

L28

FBBEAD/SMD/0603

R80 18

R136

100

C91

47nF

R11675

C82

47nF/NC

L29

FB

R148

0

R141

100

C61

47nF

R144

0

C89

47nF

C87

47nF

C83

47nF

C75

47nF

C63

47nF

R140

22

C65330pF

R138

0

R149 39k

C92

47nF

C79

47nF

R153 100

R157 100

+

CE43

47uF/16v /NC

L26

FBBEAD/SMD/0603

C67

47nF

L27

FB

FB2

0

R114

0

C59330pF

C76

47nF

C58

47nF

FB14

0

C74330pF

C73

47nF

R135

22

R159

75

C77330pF

C94

47nF

R142

0

C78

47nF

R9356

R133

100

R145

22

R160 100

R150 39k

R130

22

R137

100

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

DDCDVISDA

DVIPWR

DVIHSYNC0

DVISCL

VI[0..23]

DVIVSYNC0

DVI16DVI17DVI18DVI19

DVI12DVI13

DVI8DVI9DVI10

DVI15DVI14

DVI11

DVI4

DVI6DVI5

DVI0

DVI2DVI3

DVI1

VI3VI2VI1

DVI7

VI0

VI7VI6VI5VI4

VI11VI10VI9VI8

VI15VI14VI13VI12

VI19VI18VI17VI16

VI23VI22VI21VI20DVI20

DVI21DVI22DVI23

DATA1+

DV

ISC

DT

DVISCDT

DV

IPD

O#

DVIPVCC

DVIPDO#

DVIPVCC

DVIAVCC

DVI18DVI17DVI16

DVI19DVI20

DATA0-

DVI21

DV

I0

DV

I2

DVI23

DV

I1

DVI22

DATA1-

CLOCK+CLOCK-

DV

I3D

VI4

DDC_SDA

8205UP1_2

DVIRST#

DV IHSYNC

DV

I5

DVIVSYNC

DV

I6

DVIPWR

DVIODCK

DATA0+

DVIDE

DV

I7

DDCDVISCL

DVIRST#

DVISCL

DVIPWR

EXT_RST

HS_DJTR

DVIAVCC

OCK_INVCTL3

DV

IPD

#

DVISDA

DV

ISD

A

DVICAB 8205UP1_2

DVIODCK0

DVIDE0DATA2+DVIVSYNC0DVIHSYNC0

DATA2-

DATA1+

DATA0-DATA0+

DATA1-

DVIDE0

CLOCK+CLOCK-

DV

I13

DV

I10

DV

I9

DV

I11

DV

I8

DV

I12

DVISCLDVISDA

DVI14

DDC_SCL

DVI15

DV

ISTA

G

DVIODCK0

OGO4

DV

IPIX

S

DV IHSYNC

DVISCL

DVIVSYNCDVIDE

DVISTAGHS_DJTR

DVIPWR

DVIODCK

F_A21

OGO4

DVISDA

DDCDVISCL

DVIPWR

OCK_INV

F_A21

DDCDVISDA

DDCDVISCLDDCDVISDA

DATA2-DATA2+

DVIPIXS

DVIPDO#DVIPD#

DVIPWR

DVIPWR

DVIPWR

DVIPWR

M_S

#

M_S#

DATA2-

DATA2+

GND

DATA1+

GND

DATA1-

GND

DATA0+

GND

DATA0-

GND

CLOCK+

GND

CLOCK- DDC_SCL DDC_SDA

DVI_PLUGPWR

GND GND

GND

GND

DVI_PLUGPWR

DVICAB

DVIPWR DVIPWRDVIPWR DVIPWRDVIPWRDVIPWR DVIPWR

DVIPWR

DVI_PLUGPWR

DVIAVCC

DV33

DV33A

DVIPWR

DVI_PLUGPWR

DV33A

DVIPWR

DVIPWR

DVIPWR

DVIPWRDVIPWR

DVIPWR

DVIPWR

VCC

VCC

VCC

VCCVCC

VCC

VCC VCC VCC VCC

VCC

DVI_PLUGPWR

VI[0..23]

8205UP1_2

DVIHSYNCDVIVSYNC

DVIODCKDVIDE

DVISCLDVISDA

OGO4

F_A21

Title


Date: Sheet o f

DVI INPUT V1.2

C


When use Sil169/Sil1161 ADD R333

RED

GREEN

BLUE

CHANGE

WHEN SIL161 ADD R173 R174

WHhen use Sil161 R326 NC,Add R172When use Sil169//Sil1169 R172 NC,Add R326

WHEN Sil169/ Sil1169 R173 R174 NCWHEN USE Sil169/sil1169 ADD

CHANGE

DVISCL REPLACE OCK_INV NETDVISDA REPLACE ST

WHEN USE Sil169 add R327 R332

Add by MTK

WHEN USE Sil1169 ADD R345,NC R175WHEN USE Sil169//Sil161 ADD R175 , NC R345

When Sil169/Sil161 R346 NCAdd R347

WHEN USE Sil161 NC R331 R332

WHEN USE Sil1169 add R331 R332

Add By MTK

Add By MTK

ADD BY MTK

C102220pF

R3330

C10110uF/10v

R165390

C112220pF

C9510uF/10v

D31SOT23/SMD

1 3

2

L33

FB BEAD/SMD/0603

C11110uF/10v

R88 0/NC

R0603/SMD

R34710k/NC

CB118

0.1uF

R16810k

R17110k

R162 100

C10510uF/10v

RN28

33x4

12345678

R17310k/NC

C10910uF/10v

R91

0/NCR0603/SMD

TP8

R16310k

R3254K7

R1720.1uF

R330 0

RN25

33x4

12345678

D30SOT23/SMD

1 3

2

C108220pF

R176R/NC

TP11

R3320

SiI 161B

U18

SiI 169TQFP100/SMD

OCK_INV100 RESERVED99 PGND98 PVCC97

ST

3P

D#

2

EXT_RST96 AVCC95 RXC-94 RXC+93

RX0+90

AVCC88 AGND87 RX1-86 RX1+85 AVCC84 AGND83 AVCC82 RX2-81

QE16 30OVCC 29OGND 28QE15 27QE14 26

QE

1325

QE

1224

QE

1123

QE

1022

QE

921

OE

820

OG

ND

19O

VC

C18

QE

717

QE

616

QE

515

QE

414

QE

313

QE

212

QE

111

QE

010

PD

O9

SC

DT

8S

TAG

_OU

T7

VC

C6

GN

D5

RX0-91AGND92

HS

_DJT

R1

QE17 31QE18 32QE19 33QE20 34QE21 35QE22 36QE23 37VCC 38GND 39CTL1 40CTL2 41CTL3 42OVCC 43ODCK 44OGND 45DE 46VSYNC 47

QO

251

HSYNC 48

QO1 50

QO

352

QO

453

QO

554

QO

655

QO

756

OV

CC

57O

GN

D58

QO

859

QO

960

QO

1061

QO

1162

QO

1263

QO

1364

QO

1465

QO

1566

VC

C67

GN

D68

QO

1669

QO

1770

QO

1871

QO

1972

QO

2073

QO

2174

QO

2275

OGND76QO2377OVCC78AGND79RX2+80

QO0 49

PIX

S4

AGND89

R31010k

+C134

1uF/25V/NC

D22

1N4148/SMD

RN31

33x4

12345678

R164100k

R3244K7

R177 0

R3310

C104220pF

TP10

RN27

33x4

12345678

R17010k

C99

0.1uF

D36SOT23/SMD

1 3

2

D37SOT23/SMD

1 3

2

R8110k/NC

R3284.7K/NC

QF4

MOSFET N 2N7002SOT23/SMD1

32

C110220pF

C106220pF

TP12

R3274.7K/NC

R3234K7

D18

DIODE SMD1N4148/SMD

R167 R

R344

R/NC

C98220pF

RN30

33x4

12345678

R17410k/NC

TP9

D33SOT23/SMD

1 3

2

R16910k

L31

FB

P8 DVI-I DIP 34P

123456789

101112

13141516171819202122

2423

2526

2728

29

30

31

3233 34

+ CE45

100uF/16v

C10310uF/10v

D29SOT23/SMD

1 3

2

D35SOT23/SMD

1 3

2

R83 0/NC

D34SOT23/SMD

1 3

2

L32

FB BEAD/SMD/0603

R34510k/NC

R3224K7

RN26

33x4

12345678

C9710uF/10v

R32610K

C100220pF

R34610k/NC

R1750

D38SOT23/SMD

1 3

2

R161 100

R3294k7/NC

C10710uF/10v

C11310uF/10v

D32SOT23/SMD

1 3

2

RN29

33x4

12345678

C96220pF

QF3


32

U19

EEPROM 24C02


R166 0

CB117

0.1uF

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

AP[0..7]AN[0..6]

GPIO

SDA_8205

RGBVS YNCH SYNC

GND

RGB

H SYNCVS YNC

LVDSVDD

GND

SDASCL

R

GND

GND

B

G

CLK1+CLK1-

AN0AP0AN1AP1

CLK1-

AN2AP2

AN4

CLK1+

AP4

AN3

AN5AP5

AP3AP7

LVDSVDD

ORO6

SEL_AP7_IRQ

+12V

SCL_PSDA_P

SCL_8205SCL

SDA

DV33A

DISPEN_PDWN_READY

PDPGO

AN6

AP6CPUGO

SCL1

SCL_P

SDA1

SDA_P

SDA1SCL1

8205UP1_4

ORO5

GPIO

SDA_8205SCL_8205

ORO58205UP1_4

ORO1ORO3

ORO3

ORO1

ORO1ORO3

ORO6ORO6

5VSB

+12V

+12V

DV33A

VCC

5VSB

5VSB

DV33A

DV33A

DV33A

DV33A

5VSB DV33A

5VSB

5VSB

GPIO 3,7

AP[0..7] 3AN[0..6] 3

SDA 1,7SCL 1,7

ORO6 3

CLK1+ 3CLK1- 3

G 3R 3

B 3VSYNC 3HSYNC 3

+12V 1,7,13,14

SDA1 12SCL1 12

SDA_8205 3SCL_8205 3

ORO5 38205UP1_4 3

ORO1 3,14ORO3 3,14

ORO1 3,14ORO3 3,14

Title


Date: Sheet o f

LVDS/CRT OUT V1.2

C


LVDS OUT(Include PDP and 32' LCD LVDS interface)

CRT OUT

WHEN NOT USE PDP ADD L49 R178 R290 R292REMOVE R179 R185 R186 R187 R291 R293

WHEN USE LG V7 PDP ,ADD R185 R286 R179WHEN USE SangsungSD1 PDP ,ADD R186 R187 R185 R286WHEN USE Fujitsu 42 PDP ,ADD R179 R186 R187 R185 R286 R291 R293.REMOVE R178 R290 R292

WHEN USE LG V6 PDP ,ADD R185 R286 ,Must del R193 R194

4.7K REPALAC 47K

Change By Ada

8205UP1_4 Repalce ADIN3ORO5 Repalce ADIN2

CHANGE

Change by MICO

Change by MICO

Change By MTK

R2864.7k

F1

4A/?vFUSE/DIP/P10.0

L49 FBBEAD/SMD/1206

R36110K

R193 0/NC

R30310K

QF1


32

R292 0/NC

+CE48220uF/16v

R291 0/NC

R293 0/NC

R353

10K

R2980

J10

FI-SE30P-HFLVDS/30P/P1.25/S

123456789

101112131415161718192021222324252627282930

J11


12345678

R188 0

R2970

R36210K

R1834.7k

R30110K

R185 0

R178 0/NC

R1824.7k

R18410k

R349

10K

L52FB BEAD/SMD/1206

R36310K

CB1200.1uF

R197

75 1%

R186 100/NC

R352

10K

R348

10K

R296 0

QF2


32

R1804.7k/NC

R187 100/NC

+CE49220uF/16v

R1914.7k

R179 0/NC

R30210K

R196

75 1%

+ CE47330uF/25vC330UF25V/D8H14

R290 0/NC

L34

FB

BEAD/SMD/1206

CB1190.1uF

R36410K

Q42N3904

SOT23/SMD

1

32

R295 0

R1814.7k

R192 0

+ CE46220uF/16v

R195

75 1%

L51FB BEAD/SMD/1206

R189

4.7k

R194 0/NC

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

OBO0

OBO1

OBO2

OBO3

OBO4

OBO5

I R

VOL+C H-CH+

OBO1 MENUTV/AVOBO0

VOL-OBO3

I R

OBO6

OBO7

LED_RED

OBO7

OBO6

PWM0

PWR_GND

Inverter_PWR

BL_ON/OFF

8205UP3_0

Inverter_PWR

Inverter_PWR

SELECT

Inverter_PWR

Dimming

8205UP3_0

PWM0

POW

PWR_GNDINVERTER_PWR

OBO[0..7]

PWR_GND

PWR_GND

LED_GRN

8205UP1_2

PWR_GND

OBO5OBO4

OBO2

TV/AVMENUVOL-VOL+C H-CH+

LED_REDLED_GRN

I R

8205UP1_2

POW

8205UP1_2

5VSB

DV33A

VCC

VCC

VCC

5VSB

5VSB

OBO0 3

OBO1 3

OBO2 3

OBO3 3

OBO4 3

OBO5 3

IR 3,7

OBO6 3

OBO7 3

8205UP3_0 3

PWM0 3,14

PWR_GND 1INVERTER_PWR 1

OBO[0..7] 3

8205UP1_2 3,9

PWR_GND 1

Title


Date: Sheet o f

BACK_LIGHT/KEYPAD V1.2

C


KEYPAD - MAX 8-KEYS

IR & POWER ON LED

Back Light circuit

PANEL INVERTER POWER

FOR AU 32" INVERTER CONNECTOR

External PWM inputfor dimming control

9/05

L35FB

BEAD/SMD/1206

R315

10K

R2040

R209 510

R20310k

L41 FB

Q62N3904SOT23/SMD

1

32

R20710K

R0603/SMD

R. ANGLE

J12

14x1 W/HOUSING DIP14/WH/P2.0/R

123456789

1011121314

R211 4.7K

R316

10K

R205

4.7k

R19910k

R201 4.7k

J19

CON9

123456789

R210 0

R317

10K

+ CE51470uF/50v

R212 4.7K

L38 FB

CB1220.1uF

R206 510

R200

100k

R318

10K

R109

10K

L40 FB

Q52N3904SOT23/SMD

1

32

J20

CONN RCPT 5

12345

Q72N3906

1

32

J14


123456789

10111213

R319

10K

CB1230.1uF

R. ANGLE

J13

10x1 W/HOUSING R.A.DIP10/WH/P2.0/R

123456789

10

L42 FB

R320

10K

R202R

L36FB

BEAD/SMD/1206

Q82N3906

1

32

L37 FB

CB1210.1uF

+ CE50470uF/50v

L39 FB

R20810KR0603/SMD

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

SDA1

SCL14

SDA14

SC

L14

COD_VOUTR

COD_VOUTL

VGA_IN_RVGA_IN_L

MUTE

CODHPOUTR

CODHPOUTL

CODHPOUTR

CODHPOUTL

YPBPR1_L

YPBPR2_LYPBPR1_R

YPBPR2_R

DACLRC

ADCREFP

DV DD

HPVDD

VMIDADC

PWM0

DV33

DV

DD

DACBCLKDACMCLK

DACLRCAOSDATA1

DOUT

DACBCLKDACMCLK

DA

CL

RC

DOUT

HPVDD

DACMCLKDACLRC

SCL1

COD_VOUTLCOD_VOUTR

SD

A14

DACBCLK

HP

VD

D

VMIDDAC

ADCREFP

VMIDADC

L_BYPASSDACVA

R_BYPASS

DACBCLKAOSDATA3

DACMCLKDACLRC

AUSPR

AUSPL

+12V

VGA_IN_R

VGA_IN_L

AV_R

AV_L

YPBPR1_R

YPBPR1_L

YPBPR2_R

YPBPR2_L

GND

R_BYPASSL_BYPASS

AV1_IN

V_BYPASSTV

ORO4

AOSDATA1AOSDATA3

DVI_R

DVI_L

AV2_IN

ORO7

DVI_LDVI_R

TVAV_LAV_R

DACVA

SDA1SCL1

V_BYPASSOGO7 LINE_MUTE

ORO4ORO7

HPVDD_OGO7PWM1

PWM1

AV1_INAV2_IN

AUSPR

AUSPLGND

MUTE

GND

GND

GND

GND

DVDD

VCC

DV33

HPVDD

VCC

VCC

VCC

VCC

5VSB

VGA_IN_R 6VGA_IN_L 6

MUTE 3

YPBPR1_L 7

YPBPR2_R 7

YPBPR1_R 7YPBPR2_L 7

AOSDATA1 3AOSDATA3 3

PWM0 3,11

DOUT 3DACLRC 3DACMCLK 3DACBCLK 3

+12V 1,7,10,13,14

ORO4 3ORO7 3

DVI_L 7DVI_R 7

TV 7,8AV_L 7AV_R 7

SDA1 10SCL1 10

OGO7 3PWM1 3

AV1_IN 7,8AV2_IN 7,8

Title


Date: Sheet o f

WM8776/WM8766/AUDIO CODEC V1.2

C


MUST USE SHIELD CABLE

TWO WIRE SERIAL CONTROL DEVICE ADDRESS 0x34h

TO AUDIO BD

AUDIO BYPASS.

A/V Bypass

SPK SWICTH(PDP) BY MICO

OGO7 Repalce ADIN0 -----MTKPWM1 Repalce ADIN1 -----MTK

Change

R215 100k

L43

FB

CB1260.1uF

R234 33

L45

FB

R216 100

+

CE60 10uF/25v

R214 100k

+

CE71

10uF/25V

CB1270.1uF

+ CE7247uF/16v

R238 43,1%

R30710K

CB1321uF

R224 100k

R217 100k

+ CE6210uF/25v

CB1310.1uF

+

CE61 10uF/25v

+

CE73

10uF/25v

R22

050

k

CB1250.1uF

J16

5x1 W/HOUSINGPH6/2.0

123456

+ CE74100uF/16V

R213 100k

CB1300.1uF

R226 100k

+

CE64 10uF/25v

R1433

C125

10uF/10v

U20

WM8776

AIN2L1AIN1R2AIN1L3DACBCLK4DACMCLK5DIN6DACLRC7ZFLAGR8ZFLAGL9ADCBCLK10ADCMCLK11DOUT12

AD

CLR

C13

DG

ND

14D

VD

D15

MO

DE

16C

E17

DI

18C

L19

HP

OU

TL20

HP

GN

D21

HP

VD

D22

HP

OU

TR23

NC

24

NC 25VOUTL 26VOUTR 27VMIDDAC 28DACREFN 29DACREFP 30AUXR 31AUXL 32VMIDADC 33ADCREFGND 34ADCREFP 35AVDD 36

AG

ND

37A

INV

GR

38A

INO

PR

39A

INV

GL

40A

INO

PL

41A

IN5R

42A

IN5L

43A

IN4R

44A

IN4L

45A

IN3R

46A

IN3L

47A

IN2R

48

R237 33

R334

10K

C116100pF

U23

BA7612F

IN11 OUT 8A2 VCC 7B3 IN3 6IN24 GND 5

+

CE65 10uF/25v

FB15 FBBEAD/SMD/0805

R30610K

R236 33

+ CE75100uF/16V

R227 100k

R13 0

C126

10uF/10v

R24075/NC

C118 1uF

+C114

10uF/25v

+ CE7010uF/25v

+

CE55 10uF/25v

R231

10k

+

CE54 10uF/25v

C115100pF

R235 33

R219 100k

R2291k

R1010k

C119 1uFR23975

CB1280.1uF

+

CE56 10uF/25v

R232

10k

+

CE59 10uF/25v

+ CE6910uF/25v

+ CE6710uF/25v

CB1240.1uF

R225 100k

R2330R0805/SMD

+

CE53 10uF/25v

J15

CON8

12345678

R22

150

k

U22

CS4334 2-CH AUDIO DACSOP8/SMD

SDATA1DEM#/SCLK2LRCK3MCLK4 AOUTR 5AGND 6VA 7AOUTL 8

+CE76 220uF/16v

R24175/NC

R218 100

R222 100k

R23010k

+

CE57 10uF/25v

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

+12V

TXD

DVIVSYNC

DVIODCK

RXD

DVIHSYNCDVIDE

READY#

DACLRC

DACMCLKDACBCLK

REQUEST#

OGO5OGO6

VI[0..23]

8205UP1_3

OGO3OGO1OGO2OGO0

OGO5

SW

+12V12V

PCRXDPCTXD

12V

5V

5V

TXD

RXD_2

TXD_2

RXDWE#PWR#

PCTXD

READY#

WE#

TXD_0

RXD_0

SW

SW

PCRXD

PWR#

TXD_2

RXD_2

PCTXD

PCRXD

GND

RXD

TXD

REQUEST#

VI3VI2VI1VI0

VI4VI5VI6VI7

VI8VI9VI10VI11

VI12VI13VI14VI15

VI18VI19

VI16VI17

VI22VI23

VI20VI21

OGO4

REQUEST0#

RXD_2

REQUEST0#

TXD_2

READY0#

TXD_0

READY0#

8205UP1_3

GND

RXD_0

OGO4

DVIODCKDVIDEDVIVSYNCDVIHSYNC

OGO2OGO0

OGO1OGO3

+12V

DV33A

VCC

DV33A

5VSB

5VSB

DV33A

DV33A

DV33A

5VSB

DV33A

DV33A

DV33A

DV33A

5VSB

DV33A

DV33A

+12V 1,7,10,14

DACBCLK 3,12DACMCLK 3,12

DACLRC 3,12

READY# 3

REQUEST# 3

TXD 1,3RXD 1,3

DVIHSYNC 3,9DVIVSYNC 3,9

DVIDE 3,9DVIODCK 3,9

OGO5 3OGO6 3,7

VI[0..23] 3,9

8205UP1_3 3

OGO3 3OGO1 3OGO2 3OGO0 3SW 3PCRXD 1PCTXD 1

WE# 3PWR# 5

OGO4 3,9

Title


Date: Sheet o f

ATSC INTERFACE V1.2

Custom


Trace width of 12V>30milTrace width of 5V >40mil

LO = > DTV BOARD POWER ON

HI = > DTV BOARD POWER OFF

"GND Need Very Strong"TXD_0:MT5351 TransmitRXD_0:MT5351 ReceiverTXD_2:MT5351& MT8205 CommunicationRXD_2:MT5351& MT8205 Communication

Add by MTK

PC <---> MT5351 U0FunctionSW

MT5351 U2 <---> MT8205

MTK Modify

PC -----> MT5351 U0RXPC <---> MT8205

0

1

WHEN OGO4 HIGH , DVI OUPUTWHEN OGO4 LOW ,ATSC OUPUT

ADD 22/9

R3390/NC

R24810k

J17

DIP8/W/H/P2.54

12345678

Q102N3904

SOT23/SMD

1

32

C1211uF

R256

0/NC

74LVC00A/NC

U29

1234567 8

91011121314

U25

IDTQS3VH257TSSOP16/SMD

I1B6

I0A2I1A3

S1

YA4I0B5

YB7GND8

I0D 14E# 15

I1D 13

I0C 11YD 12

VCC 16

I1C 10YC 9

R25210k/NC

U33 74LVC244A

GND10 VCC201G 1

1A1 21A2 41A3 61A4 8

2G 19

2A1 112A2 132A3 152A4 17

1Y118 1Y216 1Y314 1Y412

2Y19 2Y27 2Y35 2Y43

J18

CON50

123456789

1011121314151617181920212223242526272829303132333435363738394041424344454647484950

JP3

3x1JP3/DIP/P2.54

123

Q112N3904

SOT23/SMD

1

32

U31 74LVC244A

GND10 VCC201G 1

1A1 21A2 41A3 61A4 8

2G 19

2A1 112A2 132A3 152A4 17

1Y118 1Y216 1Y314 1Y412

2Y19 2Y27 2Y35 2Y43

R24710k

U30 74LVC244A

GND10 VCC201G 1

1A1 21A2 41A3 61A4 8

2G 19

2A1 112A2 132A3 152A4 17

1Y118 1Y216 1Y314 1Y412

2Y19 2Y27 2Y35 2Y43

R24410k

U24

IRF7314SOIC8/SMD

S1 1G1 2S2 3G2 4D25 D26 D17 D18

C1201uF

R2510

74HCT04A/NC

U28

1234567 8

91011121314

L46FB/NC

R25510k

CB1330.1uF

R3380/NC

C13556pF

Q92N3904SOT23/SMD

1

32

+CE77

220uF/16v

L47FB

U32 74LVC244A

GND10 VCC201G 1

1A1 21A2 41A3 61A4 8

2G 19

2A1 112A2 132A3 152A4 17

1Y118 1Y216 1Y314 1Y412

2Y19 2Y27 2Y35 2Y43

R25410k

R25310k

R24222k

R245

0

CB1340.1uF

R24610k

R250

0/NC

R24322k

+CE78

220uF/16v

R24910k/NC

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

+12V

GND

RELAY_ON

VS_ON

5VSBRELAY_ON

VS_ON

5VD

5VD PWM0

PWM0

ORO1ORO3

ORO1

ORO3

ADIN4

ADIN4

5VSB

5VSB

VCC +12V

DV33A

DV33A

DV33A

DV33A

+12V 1,7,10,13

PWM0 3,11

ORO1 3,10ORO3 3,10

ADIN4 3

Title

Size Doc Number Rev

Date: Sheet o f

PDP interface V1.2

A


DEL ACD Net--------MTK

Change--------MTK USE WHEN LG V6

USE WHEN LG V6

R340

4.7k

R35710K

+ CE79220uF/16vC220UF16V/D6H11

Q152N3904

1

32

R35410K

R34310k

R2601k

R360 0/NC

R2944.7k/NC

R358 1k

Q132N3904

1

32

R28810k/NC

R2874.7k/NC

TP3

R2571k

R356 0/NC

CN2

DIP7/P2.0

1234567

R2621k

+ CE80220uF/16vC220UF16V/D6H11

Q122N3904 1

32

R28910k/NC

R355 1k

Q162N3904

1

32

R259

1k

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

Title

Size Doc Number Rev

Date: Sheet o f

V1.2

A


History

From V0.1 To V1.2 change item:

1,Add R109-10K;R107-4.7K;C135-56pF;0603-R88,R91,R104,R106-0 .0805-R96,R99,R101-0欧姆欧姆

2,Reset IC 5V Supply;DVI AUDIO ADD CO增加 NNECTOR J8.

3,ADIN4 CHANGE TO PWM0

1 2 3 4 5 6 7 8

A

B

C

D

87654321

D

C

B

A

Title

Number RevisionSize

D

Date: 21-Sep-2005 Sheet of File: D:\正在进行的项目\LCD TV\LCD TV.DdbDrawn By:

MUTEC

MUTEC

AUDPLAUDPR

MUTE

AUDPL

AUSPL

MUTEC

AUSPR

+24V

AUDPR

1 2R574K7

5%

12

C11470NF

FILM

12

C17390PFNPO

PIN1

NIN2

AGND3

EN4 BS 5

VPP 6

SW 7

PGND 8U3

ATA-120

D1

MBRS130LTR

1 2R15 47K

5%

PIN1

NIN2

AGND3

EN4 BS 5

VPP 6

SW 7

PGND 8U1

ATA-120

1 2R6310K

5%

1 2R48 1k8

5%

C2100U/35V

1 2C32

1UFX5R

C2010UF

+

12

C231000UF/35V

1 2C304.7nFNPO

12

R3610K

5%

1 2R584K7

5%

1234

J6

4x1 W/HOUSING

12

R23

10K

5%

+

1 2

C38

1000UF/25V

1234

J1

4x1 W/HOUSING

1 2R16

100K 5%

+5

-6

OUT 7

U5B

RC4558

1 2R52 47K

5%

+

12

C25

100UF/25V

1 2R6447K

5%

1 2R49 4K7

5%

12R18

10K

5%

12

R182K

5%

12

C1

22pF NPO

R42

1k

D74.7V

1 2R594K7

5%

12

C451n

1 2C9

1UFX5R

C34

NS

1 2R2

100K 5%

12

C54.7uFX5R

C24

22pF

C12100NF

1 2C31

1UFX5R

12

R6547K

5%

12

C274.7uFX5R

1 2C3

1UFX5R

1 2R50 4K7

5%

1 2R54 10K

5%

12

C7

1UF

X7R

12

C461n

12

R7

10K

5%

1 2L5 10uH

12

R3710K

5%

1 2R12

4K75%

+

12

C10

100UF/25V

12

R17100K

5%

12

R60

100K5%

C41

22pF

12

C35

100NF

X7R

12

R4

100K5%

+3

-2

OUT 1

U5A

RC4558

1 2

R44

0 5%

12

C21

22pF NPO

+

12

C42

100UF/25V

12

C471n

C43

10U/16V

+

12

C4

100UF/25V

12

R810

5%

1 2R51 4K7

5%

12

C16

100NF

X7R

1 2R55 10K

5%

+5

-6

OUT 7

U2B

RC4558

12

R2210

5%

12R3

10K

5%

1 2C84.7nFNPO

12

R1110K

5%C1422UF/16V

12

C28

100NF

X7R

C1922UF/16V

D3

MBRS130LTR

12R4010K

5%

12

C6

100NF

X7R

12

R6147K

5%

D26.2V

12

C481n

C4422U/16V

12

R25

10K5%

1 2L6 10uH

1 2C4922P

12

R9

10K

5%

12R243K

5%

12

R610

5%

+3

-2

OUT 1

U2A

RC4558

C4010UF

12

R1010K

5%

C22

22U/16V

12

C37

1UF

X5R

12

R1482K

5%

1 2R561k8

5%

12

R5100K

5%

1 2R39

4K7 5%

C15

NC

12

R53

100K

5%

12

R19

100K5%

12

C13100N

1 2C5022P

12

R21

10K

5%

1 2R6210K

5%

C26

10U/16V

12

C36390PFNPO

12

R2010

5%

12

C29

1UF

X7R

+

1 2

C39

1000UF/25V

12

R41

10K

5%

11

22

J8

NS

12

C33470NFFILM

1 2R3847K

5%

D46.2V

AGND

AGND

VCC

+24V

+24V

+24V

AGND

AGNDAGND AGND

AGND

+24V

AGND

+24V

AGND

+24V

A

Audio Input

2 2

3 3

4 4

5 5

99

88

77

66

NC

1

M4

GND HOLE

2 2

3 3

4 4

5 5

99

88

77

66

NC

1

M3

GND HOLE

AF1_IN

AF1

AF1

TU_12V

TU_VCC

AF1_OUT

SIF1 SIF1_OUT

SIF1_IN SIF1_OUT

1 21R14 0

1 21R16 0/NC

+1 2CE733uF/16V

1 21R15 0

AF1_OUT

SIF1_OUT TU_12V

TU_VCC

AF1_IN

VCC

SIF1_IN TU_CVBS

TU_SDA

TU_SCL

GN

D1

TH1

GN

D2

TH2

VS_

TUN

ER3

SCL

4

AS

6SD

A5

2nd

SIF

OU

T11

AF-

R9

AF-

L10

CV

BS

12

GN

D3

TH3

GN

D4

TH4

AF

/MPX

14V

S_IF

13

NC

1

NC

2

NC

7

NC

8

TU1

FQ1236-MK3

GNDSGNDS

GNDS

FQ1236 / : NTSC TV

IF

ADDRESS

TUNER

TUNER1 IN

TUNER1

C2 86

SIF1

SIF1_IN

12

1R110R

12

1L3

1.5uH/1.2uH

1 21C5 1NF(22P/27P)

1 21L2 3.3UH(47uH/22uH)

1 21C4 10nF

+

12

CE6

10uF/25v

1 21C6 10nF

12

1R1282R

1 21C1 10nF

1 21R9 0

12

1C8

820pF/560pF

12

1C7

820pF/560pF

12

1R81k

12

1R10220

12

1L4

1.5uH/1.2uH

12

1R71.8K

12

1C9NC

GND V

SIF_12V

GND VGND VGND V

GND V GND VGND VGND V

TUNER1 SIF1 BPFNTSC 4.5MHz PAL 6MHz　

SIF_12VTU_12V

12

CB40.1uF

12

CB50.1uF

1 21L5 FB

1 21L6 FB

+

12

CE8100uF/16V

+

12

CE3100uF/16V

12

CB60.1uF

12

CB30.1uF

+

12

CE9220uF/16V

12

CB70.1uF

+

12

CE4

100uF/16V

+

12

CE5

100uF/16V

TU_VCC

TU_12V SIF_12V

VCC

GNDS

GNDS

GNDS

GNDS

GND V

GND V

VIDEO GROUNDAUDIO GROUND

SDASCL

AF1_OUTSIF1_OUT

TVTV_GND

TV_GND

TVTU_CVBS

12

FB1

0

1 21R2 0

1 21R4 0

12

FB2

0

123456789101112

1J1

CON12

12

1R356

1 21R1

18

GNDS

TU_VCC

GNDS

TU_12V

AV , TUNER I/O

2 2

3 3

4 4

5 5

99

88

77

66

NC

1

M2

GND HOLE

2 2

3 3

4 4

5 5

99

88

77

66

NC

1

M1

GND HOLE

GNDSGNDS

TU_SDA

TU_SCL

12

1C247pF

1 21R5 100

1 2

1R6100

12

1C3

47pF

SCL

SDA

Q52N3904

Q62N3904

Q22N3904

1Q32N3904

12 R34

1K 5%

1 2R35

1K 5%

12C60

10UFX5R

12C59

10UFX5R

12 R29

1K

5%

MUTE

Q3

2N3904

AGND

12 R13

47K 5%

12 R26

47K 5%

Q71015

Q41015

Q12N3906

R271K

LMUTE

AGND

R281k

R30

10k

+

12

C18

NC

+

12

C51

220UF/25V

D5

NC

D6

1N4148

D8

1N4148

D9

1N4148

MUTEB

AGND

AGND

R43

4K7

LOUT

ROUT

AGND

AGND

LOUT

ROUT

12 R66

4K75%

12 R67

4K75%

C541n

C551n

C521n

C531n

12 R46

4K75%

12 R45

4K75%

12 R47

1K85%

12 R33

1K85%

VIDEO OUTLMUTE

AGNDAUSPLAUSPR

1234567

J11

CON7

VIDEO OUT

LOUT

ROUT

K1

G6A-234P

D10

1N4148

+24V

Q82N3904

12

R320R5%

1 2R31

3K3 5%

12

C56100NFX7R

PMUTE

LOUT

ROUT

LOUT

ROUT

INTL INTR

INTL

INTR

EXTL

EXTR

12345

J2

CON5

PGND

EXTRPGND

EXTL

INT: 0EXT: 1 1

2

R68NC/0R5%

123456

J5

CON6

PMUTE

1 2BL1

600 OHM

D11 SR240 +24V

+

12

C571000UF/35V

1 2L1

2mH

123

J7

CON3

12

R70

0R/NC5%

123456

J3

CON6

9V

TU_12V

C61100n

C63100U/16V

Q97805

C62330U/16V

C58100n

9V TU_VCC

D13

1N4001D12

1N4001

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

DV33+5V+12V

VOR[0..7]VOG[0..7]VOB[0..7]VOPCLKVOHSYNCVOVSYNCVODE

U2TXU2RX

U0RXU0TX

AO1MCLKAO1LRCKAO1BCK

REQUEST#READY#

ORESET#

ASPDIF

ASPDIF

ASPDIF

AO1SDATA0

AUD_CTRL

AO1LRCKAO1SDATA0

AO1BCKAO1MCLK

AUD_CTRL

VOR1

VOG3

VOR3

VOB4

VOG2

VOG7

VOB5

U0RX

VOB7

VOB1

U2TX

VOR4

VOG1

READY#

VOG6

REQUEST#

GND

VOB0

VOB3

VOR7

VOG0

VOB6

ORESET#

U2RX

VOB2

U0TX

VOR0

VOR5

VOG4

VOR6

VOG5

VOR2

VODEVOPCLK

VOVSYNCVOHSYNC

AO1MCLK

AO1SDATA0

AO1BCKAO1LRCK

+5V

+12V

+5V

DV33

DV33

DV332,5,6,8

GND2,3,4,5,6,7,8

+5V2,6+12V2

VOR[0..7]5VOG[0..7]5VOB[0..7]5VOPCLK5VOHSYNC5,8VOVSYNC5,8VODE5

U2TX5,8U2RX5,8

U0RX5,8U0TX5,8

AO1MCLK5

AO1BCK5AO1LRCK5

AO1SDATA05

REQUEST#5READY#5

ORESET#4,5,8

ASPDIF5

ASPDIF5

AUD_CTRL5

Title POWER

Size Document Number Rev

Date: Sheet o f

Rev DATEP#History

RA-V1 INITIAL VERSION 2005/06/15

DEVICETYPENAME

POWER +12VPOWER +5V

POWER +5VPOWER +3V3POWER +1V8POWER +3V3POWER +3V3POWER +2V5POWER +1V2

+12V+5V

+5V_tunerDV33_DMDV18DV33AV33DV25DV12

POWER SUPPLYPOWER SUPPLY

TUNER POWERMT5111 POWERMT5111 POWERMT5351 POWERMT5351 ANALOG POWERMT5351 DDR POWERMT5351 POWER

GLOBAL SIGNAL01. INDEX AND INTERFACE02. POWER03. TUNER04. MT5111 ASIC05. MT5351 ASIC06. MT5351 PERIPHERAL07. DDR MEMORY08. NOR FLASH / JTAG / UART

GND GROUND GROUND

MT5111 / MT5351 REFERENCE DESIGN - 4 LAYERSMT5351RA-V2

NS : NON-STUFF

DIGITAL VIDEO OUTPUT

UART (RS232)

DIGITAL AUDIO INTERFACE

SPDIF CIRCUIT

RA-V2 ADDED AUDIO SWITCH / REFINE POWER CIRCUIT 2005/07/14

POWER INPUT FROM MAIN BOARD

DIGITAL OUTPUT

+3.3V

RN3

33x4 RN0603/SMD

7 85 63 41 2

R2 75

CB20.1uFC0603/SMD

CB1420.1uFC0603/SMD

RN10

33x4 RN0603/SMD

7 85 63 41 2

RN8

33x4 RN0603/SMD

7 85 63 41 2

L2 FBBEAD/SMD/1206

RN6

33x4 RN0603/SMD

7 85 63 41 2

CB10.1uFC0603/SMD

FB1

FBBEAD/SMD/0603

R3 75

R4

33R0603/SMD

R50 75

RN7

33x4 RN0603/SMD

7 85 63 41 2

RN9

33x4 RN0603/SMD

7 85 63 41 2

RN5

33x4 RN0603/SMD

7 85 63 41 2

J1


12345678

R49 75

RN4

33x4 RN0603/SMD

7 85 63 41 2

U1

NC/IDTQS3VH257TSSOP16/P0.65/SMD

IA02IB05IC011ID014

IA13IB16IC110ID113 GND 8

VCC 16

OE15 S1 YA 4YB 7YC 9YD 12

+ CE2220uF/16vC220UF16V/D6H11

+ CE1220uF/16vC220UF16V/D6H11

RN1

33x4 RN0603/SMD

7 85 63 41 2

P1S/PDIF OUTRCA/SPDIF/5P/DIP

G1 VCC2 IN3 K14

K25

66

G7

88

99

BO

TT

OM

HA1

HEADER 50 SMD0.5 BOTTOMH50S/P0.5

123456789

1011121314151617181920212223242526272829303132333435363738394041424344454647484950

L19 FB

L1 FBBEAD/SMD/1206

R14.7KR0603/SMD

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

GND

+5V

AV33

DV33

DV25DV12

+5V_TUNERDV33_DMDV18

+12V

DV25

AV33

+5V DV25

DV33 DV12

+5V DV33_DM

DV33_DMDV18

+5V_TUNER+12V

DV33

+5V DV33

+5V_TUNER+5V

+5V

GND1,3,4,5,6,7,8

+5V1,6

AV335,6

DV331,5,6,8

DV255,6,7DV125,6

+5V_TUNER3,4DV33_DM4DV184

+12V1

Title

Size Document Number Rev

Date: Sheet o f

MT5351RA-V2 1Custom

2 8Monday, September 26, 2005

POWER

TwinSon Chan

GLOBAL SIGNAL

POWER SUPPLY +2V5 FOR MT5351 AND DDR

1.25 x (1+0/100) = 1.25V

POWER SUPPLY +1V2 FOR MT5351

1.25 x (1+100/100) = 2.5V

POWER SUPPLY +3V3 FOR MT5351 (ANALOG)

1.25 x (1+180/110) = 3.3V


1.25 x (1+120/270) = 1.8V


POWER SUPPLY +5V FOR TUNER

1.25 x (1+180/110) = 3.3V


ADD

9V

Compatible With U6

CB15010uFC0805/SMD

CB50.1uFC0603/SMD

+ CE3220uF/16vC220UF16V/D6H11

R9270R0603/SMD

+ CE7220uF/16vC220UF16V/D6H11

+ CE13220uF/16vC220UF16V/D6H11

+ CE9220uF/16vC220UF16V/D6H11

R7110 R0603/SMD

+ CE30470uF/16v/NCC220UF16V/D6H11

R10100R0603/SMD

R5110 R0603/SMD

+ CE10220uF/16vC220UF16V/D6H11

U5

AZ1117/adjSOT223/SMD

ADJ/

GN

D1

OUT 2IN3

+ CE6220uF/16vC220UF16V/D6H11

L4

FBBEAD/SMD/0805

U4


ADJ/

GN

D1

OUT 2IN3

CB90.1uFC0603/SMD

U6


ADJ/

GN

D1

OUT 2IN3

U2


ADJ/

GN

D1

OUT 2IN3

+ CE16220uF/16vC220UF16V/D6H11

CB60.1uFC0603/SMD

CB1460.1uF/NCC0603/SMD

L33

FB

4.7UH

U21MP2105

IN4

GN

D2

EN1 SW 3FB 5

U3

AP1084/TO220-DIP/5VTO220/DIP

AD

J1

IN3 OUT 2

VOUT 4

L6

FBBEAD/SMD/0805

+ CE31470uF/16v/NCC220UF16V/D6H11

R140R0603/SMD

R11120R0603/SMD

+ CE5220uF/16vC220UF16V/D6H11

L17FB BEAD/SMD/0805/NC

L9

FBBEAD/SMD/0805

CB15110uFC0805/SMD

R6180 R0603/SMD

+ CE8220uF/16vC220UF16V/D6H11

L32

FBBEAD/SMD/1206/NC

+ CE12220uF/16vC220UF16V/D6H11

CB100.1uFC0603/SMD

R112499kR0603/SMD

+ CE14220uF/16vC220UF16V/D6H11

CB150.1uFC0603/SMD

+ CE4220uF/16vC220UF16V/D6H11

R8180 R0603/SMD

R12100R0603/SMD

CB1470.1uF/NCC0603/SMD

CB160.1uFC0603/SMD

CB30.1uFC0603/SMD

CB120.1uFC0603/SMD

CB70.1uFC0603/SMD

R113249kR0603/SMD

L8

FBBEAD/SMD/0805

L18

FB

BEAD/SMD/0805/nc

+ CE15220uF/16vC220UF16V/D6H11

CB40.1uFC0603/SMD

L7

FBBEAD/SMD/0805

L5

FBBEAD/SMD/0805

CB130.1uFC0603/SMD

R13100R0603/SMD

L3

FBBEAD/SMD/0805

CB80.1uFC0603/SMD

U7


ADJ/

GN

D1

OUT 2IN3

CB140.1uFC0603/SMD

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

GND

+5V_TUNER

RF_AGC

2nd_IF-

2nd_IF+

TUNER_SDAO

IF_AGC

RF_AGCIF_AGC

2nd_IF-2nd_IF+

TUNER_SCLO

TUNER_SCLOTUNER_SDAO

+5V_TUNER

+5V_TUNER

+5V_TUNER

+5V_TUNER

GND1,2,4,5,6,7,8

+5V_TUNER2,4

RF_AGC4IF_AGC4

2nd_IF-42nd_IF+4

TUNER_SCLO4TUNER_SDAO4

Title

Size Document Number R ev

Date: Sheet o f

MT5351RA-V2 1Custom


TUNER

TwinSon Chan

GLOBAL SIGNAL

TUNER INTERFACE

ROUTE SYMMETRICALLYIF SAW FILTER AND AMPLIFIER

R1510KR0603/SMD

R19 100 R0603/SMD

C61uFC0603/SMD

L10

FBBEAD/SMD/0805

CB180.1uFC0603/SMD

C71uFC0603/SMD

L12NSL/IND/SMD/0805

+ CE1810uF/16vC10UF16V/D5H11

R22510/1%R0603/SMD

R17 NS R0603/SMD

R21510/1%R0603/SMD

R18 100 R0603/SMD

R1610KR0603/SMD

U9

PORT SAW FILTER X6965D SIP5KSIP5K/DIP

IN+1IN-2

GND3

OUT+ 5OUT- 4

+ CE1710uF/16vC10UF16V/D5H11

U8

PORT TUNER TD1336/FGHP

GND TH1GND TH2

GND TH3GND TH4

Outdoor PS 1VS_splitter_+5V 2

OOB_OP 3NC 4

RF_AGC 5NC 6AS 7

SCL 8SDA 9

NC 10VS_Tuner_+5V 11

Broad_IF_OP 12IF_AGC 13

Narrow_IF_OP1 14Narrow_IF_OP2 15

C41nFC0603/SMD

C50.1uFC0603/SMD

R234.7KR0603/SMD

U10

upc3218TSSOP8/SMD

VCC_+5V1IN_12IN_23VAGC4 GND 5OUT_2 6OUT_1 7GND 8

CB170.1uFC0603/SMD

L11

FBBEAD/SMD/0805

R204.7KR0603/SMDC3

10nFC0603/SMD

C810nFC0603/SMD

A

A

B

B

C

C

D

D

E

E

4 4

3 3

2 2

1 1

DV18

GND

DV33_DM

RF_AGCIF_AGC

2nd_IF-2nd_IF+

TS1ERROR

TS1SYNCTS1VALID

TS1DATA[0..7]

OSCL_MSTOSDA_MST

TS1CLK

+5V_TUNER

TUNER_SDAO

TUNER_SCLO

TUNER_SDA1

TUNER_SCL1

ORESET#

TUNER_SCLOTUNER_SDAO

TS1DATA7

TS1DATA7

TS1DATA7_T

TS1SYNC

TS1CLK#

TS1CLK TS1CLK#

TS1DATA7_T TS1ERROR

DV

DD

33

DV

DD

18

DVDD33

XTAL2

ORESET#

TS1DATA0

TS1D

ATA6

AVDD33

DV

DD

18

AV

DD

33

VCMEXT

DVDD33

IF_AGCIF_AGCIF_AGC

TS1SYNC

ADVDD33_1

REFBOT

DV

DD

18

AV

DD

33

TS1D

ATA7

_T

DV

DD

33

DVDD18

TS1DATA2TS1DATA1

2nd_IF+

REFTOP

MT5

111_

IF_A

GC

DVDD33

TS1ERROR

OSDA_MST

AVDD33

AVDD33

TUN

ER

_SD

A

DVDD18

AVDD3

TS1D

ATA4

TS1VALID

AVDD33

TU

NE

R_S

CL

RF_AGCRF_AGCRF_AGC

AVDD33

DVDD18

MT5111_IF_AGC

XTAL1

DV

DD

18

DV

DD

33

AV

DD

5

TS1CLK

MT5

111_

RF_

AG

C

DV

DD

33

TS1DATA3

MT5111_RF_AGC

TS1CLK

TS1D

ATA5

2nd_IF-

AD

VD

D33

_2

IF_AGCIF_AGCIF_AGC

OSCL_MST

TUNER_SDA1

TUNER_SCL

TUNER_SDA

TUNER_SCL1

DVDD33

DV18

DV33_DM

AVDD33DV33_DM AVDD33

DVDD18 DVDD18AVDD33 AVDD3

AVDD33 AVDD5

AVDD33 ADVDD33_1

AVDD33 ADVDD33_2

DVDD33

DV33_DM

DV33_DM

DVDD18

DVDD33

DV33_DM+5V_TUNER

DV182

GND1,2,3,5,6,7,8

DV33_DM2

RF_AGC3IF_AGC3

2nd_IF-32nd_IF+3

TS1ERROR5

TS1SYNC5TS1VALID5

TS1DATA[0..7]5

OSDA_MST6OSCL_MST6

TS1CLK5

+5V_TUNER2,3

ORESET#1,5,8

TUNER_SCLO3TUNER_SDAO3

Title


Date: Sheet o f

MT5351RA-V2 1C


MT5111 ASIC

TwinSon Chan

GLOBAL SIGNAL

Digital 3.3V Bypass Caps

Analog 3.3V Bypass Caps

Digital 1.8V Bypass Caps

TUNER INTERFACE

TS INPUT

MODIFIED IN V3

Close to MT5111

SIF LEVEL SHIFTER

U20B

74HC00SOP14/SMD

4

56

147

R25

4.7

KR

0603

/SM

D/N

C

C1047nFC0603/SMD

U12B

74HC74SOP14/SMD

D12

CLK11 Q 9Q 8

VCC 14

PR

10

GND 7CL

13

CB260.1uFC0603/SMD

L13NS/220nHL/IND/SMD/0805

CB350.1uFC0603/SMD

CB250.1uFC0603/SMD

C15 0.1uFC0603/SMD

U20C

74HC00SOP14/SMD

9

108

147

R261KR0603/SMD

FB5

FBBEAD/SMD/0603

L15FB

BEAD/SMD/0805

CB410.1uFC0603/SMD

C180.1uFC0603/SMD

C1610uF/10vC0805/SMDC17 0.1uF

C0603/SMD

+ CE2010uF/16vC10UF16V/D5H11

CB340.1uFC0603/SMD

CB1480.1uFC0603/SMD

C2018pFC0603/SMD

CB380.1uFC0603/SMD

CB360.1uFC0603/SMD

R314.7KR0603/SMD

C131uFC0603/SMD

QF2

2N7002N-MOSFET2

13

RN12

33x4RN0603/SMD

1 23 45 67 8

CB320.1uFC0603/SMD

CB240.1uFC0603/SMD

C111uFC0603/SMD

CB230.1uFC0603/SMD

RN1333x4RN0603/SMD

12

34

56

78

U20D

74HC00SOP14/SMD

12

1311

147

R324.7KR0603/SMD

CB300.1uFC0603/SMD

R3410R0603/SMD

FB6

FBBEAD/SMD/0603

CB220.1uFC0603/SMD

CB1490.1uFC0603/SMD

QF1

2N7002N-MOSFET2

13

CB310.1uFC0603/SMD

CB830.1uFC0603/SMD

FB3

FBBEAD/SMD/0603

+ CE2110uF/16vC10UF16V/D5H11

C947nFC0603/SMD

CB390.1uFC0603/SMD

CB270.1uFC0603/SMD

CB190.1uFC0603/SMD

R2910KR0603/SMD

R27

4.7

KR

0603

/SM

D

C12NS/47pFC0603/SMD

FB2

FBBEAD/SMD/0603

C14 0.1uFC0603/SMD

CB210.1uFC0603/SMD

CB280.1uFC0603/SMD

L14FB

BEAD/SMD/0805CB200.1uFC0603/SMD

RN11

33x4RN0603/SMD

1 23 45 67 8

U20A

74HC00SOP14/SMD

1

23

147

R3010KR0603/SMD

R3310

R0603/SMD

U12A

74HC74SOP14/SMD

D2

CLK3 Q 5Q 6

VCC 14

PR

4

GND 7CL

1

MT5111AE

100-LQFP

U11MT5111AE

NC

1N

C2

AV

DD

3N

C4

NC

5N

C6

AV

SS

7N

C8

NC

9A

VD

D10

AV

SS

11A

VD

D12

NC

13N

C14

AD

VD

D33

15D

GN

D16

DV

DD

3317

DV

DD

1818

DG

ND

19N

C20

NC

21TS

_DA

TA7

22TS

_DA

TA6

23TS

_DA

TA5

24TS

_DA

TA4

25

DVDD33 26DGND 27TS_DATA3 28TS_DATA2 29DVDD18 30DGND 31TS_DATA1 32TS_DATA0 33TS_SYNC 34DVDD33 35DGND 36TS_CLK 37TS_VAL 38TS_ERR 39DVDD18 40DGND 41DVDD33 42DGND33 43HOST_DATA 44DVDD18 45DGND 46HOST_CLK 47RESET_ 48NC 49NC 50

DV

DD

1875

DG

ND

74R

F_A

GC

73IF

_AG

C72

DG

ND

71D

VD

D33

70TU

NE

R_C

LK69

TUN

ER

_DA

TA68

SA

167

SA

066

DG

ND

65D

VD

D18

64D

GN

D63

AN

TIF

62D

GN

D61

DV

DD

3360

NC

59N

C58

NC

57D

GN

D56

DV

DD

1855

NC

54N

C53

DV

DD

3352

DG

ND

51

AVSS100 AVDD99 AVSS98 XTAL197 XTAL296 AVSS95 AVSS94 AVDD93 AVDD92 AVDD91 AVDD1890 AVSS89 REFTOP88 VCMEXT87 REFBOT86 AVSS85 NC84 AVDD83 IN+82 IN-81 AVDD80 AVSS79 NC78 NC77 ADVDD3376

R241KR0603/SMD

L16FB

BEAD/SMD/0805

R111NS/0R0603/SMD

CB370.1uFC0603/SMD

CB330.1uFC0603/SMD

Y125MHz

CRYS/DIP/SMD

FB4

FBBEAD/SMD/0603

C1918pFC0603/SMD

CB290.1uFC0603/SMD

R281MR0603/SMD

CB400.1uFC0603/SMD

+ CE1910uF/16vC10UF16V/D5H11

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

JTRST#JTDIJTMSJTCKJRTCKJTDO

READY#

DV12

POWE#

POCE0#POOE0#

RDQ[0..31]RDQS[0..3]RDQM[0..3]RA[0..13]

RCLK0#RCS#RRAS#RCAS#RWE#RCKE

RBA[0..1]

RCLK1RCLK1#

RCLK0

PDA[0..22]PDD[0..7]

U2TXU2RX

U1RXU1TX

U0RXU0TX

AO1MCLKAO1LRCKAO1BCK

ASPDIF

OSCL0OSDA0

DV25DV33

RVREF

OXTALIOXTALO

DVDDKP

FS

CAPVPLL

RV

RE

F

CAPVGND

AVDDRKP

AVDD_APLL0AVDD_APLL1

AVDDBGKP

AVDD_DMPLL1AVDD_VPLL

AVDDYKP

AVDD_DMPLL0

APLLCAP1APLLCAP0

ATP1ATP2

OPWM0

REQUEST#ORESET#

VCXO0

TS1CLKTS1ERROR

TS1SYNCTS1VALID

TS1DATA[0..7]

VOR[0..7]VOG[0..7]VOB[0..7]VOPCLKVOHSYNCVOVSYNCVODE

AO1SDATA0

U2CTS

OIRI

AUD_CTRL

AV

DD

_VP

LL

RA

7

RA

2

RD

QM

0

JTDO

VOR7

GR TS1D

ATA0

PD

A1

AV

DD

YK

P

RC

LK1

RC

KE

RR

AS

#R

CA

S#

RD

Q13

VOB4

TS1E

RR

OR

PD

A18

PD

A14

PD

A2

RD

QM

3

RD

Q19

RA

13

RD

Q1

DONE

OIRI

VOPCLK

VOG7

VOB5

U2CTS

VCXO0

OP

WM

0

TS1D

ATA3

PD

A22

OXT

ALO

RD

Q30

RD

Q20

RB

A0

RD

Q10

RC

LK0

VOR0

VOG1

AO1BCK

U1RX

U0TX

OSCL0

TS1D

ATA7

TS1D

ATA4

PD

A9

AV

DD

_AP

LL1

RA

6

VOR6

PD

A0

AV

DD

BG

KP

RD

QM

2

RA

11

RD

Q6

JRTCK

VOB3

ASPDIF

OSDA0

PD

D3

TS1D

ATA1

PD

A17

AV

DD

_AP

LL0

RD

Q18

RA

12

RW

E#

RD

Q0

VOG6

PD

D0

TS1D

ATA2

PD

A21

RD

Q29

RD

Q25

RA

5

RD

Q9

VODE

VOG0

POCE0#

PD

D1

AP

LLC

AP

1

TS1D

ATA6

PD

A8

PD

A6

PD

A5

RD

Q26

RD

Q23

RD

Q16

RA

0

RC

S#

VOR5

AO1LRCK

U1TX

RA

9

RA

4

RA

1

RD

QS

1

RD

QS

0

RD

Q5

VOR1

VOB2

AO1SDATA0

PD

D2

AP

LLC

AP

0

FS

PD

A16 GND

RD

Q17

RD

Q15

JTCKJTMSJTDI

VOR2

VOG5

AO1MCLK

U2RX

VCXO1

PD

A20

CA

PV

GN

D

RD

Q28

RD

Q24

RD

Q8

RD

Q3

RC

LK0#

JTRST#

VOVSYNC

VOB7

TS1D

ATA5

PD

A7

PD

A4

DV

DD

KP

RA

10

RD

Q12

VOR4

VOG3

PD

D6

TS1V

ALI

D

PD

A13

AV

DD

_DM

PLL

1

OXT

ALI

ATP1

RC

LK1#

RA

8

RA

3

RD

QM

1

RD

Q7

RD

Q4

ORESET#

VOB1

POOE0#

POWE#

PD

D7

PD

D4

TS1C

LK

AV

DD

RK

P

AV

DD

_DM

PLL

0

RD

Q14

READY#REQUEST#

VOG4

CA

PV

PLL

B PD

A19

PD

A15

RD

Q27

RD

QS

3

RD

Q2

VOHSYNC

VOB6

AUD_CTRL

U2TX

U0RX

TS

1SY

NC

PD

A11

PD

A3

ATP2

RD

Q31

RD

QS

2

RD

Q21

RB

A1

RD

Q11

VOR3

VOG2

VOB0

TUNER_SW

PD

D5

PD

A12

PD

A10

RD

Q22

RBG

DV33

DV25

DV12

DV33

DV12

JTRST#8JTDI8JTMS8JTCK8JRTCK8JTDO8

GND1,2,3,4,6,7,8

DV122,6

POCE0#8POOE0#8POWE#8

RDQ[0..31]7RDQS[0..3]7RDQM[0..3]7RA[0..13]7

RCLK07RCLK0#7RCS#7RRAS#7RCAS#7RWE#7RCKE7

RBA[0..1]7

RCLK17RCLK1#7

PDA[0..22]8PDD[0..7]8

U2TX1,8U2RX1,8

U1RX8U1TX8

U0RX1,8U0TX1,8

READY#1

AO1MCLK1

AO1BCK1AO1LRCK1

AO1SDATA01

ASPDIF1

OPWM06

OSCL06OSDA06

DV252,6,7DV331,2,6,8

RVREF6

OXTALI6OXTALO6

DVDDKP6

FS6

CAPVPLL6CAPVGND6

AVDDRKP2,6

AVDD_APLL02,6AVDD_APLL12,6

AVDDBGKP2,6

AVDD_DMPLL12,6AVDD_VPLL2,6

AVDDYKP2,6

AVDD_DMPLL02,6

APLLCAP16APLLCAP06

ATP16ATP26

REQUEST#1ORESET#1,4,8

VCXO06

TS1CLK4TS1ERROR4

TS1SYNC4TS1VALID4

TS1DATA[0..7]4

VOR[0..7]1VOG[0..7]1VOB[0..7]1VOPCLK1VOHSYNC1,8VOVSYNC1,8VODE1

U2CTS6

OIRI6

AUD_CTRL1

R8B8G8

Title


Date: Sheet o f

MT5351RA-V2 1Custom5 8Monday, September 26, 2005

MT5351 ASIC

TwinSon Chan

JTAG PORT

GLOBAL SIGNAL

DDR MEMORY

FLASH INTERFACE

UART (RS232)

AUDIO INTERFACE

ANALOG PART

TEST PURPOSE

TS INPUT

DIGITAL VIDEO OUTPUT

Add by Ada

R36330R0603/SMD

TP6TUNER_SWTP/SMD/D1.0

C1180.1uFC0603/SMD

TP5IRTP/SMD/D1.0

TP2IOB_Y5TP/SMD/D1.0

MT5351

U14

MT5351BGA471/SMD

PD

CD

2#A

14P

DIO

IS16

#A

15

PD

A0

B24

PD

A1

A24

PD

A2

D23

PD

A3

C23

PD

A4

B23

PD

A5

A23

PD

A6

D22

PD

A7

C22

PD

A8

B22

PD

A9

A22

PD

A10

D21

PD

A11

C21

PD

A12

B21

PD

A13

A21

PD

A14

D20

PD

A15

C20

PD

A16

B20

PD

A17

A20

PD

A18

D19

PD

A19

C19

PD

A20

B19

PD

A21

A19

PD

A22

D18

PD

A23

C18

PD

A24

B18

PD

A25

A18

PD

CE

1#D

17P

DC

E2#

C17

PD

OE

#B

17P

DIO

RD

#A

17P

DIO

WR

#D

16P

DW

E#

C16

PD

IRE

Q#

B16

PD

RE

SE

TA

16P

DW

AIT

#D

15P

DIN

PA

CK

#C

15P

DR

EG

#B

15

PD

EN

PO

DB

14

T0C

LKC

14T0

SY

NC

D14

T0V

ALI

DA

13T0

DA

TA0

B13

T0D

ATA

1C

13T0

DA

TA2

D13

T0D

ATA

3A

12T0

DA

TA4

B12

T0D

ATA

5C

12T0

DA

TA6

D12

T0D

ATA

7A

11T1

CLK

B11

T1S

YN

CC

11T1

VA

LID

D11

T1D

ATA

0A

10T1

DA

TA1

B10

T1D

ATA

2C

10T1

DA

TA3

D10

T1D

ATA

4A

9T1

DA

TA5

B9

T1D

ATA

6C

9T1

DA

TA7

D9

OP

WM

0D

8

OR

TCV

DD

D7

OR

TCO

B8

OR

TCI

A8

OP

WM

1C

8

OR

TCV

SS

C7

FSA

6

CIN

_Y0

A7

IOR

_Y6

B3

IOB

_Y5

A3

IOG

_Y4

C4

IOX

_Y3

B4

IOY

_Y2

A4

IOC

_Y1

C5

CA

PV

PLL

D5

AP

LLC

AP

1D

4A

PLL

CA

P0

E4

AG

ND

L11

AG

ND

L12

AG

ND

L13

AG

ND

M11

AG

ND

M12

AG

ND

M13

AG

ND

N11

AG

ND

N12

AG

ND

N13

PD

D0

A27

PD

D1

B26

PD

D2

A26

PD

D3

C25

PD

D4

B25

PD

D5

A25

PD

D6

D24

PD

D7

C24

PD

CD

1#A

28

CV

DD

M5

CV

DD

N5

CV

DD

U5

CV

DD

E10

CV

DD

E19

CV

DD

M24

CV

DD

N24

CV

DD

U24

CV

DD

AE

14C

VD

DA

E15

IOVDDP5IOVDDR1IOVDDR2IOVDDR3IOVDDR4IOVDDR5IOVDDT5IOVDDE11IOVDDE12IOVDDE13IOVDDE14IOVDDE15IOVDDE16IOVDDE17IOVDDE18IOVDDP24IOVDDR24IOVDDR25IOVDDR26IOVDDR27IOVDDR28IOVDDT24

POWE# B27POCE0# B28POOE0# C26POCE1# C27POOE1# C28POCE2# D25POOE2# D26

OSDA0E1OSCL0F4OSDA1E3OSCL1E2

U0TXF3U0RXF2U1TXF1U1RXG4U2TXG3U2RXG2U2CTSG1U2RTSH4

AO1SDATA3H3AO1SDATA2H2AO1SDATA1H1AO1SDATA0J4AO1LRCKJ3AO1BCKJ2AO1MCLKJ1AO2SDATA0K1AO2LRCKK2AO2BCKK3AO2MCLKK4ASPDIFL3ASPDIF2L4

VOB0L2VOB1L1VOB2M4VOB3M3VOB4M2VOB5M1VOB6N4VOB7N3VOG0N2VOG1N1VOG2P4VOG3P3VOG4P2VOG5P1VOG6T1VOG7T2VOR0T3VOR1T4VOR2U1VOR3U2VOR4U3VOR5U4VOR6V1VOR7V2VOPCLKV3VOHSYNCV4VOVSYNCW1VODEW2

JTRST#W3JTDIW4JTMSY1JTCKY2JRTCKY3JTDOY4

GNDL14GNDL15GNDL16GNDL17GNDL18GNDM14GNDM15GNDM16GNDM17GNDM18GNDN14GNDN15GNDN16GNDN17GNDN18GNDP11GNDP12GNDP13GNDP14GNDP15GNDP16GNDP17GNDP18GNDR11GNDR12GNDR13GNDR14GNDR15GNDR16GNDR17GNDR18

PARB# D27PARE# D28PACE# E25PACLE E26PAALE E27

PAWE# E28

ELREQ F25ECLK F26

ECNTL0 F27ECNTL1 F28EDATA0 G25EDATA1 G26EDATA2 G27EDATA3 G28EDATA4 H25EDATA5 H26EDATA6 H27EDATA7 H28

ELPS J25ELINKON J26

ORESET# J27OIRI J28

OIRO K25

ICS1# K26ICS0# K27IDA2 K28IDA0 L25IDA1 L26

IINTRQ L27IDMACK# L28

IIORDY M25IDIOR# M26IDIOW# M27

IDMARQ M28IDD15 N25IDD0 N26

IDD14 N27IDD1 N28

IDD13 P25IDD2 P26

IDD12 P27IDD3 P28

IDD11 T28IDD4 T27

IDD10 T26IDD5 T25IDD9 U28IDD6 U27IDD8 U26IDD7 U25

IRESET# V28

DDETECT V27DCLK V26

DCMD V25DDATA0 W28DDATA1 W27DDATA2 W26DDATA3 W25

MDETECT Y28MCLK Y27

MBS Y26MDATA0 Y25MDATA1 AA28MDATA2 AA27MDATA3 AA26

STSCLK AA25STSDOUT AB28

STSDIN AB27SPWRSEL AB26SDETECT AB25

SCMDVCC AC28SRST AC27SCLK AC26

SDATA AC25

GND T11GND T12GND T13GND T14GND T15GND T16GND T17GND T18GND U11GND U12GND U13GND U14GND U15GND U16GND U17GND U18GND V11GND V12GND V13GND V14GND V15GND V16GND V17GND V18

DV

RE

F2A

E8

DV

RE

F0A

E9

DV

RE

F1A

E20

DV

RE

F3A

E21

RD

Q32

AA

1R

DQ

33A

A2

RD

Q34

AA

3R

DQ

35A

B1

RD

Q36

AB

2R

DQ

37A

B3

RD

Q38

AC

1R

DQ

39A

C2

RD

QS

4A

C3

RD

QM

4A

D1

RD

QM

5A

D2

RD

QS

5A

D3

RD

Q40

AE

1R

DQ

41A

E2

RD

Q42

AE

3R

DQ

43A

F1R

DQ

44A

F2R

DQ

45A

F3R

DQ

46A

G1

RD

Q47

AG

2R

CLK

0A

H1

RC

LK0#

AH

2R

DQ

0A

H3

RD

Q1

AG

3R

DQ

2A

H4

RD

Q3

AG

4R

DQ

4A

F4R

DQ

5A

H5

RD

Q6

AG

5R

DQ

7A

F5R

DQ

S0

AH

6R

DQ

M0

AG

6R

DQ

M1

AF6

RD

QS

1A

H7

RD

Q8

AG

7R

DQ

9A

F7R

DQ

10A

H8

RD

Q11

AG

8R

DQ

12A

F8R

DQ

13A

H9

RD

Q14

AG

9R

DQ

15A

F9R

WE

#A

H10

RC

AS

#A

G10

RR

AS

#A

F10

RC

S#

AH

11R

BA

0A

G11

RB

A1

AF1

1R

A10

AH

12R

A0

AG

12R

A1

AF1

2R

A2

AH

13R

A3

AG

13R

A4

AF1

3R

A5

AH

14R

A6

AG

14R

A7

AF1

4R

A8

AH

15R

A9

AG

15R

A11

AF1

5R

A12

AH

16R

A13

AG

16R

CK

EA

F16

RD

Q16

AH

17R

DQ

17A

G17

RD

Q18

AF1

7R

DQ

19A

H18

RD

Q20

AG

18R

DQ

21A

F18

RD

Q22

AH

19R

DQ

23A

G19

RD

QS

2A

F19

RD

QM

2A

H20

RD

QM

3A

G20

RD

QS

3A

F20

RD

Q24

AH

21R

DQ

25A

G21

RD

Q26

AF2

1R

DQ

27A

H22

RD

Q28

AG

22R

DQ

29A

F22

RD

Q30

AH

23R

DQ

31A

G23

RC

LK1

AF2

3R

CLK

1#A

H24

RD

Q48

AG

24R

DQ

49A

F24

RD

Q50

AH

25R

DQ

51A

G25

RD

Q52

AF2

5R

DQ

53A

H26

RD

Q54

AG

26R

DQ

55A

H27

RD

QS

6A

H28

RD

QM

6A

G28

RD

QM

7A

G27

RD

QS

7A

F28

RD

Q56

AF2

7R

DQ

57A

F26

RD

Q58

AE

28R

DQ

59A

E27

RD

Q60

AE

26R

DQ

61A

D28

RD

Q62

AD

27R

DQ

63A

D26

RV

DD

AA

4R

VD

DA

B4

RV

DD

AC

4R

VD

DA

D4

RV

DD

AE

4R

VD

DA

E5

RV

DD

AE

6R

VD

DA

E7

RV

DD

AE

10R

VD

DA

E11

RV

DD

AE

12R

VD

DA

E13

RV

DD

AE

16R

VD

DA

E17

RV

DD

AE

18R

VD

DA

E19

RV

DD

AE

22R

VD

DA

E23

RV

DD

AE

24R

VD

DA

E25

RV

DD

AD

25

ATP

1D

2A

VD

D_A

PLL

0C

2A

VD

D_A

PLL

1B

1A

VD

D_V

PLL

A1

AV

DD

_DM

PLL

0C

1

AV

DD

RK

PC

3

AV

DD

YK

PB

5A

VD

DB

GK

PB

6

DA

CV

RE

FB

7

DV

DD

KP

C6

OX

TALO

A2

OX

TALI

B2

NC

A5

NC

D6

AV

DD

_DM

PLL

1D

3

ATP

2D

1

CA

PV

GN

DE

5

+ CE2247uF/16vC10UF16V/D5H11

TP4VCXO1TP/SMD/D1.0

TP3IOG_Y4TP/SMD/D1.0

R354.7KR0603/SMD

LED1LED DIP2.54LED/DIP/P2.54

C1160.1uFC0603/SMD

TP1IOR_Y6TP/SMD/D1.0

C1170.1uFC0603/SMD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

RVREF

GND

OXTALIOXTALO

OPWM0

OXTALO

OXTALI

MEM_VREF

FS

APLLCAP1 APLLCAP0

DV25

DV33

DV12

AVDDBGKP

AVDDYKP

AVDDRKP

AVDD_DMPLL0

AVDD_DMPLL1

AVDD_VPLL

AVDD_APLL1

AVDD_APLL0

MEM_VREF RVREF

CAPVPLLAV33

DVDDKP

FS

CAPVPLL

APLLCAP1APLLCAP0

ATP1ATP2

AVDDRKP

AVDD_APLL0AVDD_APLL1

AVDDBGKP

AVDD_DMPLL1AVDD_VPLL

AVDDYKP

AVDD_DMPLL0

CAPVGND

ATP1 ATP2

OSCL_MST

OSDA_MSTOSDA0

OSCL0

OSCL_MSTOSDA_MST

OPWM0

OSCL_MSTOSDA_MST

OSCL0OSDA0

VCXO0

VCXO0

CAPVGND

OXTALIU2CTS

U2CTS

O IRI

O IRI

+5V

DV25

DV12

DV33

DV33

DVDDKPAV33

AV33 AV33

DV12

DV33

DV33

DV33

+5V

GND1,2,3,4,5,7,8

DV252,5,7

RVREF5

OXTALI5OXTALO5

OPWM05

MEM_VREF7

DV331,2,5,8

DV122,5

AV332,5

DVDDKP5

FS5

CAPVPLL5

APLLCAP15APLLCAP05

ATP15ATP25

AVDDRKP2,5

AVDD_APLL02,5AVDD_APLL12,5

AVDDBGKP2,5

AVDD_DMPLL12,5AVDD_VPLL2,5

AVDDYKP2,5

AVDD_DMPLL02,5

CAPVGND5

OSDA_MST4OSCL_MST4

OSCL05OSDA05

VCXO05

U2CTS5

OIRI5

+5V1,2

Title


Date: Sheet o f

MT5351RA-V2 1Custom


MT5351 PERIPHERAL

TwinSon Chan

GLOBAL SIGNAL

LEFT SIDE BOTTOM SIDE

LEFT SIDE RIGHT SIDE

LEFT SIDE RIGHT SIDE TOP SIDE

TOP SIDE BOTTOM SIDE

ANALOG PART

MT5351 SYSTEM EEPROM

CB760.1uFC0603/SMD

R454.7KR0603/SMD

CB880.1uFC0603/SMD

C1400.1uFC0603/SMD

C22NS/20pFC0603/SMD

C3110uF/10vC0805/SMD

C1830.1uFC0603/SMD

C1850.1uFC0603/SMD

CB444.7uFC0603/SMD

CB504.7uFC0603/SMD

CB720.1uFC0603/SMD

R44NS/10R0603/SMD

CB750.1uFC0603/SMD

C2910uF/10vC0805/SMD

C1040.1uFC0603/SMD

X1

VCXO FR270003OSC/6P/SMD/7X5

CVIN1

TRI-STATE2

GND3 OUT 4

NC 5

VDD 6

C1840.1uFC0603/SMD

JP1

JP2/DIP/P2.542x1

1 2

R38NS/10MR0603/SMD

C1280.1uFC0603/SMD

CB670.1uFC0603/SMD

CB574.7uFC0603/SMD

R40NS/50R0603/SMD

CB710.1uFC0603/SMD

R39NS/10R0603/SMD

C251500pFC0603/SMD

IR1

IRNS/IR

1 2 3

CB740.1uFC0603/SMD

R4310R0603/SMD

C1290.1uFC0603/SMD

R47100R0603/SMD

OSC1NS/74.25MHzOSC/SMD/A

VCC4 OUT 3

GND 2NC1

FB7

FBBEAD/SMD/0603

CB660.1uFC0603/SMD

CB770.1uFC0603/SMD

CB850.1uFC0603/SMD

R464.7KR0603/SMD

CB900.1uFC0603/SMD

CB870.1uFC0603/SMD

CB700.1uFC0603/SMD

R41NS/50R0603/SMD

Y2

NS/27MHzCRYS/DIP/SMD

CB530.1uFC0603/SMD

C10110uF/10vC0805/SMD

C1384.7uFC0603/SMD

C2610nFC0603/SMD

CB480.1uFC0603/SMD

CB520.1uFC0603/SMD

U13

EEPROM 24C16SOP8/SMD/NC


R48100R0603/SMD

R428.2KR0603/SMD

R37NS/560R0603/SMD

C2847pFC0603/SMD

CB540.1uFC0603/SMD

CB690.1uFC0603/SMD

CB810.1uFC0603/SMD

CB890.1uFC0603/SMD

C241500pFC0603/SMD

CB450.1uFC0603/SMD

C1860.1uFC0603/SMD

CB420.1uFC0603/SMD

TP7CAPVGNDTP/SMD/D1.0

CB784.7uFC0603/SMD

CB820.1uFC0603/SMD

CB510.1uFC0603/SMD

CB790.1uFC0603/SMD

CB650.1uFC0603/SMD

CB680.1uFC0603/SMD

C271nFC0603/SMD

C1790.1uFC0603/SMD

CB490.1uFC0603/SMD

CB860.1uFC0603/SMD

C21NS/20pFC0603/SMD

CB460.1uFC0603/SMD

CB474.7uFC0603/SMD

CB730.1uFC0603/SMD

CB430.1uFC0603/SMD

CB800.1uFC0603/SMD

C23

5600pFC0603/SMD

L31

FBL0603/SMD

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DV25

GND

MEM_VREFMEM_ADDR6MEM_ADDR5MEM_ADDR4

MEM_DQ0

MEM_ADDR6MEM_ADDR5MEM_ADDR4

MEM_DQ16 MEM_DQ31

MEM_DQ17 MEM_DQ30MEM_DQ18

MEM_DQ19MEM_DQ20

MEM_DQ21MEM_DQ22

MEM_DQ23

MEM_DQS2

MEM_WE#MEM_DQM2

MEM_CAS#

MEM_CS#MEM_RAS#

MEM_BA0MEM_BA1MEM_ADDR10MEM_ADDR0MEM_ADDR1MEM_ADDR2MEM_ADDR3

MEM_DQ29

MEM_DQ28MEM_DQ27

MEM_DQ26MEM_DQ25

MEM_DQ24

MEM_DQS3

MEM_DQM3MEM_CLKB#MEM_CLKBMEM_CLKEN

MEM_ADDR12MEM_ADDR11MEM_ADDR9MEM_ADDR8MEM_ADDR7

MEM_DQ15

MEM_DQ1 MEM_DQ14MEM_DQ2

MEM_DQ3MEM_DQ4

MEM_DQ5MEM_DQ6

MEM_DQ7

MEM_DQS0

MEM_WE#MEM_DQM0

MEM_CAS#

MEM_CS#MEM_RAS#

MEM_BA0MEM_BA1MEM_ADDR10MEM_ADDR0MEM_ADDR1MEM_ADDR2MEM_ADDR3

MEM_DQ13

MEM_DQ12MEM_DQ11

MEM_DQ10MEM_DQ9

MEM_DQ8

MEM_DQS1

MEM_DQM1MEM_CLKA#MEM_CLKAMEM_CLKEN

MEM_ADDR12MEM_ADDR11MEM_ADDR9MEM_ADDR8MEM_ADDR7

MEM_DQ6

MEM_DQ14

MEM_DQ23

MEM_DQ12

MEM_DQ17

MEM_DQ1

MEM_DQ20

MEM_DQ22

MEM_DQ26

MEM_DQ3MEM_DQ4

MEM_DQ29

MEM_DQ0

MEM_DQ28

MEM_DQ19

MEM_DQ31

MEM_DQ13

MEM_DQ25

MEM_DQ21

MEM_DQ11

MEM_DQ8

MEM_DQ10MEM_DQ9

MEM_DQ2

MEM_DQ5

MEM_DQ24

MEM_DQ18

MEM_DQ7

MEM_DQ15

MEM_DQ30

MEM_DQ27

MEM_DQ16

RDQ[0..31]RDQS[0..3]RDQM[0..3]RA[0..13]

RCLK0RCLK0#RCS#RRAS#RCAS#RWE#RCKE

RBA[0..1]

RCLK1RCLK1#

MEM_DQS0MEM_DQM0MEM_DQM1MEM_DQS1

MEM_DQS2MEM_DQM2MEM_DQM3MEM_DQS3

RDQM1RDQS1

RDQS0RDQM0

RDQ0RDQ1RDQ2RDQ3RDQ4RDQ5

RDQ7

RDQS2RDQM2RDQM3RDQS3

RDQ8RDQ9RDQ10RDQ11RDQ12

RDQ14

RDQ17RDQ18RDQ19RDQ20RDQ21RDQ22RDQ23

RDQ16

RDQ15

RDQ24RDQ25RDQ26RDQ27RDQ28RDQ29RDQ30RDQ31

MEM_CLKA

MEM_CLKA#

RCLK0

RCLK0#

MEM_CLKB

MEM_CLKB#

RCLK1

RCLK1#

MEM_VREF

MEM_VREFMEM_VREFMEM_ADDR13 MEM_ADDR13

DV25

RA0 MEM_ADDR0

MEM_ADDR8

MEM_ADDR7

MEM_ADDR2

MEM_ADDR4

MEM_ADDR5

RA1

RA2

MEM_ADDR1

MEM_ADDR3

MEM_ADDR6

RA3

RA4

RA5RA6

RA7

RA13 MEM_ADDR13

MEM_ADDR9RA9

MEM_ADDR12

RA11

RCKE

MEM_ADDR10

RA12

MEM_ADDR11

MEM_CLKEN

MEM_CAS#MEM_CS#MEM_BA0

MEM_WE#

MEM_RAS#

RWE#RCAS#

RRAS#MEM_BA1

RCS#RBA0

RBA1

RA10MEM_ADDR0

MEM_ADDR12

MEM_ADDR10

MEM_ADDR11

MEM_CLKEN

MEM_ADDR2MEM_ADDR1

MEM_ADDR13

MEM_CS#

MEM_ADDR7

MEM_ADDR3

MEM_CAS#

MEM_ADDR4

MEM_WE#

MEM_ADDR5

MEM_ADDR9

MEM_ADDR6

MEM_ADDR8

MEM_BA1MEM_BA0

MEM_RAS#

RA8

RDQ6

RDQ13

DV25 DV25 DV25 DV25

DV25

DV25

+1V25_DDR

+1V25_DDR

+1V25_DDR+1V25_DDR

+1V25_DDR

DV25

+1V25_DDR

+1V25_DDR

GND1,2,3,4,5,6,8

DV252,5,6

MEM_VREF6

RDQ[0..31]5RDQS[0..3]5RDQM[0..3]5RA[0..13]5

RCLK05RCLK0#5RCS#5RRAS#5RCAS#5RWE#5RCKE5

RBA[0..1]5

RCLK15RCLK1#5

Title


Date: Sheet o f

MT5351RA-V2 1Custom


DDR MEMORY

TwinSon Chan

GLOBAL SIGNAL

EQUAL LINE LENGTH

BYPASS CAP. FOR DDR

BYPASS CAP. FOR TERMINATOR(EVERY 2 RESISTOR PUT 1 BYPASS CAP.)

DDR MEMORY

DDR#1 DDR#2

BYPASS CAP. FOR DIMM+1V25_DDR FOR DDR TERMINATORMEM_VREF FOR DDR AND MT5351 VREF

FOR DDR#1

FOR DDR#2

CLOSED TO MT5351 CLOSED TO DDR

CLOSED TO MT5351

CLOSED TO MT5351 CLOSED TO DDR

CLOSED TO DDR

ADD by Ada

R73 47

C1740.1uFC0603/SMD

R72 75

C1600.1uFC0603/SMD

C1410.1uFC0603/SMD

R80 75

C1440.1uFC0603/SMD

R10247R0603/SMD

R57 47R56 75

C1590.1uFC0603/SMD

RN20 47x4

1 23 45 67 8

R69 47

C1700.1uFC0603/SMD

RN14 22x4

1 23 45 67 8

R76 75

C1090.1uFC0603/SMD

R107100R0603/SMD

U18

16M x 16 DDR TSOP-66TSOP_0D65_22D6LX9D7W_66SP

VDD1DQ02VDDQ3DQ14DQ25VSSQ6DQ37DQ48VDDQ9DQ510DQ611VSSQ12DQ713NC14VDDQ15LDQS16NC17VDD18NC19LDM20WE21CAS22RAS23CS24NC25BS026BS127A10/AP28A029A130A231A332VDD33 VSS 34A4 35A5 36A6 37A7 38A8 39A9 40A11 41A12 42NC 43CKE 44CLK 45CLK 46UDM 47VSS 48VREF 49NC 50UDQS 51VSSQ 52NC 53DQ8 54VDDQ 55DQ9 56DQ10 57VSSQ 58DQ11 59DQ12 60VDDQ 61DQ13 62DQ14 63VSSQ 64DQ15 65VSS 66

C1610.1uFC0603/SMD

RN22 22x4

1 23 45 67 8

C1770.1uFC0603/SMD

RN32 47x4

1 23 45 67 8

R55 47

C1460.1uFC0603/SMD

U19

IC LP2996 DDR Termination SOP-8SOP8/SMD

GND1SD2VSENSE3VREF4 VDDQ 5AVIN 6PVIN 7VTT 8

C1800.1uFC0603/SMD

C1100.1uFC0603/SMD

U15

16M x 16 DDR TSOP-66TSOP_0D65_22D6LX9D7W_66SP

VDD1DQ02VDDQ3DQ14DQ25VSSQ6DQ37DQ48VDDQ9DQ510DQ611VSSQ12DQ713NC14VDDQ15LDQS16NC17VDD18NC19LDM20WE21CAS22RAS23CS24NC25BS026BS127A10/AP28A029A130A231A332VDD33 VSS 34A4 35A5 36A6 37A7 38A8 39A9 40A11 41A12 42NC 43CKE 44CLK 45CLK 46UDM 47VSS 48VREF 49NC 50UDQS 51VSSQ 52NC 53DQ8 54VDDQ 55DQ9 56DQ10 57VSSQ 58DQ11 59DQ12 60VDDQ 61DQ13 62DQ14 63VSSQ 64DQ15 65VSS 66

RN28 47x4

1 23 45 67 8

CB1330.1uFC0603/SMD

R74 75

+ CE29220uF/16vC220UF16V/D6H11

R67 22

C1620.1uFC0603/SMD

R103100R0603/SMD

CB950.1uFC0603/SMD

RN26 47x4

1 23 45 67 8

C1030.1uFC0603/SMD

C1470.1uFC0603/SMD

C1560.1uFC0603/SMD

+ CE2447uF/16v C47UF16V/D5H5

C1730.1uFC0603/SMD

RN19 75x4

1 23 45 67 8

R70 75

C1520.1uFC0603/SMD

C1670.1uFC0603/SMD

+ CE26220uF/16vC220UF16V/D6H11

C1420.1uFC0603/SMD

RN36 47x4

1 23 45 67 8

RN15 75x4

1 23 45 67 8

C1680.1uFC0603/SMD

R71 22

R63 22

+ CE28220uF/16vC220UF16V/D6H11

C1630.1uFC0603/SMD

C1110.1uFC0603/SMD

R10847R0603/SMD

RN17 75x4

1 23 45 67 8

RN29 75x4

1 23 45 67 8

C1760.1uFC0603/SMD

C1480.1uFC0603/SMD

R78 NS/75

RN25 75x4

1 23 45 67 8

R1044.7KR0603/SMD

R64 75

CB1260.1uFC0603/SMD

C1060.1uFC0603/SMD

C1540.1uFC0603/SMD

R77 22

R68 75

+ CE25220uF/16vC220UF16V/D6H11

R65 22

RN35 75x4

1 23 45 67 8

C1570.1uFC0603/SMD

C1820.1uFC0603/SMD

C1640.1uFC0603/SMD

R79 47

C1020.1uFC0603/SMD

C1450.1uFC0603/SMD

R62 75

C1050.1uFC0603/SMD

C1750.1uFC0603/SMD

R10647R0603/SMD

C1500.1uFC0603/SMD

C1070.1uFC0603/SMD

R61 47

+ CE23220uF/16vC220UF16V/D6H11

RN33 75x4

1 23 45 67 8

RN31 75x41 23 45 67 8

C1810.1uFC0603/SMD C155

0.1uFC0603/SMD

C1430.1uFC0603/SMD C172

0.1uFC0603/SMD

RN34 47x4

1 23 45 67 8

C1580.1uFC0603/SMD

C1650.1uFC0603/SMD

R60 75

RN24 47x4

1 23 45 67 8

R75 47

C1390.1uFC0603/SMD

C1710.1uFC0603/SMD

C1510.1uFC0603/SMD

CB910.1uFC0603/SMD

R59 47

CB1250.1uFC0603/SMD

C1530.1uFC0603/SMD

C1080.1uFC0603/SMD

RN18 22x4

1 23 45 67 8

RN16 47x4

1 23 45 67 8

R10547R0603/SMD

C1780.1uFC0603/SMD

RN27 75x4

1 23 45 67 8

RN23 75x4

1 23 45 67 8

RN37 75x4

1 23 45 67 8

C1690.1uFC0603/SMD

R58 75

R66 75

RN30 22x41 23 45 67 8

C1660.1uFC0603/SMD

RN21 75x4

1 23 45 67 8

5

5

4

4

3

3

2

2

1

1

D D

C C

B B

A A

DV33

ORESET#

PDA0

PDA20PDA19PDA18PDA17PDA16PDA15PDA14PDA13PDA12

PDA10PDA11

PDA9PDA8PDA7PDA6PDA5PDA4PDA3PDA2PDA1

PDA21PDA22POCE0#POOE0#POWE#

NOR_RST#

PDD0PDD1PDD2PDD3PDD4PDD5PDD6PDD7

NOR_WP#

ORESET#

ORESET#

NOR_RY_BY0#PDA[0..22]PDD[0..7]

POWE#

POCE0#POOE0#

GND

U0TXU0RX

U1TXU1RX

JTRST#JTDIJTMSJTCKJRTCKJTDO

U2TXU2RX

U1RXU1TX

U0RXU0TX

JRTCKJTDO

JTAG_DBGACKJTAG_DBGRQ

JTMS

JTRST#JTDI

JTCK

TVTREF#1

+5V

U2TXU2RX

PDA1 PDA2PDA0

RBG

G

VOHSYNCVOVSYNC

VOHSYNCVOVSYNC

R

B

DV33

DV33

DV33

DV33

DV33

DV33

DV33DV33

GND1,2,3,4,5,6,7

DV331,2,5,6

ORESET#1,4,5

PDA[0..22]5PDD[0..7]5

POCE0#5POOE0#5POWE#5

JTRST#5JTDI5JTMS5JTCK5JRTCK5JTDO5

U2TX1,5U2RX1,5

U1RX5U1TX5

U0RX1,5U0TX1,5

+5V1,2,6

R5B5G5VOHSYNC1,5VOVSYNC1,5

Title


Date: Sheet o f

MT5351RA-V2 1Custom


NOR FLASH / JTAG / UART

TwinSon Chan

GLOBAL SIGNAL

FLASH INTERFACE

NOR FLASH #0JTAG PORT

UART (RS232)

FOR SOFTWARE LINK

CLI OUTPUT

SOFTWARE DEBUG PORT

TRAP CIRCUIT

ADD

R85NS/4.7KR0603/SMD

C32NS/10pFC0603/SMD

J3

10x2DIP10X2/W/H/IDE/P2.54

13579

1113151719

2468101214161820

R97 0 R0603/SMD

R984.7KR0603/SMD

R83NS/4.7KR0603/SMD

R894.7KR0603/SMD

R84

0R0603/SMD

J6

CON8

12345678

RN381Kx4RN0603/SMD

12

34

56

78

R954.7KR0603/SMD

R934.7KR0603/SMD

+ CE2710uF/16vC10UF16V/D5H11

J5


1234

R924.7KR0603/SMD

U17

IC FLASH MX29LV320 32Mb TSOP-48TSOP48/SMD

A025A124A223A322A421A520A619A718A88

A2010

OE28

BYTE 47A1816

D0 29D1 31D2 33D3 35

A97

CE26

D4 38D5 40D6 42D7 44D8 30D9 32

WP/ACC 14

D11 36D12 39D13 41D14 43

D15/A-1 45

VCC 37

GND1 27WE11

A199

D10 34

GND2 46

A106

A124 A115

A133A142A151A1648A1717

A2113

RESET12

RY/BY 15

R1014.7KR0603/SMD

R96 0 R0603/SMD

R944.7KR0603/SMD

CB1450.1uFC0603/SMD

R994.7KR0603/SMD

R1004.7KR0603/SMD

J4


1234

R874.7KR0603/SMD

R911KR0603/SMD

R82NS/4.7KR0603/SMD

R88

0R0603/SMD

R86

NS/4.7KR0603/SMD

C3310pFC0603/SMD

R904.7KR0603/SMD J2


1234

FB9

FBBEAD/SMD/0603

Basic Operations & Circuit Description

MODULE There are 1 pcs panel and 8 pcs PCB including 2 pcs Y/Z Sustainer board, 2 pcs Y Driveboard, 2 pcs X (left and right) Extension PCB, 1 pcs Control (Signal Input) and 1 pcs Powerboard in the Module.

SET There are 6 pcs PCBs including 1 pcs Tuner/Audio board, 1 pcs Keypad board, 1 pcsRemote Control Receiver board, 1 pcs L/R Speakers and 1 pcs Main (Video) board, 1 pcs ATSC 1 pcs ATSC board in the SET.

Internal Speaker (Right) Power Supply Internal Speaker (Left)

Local Keyremote controlreceiver

Main

Tuner/Audio X Right Extension

Control (Signal Input)

EMI Filter + AC Inlet

Power SW

External Speaker Terminal

Z-Sustainer

X Left Extension

Y-Drive Bottom

Y-Sustainer

Y-Drive Top

ATSC

Parts position

PCB function1. Power:

(1). Input voltage: AC 110V~240V, 47Hz~63Hz.Input range: AC 90V(Min)~265V(Max) auto regulation.

(2). To provide power for PCBs.2. Main board: To converter TV signals, S signals, AV signals, Y Pb/

Cb Pr/Cr signals, DVI signals and D-SUB signals to digital ones and to transmit toControl board.

3. Control board: Dealing with the digital signal for output to panel.4. Y-Sustainer / Z-Sustainer board:

(1). Receiving the signals from Control and high voltage supply.(2). Output scanning waveform for Module.

5. Y-Drive board: Receive signal from Y sustainer, output horizontal scanning wave-form to the panel.

6. X (left and right) extension board: Output addressing signals.7. Tuner/Audio Board: : : : : Amplifying the audio signal to the internal or external speakers

of which selected.To convert TV RF signal to video and SIF audio signal to Main board.

8. ATSC Board: Receiver and converter ATSC TV signal to transmit to main board.

PCB failure analysis

1. CONTROL: a. Abnormal noise on screen. b. No picture.2. MAIN : a. Lacking color, Bad color scale.

b. No voice.c. No picture but with signals output, OSD and back light.d. Abnormal noise on screen.

3. POWER: No picture, no power output.4. Z - Sustainer:a. No picture.

b. Color not enough.c. Flash on screen.

5. Y - Sustainer: Darker picture with signals.

6. Tuner/Audio : a. No voice. (Make sure status: Mute / Internal, External speaker) b. Noise c. No ATV signals 7. Y/Z - Sustainer: The component working temperature is about 55oC.

If the temperature rises abnormal, this may be a error point.

8. ATSC: a. No ATSC TV signal

Basic operation of Plasma Display

1. After turning on power switch, power board sends 5Vst-by Volt to MainIC MT8205 waiting for ON signals from Key Switch or Remote Receiver.

2. When the ON signal from Key Switch or Remote Receiver is detected, MT8205 will send ON Control signals to Power. Then Power sends (5Vsc, 9Vsc, 12Vsc, 24V and RLYON, Vs ON) to PCBs working. This time VIF will send signals to display back light,OSD on the panel and start to search available signal sources. If the audio signalsinput, them will be amplified by Audio AMP and transmitted to Speakers.

3. If some abnormal signals are detected (for example: over volts, over current, overtemperature and under volts), the system will be shut down by Power off.

Main IC Specifications

- MT8205 - SiI169 - M13S128168A - MP7720

MT8205/8203Specifications are subject to change without notice Application Notes

Page 1 October, 2004

History 2004/09/12 Runma Chen for customer design-in V1.02004/09/30 Dragon Chen Add feature list V1.12004/09/30 Runma Chen Modify for PIP/POP 444 support V1.22004/10/01 Runma Chen PIP/POP hardware limitation-I V1.32004/10/18 Dragon Chen &

Wen Hsu PIP/POP hardware limitation-II & video front end component V1.4

2004/10/20 Dragon Chen Update functional block V1.52004/10/21 Dragon Chen Correct function block fault to V1.4 V1.62004/11/04 Dragon Chen 1. Delete power spec. (About power spec, please reference another document)

2. Add AC & DC characteristics 3. Add pin description 4. Add audio out mapping rule

V1.7

2004/11/05 Dragon Chen Descript more detail for pin power initial state & remove some description to another document (MT8205 product brief)

V1.8

MT8205/8203Specifications are subject to change without notice Application Notes

Page 2 October, 2004

MT8205/8203 Application Notes

MT8205/8203 is a highly integrated single chip for LCD TV supporting video input and output format up to HDTV. It includes 3D comb filter TV Decoder to retrieve the best image from popular composite signals. On-chip advanced motion adaptive de-interlacer converts accordingly the interlace video into progressive one with overlay of a 2D Graphic processor. Optional 2nd HDTV or SDTV inputs allows user to see multi-programs on same screen. Flexible scalar provides wide adoption to various LCD panel for different video sources. Its on-chip audio processor decodes analog signals from Tuner with lip sync control, delivering high quality post-processed sound effect to customers. On-chip microprocessor reduces the system BOM and shortens the schedule of UI design by high level C program. MT8205/8203 is a cost-effective and high performance HDTV-ready solution to TV manufactures.

FEATURES

Video Input Input Multiplexing: Without external switch, it supports 1x Component, 1x S-video, 1x VGA/Component, (dual function ports) 1x Digital and 3x Composite inputs All the input sources can be flexibly routed to Main/PIP internally Input Formats: Support VGA input up to SXGA (1280x1024@60Hz) including SOG VGA Support HDTV 480p/720p/1080i input Support DVI 24-bit RGB digital input Support CCIR-656/601 digital input

TV decoder For PIP/POP: Dual identical TVD on chip (Single on MT8203) 3D-Comb for both path. Dual VBI decoders for the application of V-Chip Supporting formats: Support PAL (B,G,D,H,M,N,I,Nc), PAL(Nc), PAL, NTSC, NTSC-4.43, SECAM Automatic Luma/Chroma gain control Automatic TV standard detection NTSC/PAL Motion Adaptive 3D comb filter Motion Adaptive 3D Noise Reduction VBI decoder for Closed-Caption/XDS/ Teletext/WSS/VPS Macrovision detection

MT8205 DOCUMENT ARE SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE

Page 3 July, 2004

2D-Graphic/OSD processor Two OSD planes. (For example, Teletext and V-Chip will occupy one planes) Support alpha blending among these two planes and video Support Text/Bitmap decoder Support line/rectangle/gradient fill Support bitblt Support color Key function Support Clip Mask 65535/256/16/4/2-color bitmap format OSD, Automatic vertical scrolling of OSD image Support OSD mirror and upside down

Host Micro controller Turbo 8032 micro controller Built-in internal 373 and 8-bit programmable lower address port 2048-bytes on-chip RAM Up to 4M bytes FLASH-programming interface Supports 5/3.3-Volt. FLASH interface Supports power-down mode Supports additional serial interface IR control serial input Support RS232 interface Support single interface directly supporting SD/MS/MMC memory card Support 2 PWM output Support DDC2Bi/DDC2B/DDC1/DDCCI Maximum 48 programmable GPIO pins DRAM Controller Supports up to 32M-byte SDR/DDR DRAM Supports 16 bit DDR or 32 bit SDR/DDR bus interface Build in a DRAM interface programmable clock to optimize the DRAM performance Programmable DRAM access cycle and refresh cycle timings Maximum DRAM clock rate is 166MHz Support 3.3/2.5-Volt SDR/DDR Interface

Video Processor Color Management Flesh tone and multiple-color enhancement. (For skin, sky, and grass…) Gamma/anti-Gamma correction Color Transient Improvement (CTI) Saturation/hue adjustment Contrast/Brightness/Sharpness Management Sharpness and DLTI/DCTI Brightness and contrast adjustment Black level extender White peak level limiter Adaptive Luma/Chroma management De-interlacing Automatic detect film or video source


Page 4 July, 2004

3:2/2:2 pull down source detection Advanced Motion adaptive de-interlacing Scaling Arbitrary ratio vertical/horizontal scaling of video, from 1/32X to 32X Advanced linear and non-linear Panorama scaling. Programmable Zoom viewer Picture-in-Picture (PIP) Picture-Out-Picture (POP) Display 12/10, 10/8, 8/6 Dithering processing for LCD display 10bit gamma correction Support Alpha blending for Video and two OSD planes Frame rate conversion

Audio Input/Output 2 path TV audio in. Support AF/SIF decode from Tuner. 2 channel audio L/R digital line in. Total support 12 channel digital outputs optional for general stereo, 2.1 channel with subwoofer, 5.1 channel, and

headphone out.

Audio Features Support BTSC/EIAJ/A2/NICAM decode Stereo demodulation, SAP demodulation Mode selection (Main/SAP/Stereo) Equalizer Sub-woofer/Bass enhancement MTK proprietary 3D surround processing (Virtual surround) Audio and video lip synchronization Support Reverberation

JPEG Decoder Decode base-line/progressive JPEG file thru memory card i/f SD/MS/MMC, Maximum 1000 files (depend on DRAM size), FW is not finished yet. (10/E will be ready)

Video Output 480i/576i/480p/576p/720p/1080i Up to (1280x1024@75Hz) (1366x768@60Hz) Dual-channel 6/8-bit LVDS/TTL output Support video output mirror and upside down

DRAM Usage For features of 8205, 2pcs of 8x16 DDR166 is necessary For features of 8203, 2/1pcs of 8x16 DDR (limited PIP/POP features) Here is a comparison chart between (2xDDR) and (1xDDR)


Page 5 July, 2004

DDR*1(16Mb) DDR*2(32Mb) NR Y Y 3D-Comb Y Y MDDi 480i/576i 1080i PIP *Y Y POP *Y Y Display 1024x768 1920x1080 For 1080i input, 8203 only support bob mode de-interlacing. With single DDR, we could support very limited PIP/POP mode.

Flash Usage Flash is used to store FW code, fonts, bitmaps, big tables for VGA, Video, Gamma.. In our demo system, we can support 2-4 languages within 1MB flash. For single country, we need around 20KB to store font data. For more bitmaps, we need more flash space to store them. 2Mbytes is recommended to build a general TV model.

Outline 388-pin BGA package 3.3/1.8-Volt. Dual operating voltages 0.18um UMC process

MT8205 PRELIMINARY, SUBJECT TO CHANGE WITHOUT NOTICE MTK CONFIDENTIAL, NO DISCLOSURE

Page 6 July, 2004

BLOCK DIAGRAM

ADC

ADC

ADC

ADC

3D TVD

3D TVD

HDTVD

VGAD

DS

PLCDI DS

Digital Path

Analog Front End

Main Path

PIP Path

MU

X DR

AM

2D GraphOSD

USColor

CVBS (AV)

YPbPr

S(Customer)

ExternalSwitches

Digital

VGA (aRGB)

(x3)

Control Signal (GPIO, …)

Gamma

OSDMerge

Dithering

TTLLVDS LVDS Tx

8032

DSP

Analog Path

MDDiMLC

®

Technology

SiI 169 HDCP PanelLink Receiver

Data Sheet

Document # SiI-DS-0049-B

SiI 169 HDCP PanelLink Receiver Data Sheet

ii SiI-DS-0049-B

Silicon Image, Inc. SiI-DS-0049-B August 2002 Application Information To obtain the most updated Application Notes and other useful information for your design, contact your local Silicon Image sales office. Please also visit the Silicon Image web site at www.siliconimage.com.

Copyright Notice This manual is copyrighted by Silicon Image, Inc. Do not reproduce, transform to any other format, or send/transmit any part of this documentation without the expressed written permission of Silicon Image, Inc.

Trademark Acknowledgment Silicon Image, the Silicon Image logo, PanelLink® and the PanelLink® Digital logo are registered trademarks of Silicon Image, Inc. TMDSTM is a trademark of Silicon Image, Inc. VESA® is a registered trademark of the Video Electronics Standards Association. All other trademarks are the property of their respective holders.

Disclaimer This document provides technical information for the user. Silicon Image, Inc. reserves the right to modify the information in this document as necessary. The customer should make sure that they have the most recent data sheet version. Silicon Image, Inc. holds no responsibility for any errors that may appear in this document. Customers should take appropriate action to ensure their use of the products does not infringe upon any patents. Silicon Image, Inc. respects valid patent rights of third parties and does not infringe upon or assist others to infringe upon such rights.

Revision History Revision Date Comment A 07/18/2002 Release to Production with complete parametric information. B 08/14/2002 Correction to DDC bus voltage level-shifting diagram; add Pb-free part number.

© 2002 Silicon Image. Inc.


SiI-DS-0049-B iii

TABLE OF CONTENTS

Functional Description .................................................................................................................................... 2 PanelLink TMDS Core ................................................................................................................................ 2 I2C Interface and Registers ......................................................................................................................... 2 HDCP Decryption Engine and XOR Mask .................................................................................................. 3 HDCP Keys EEPROM................................................................................................................................. 3 Panel Interface Logic and Configuration Logic ........................................................................................... 3

Electrical Specifications .................................................................................................................................. 4 Absolute Maximum Conditions.................................................................................................................... 4 Normal Operating Conditions...................................................................................................................... 4 DC Specifications........................................................................................................................................ 5 AC Specifications ........................................................................................................................................ 6 Timing Diagrams ......................................................................................................................................... 8

Input Timing............................................................................................................................................. 8 Output Timing .......................................................................................................................................... 8

Pin Descriptions.............................................................................................................................................11 Digital Output Pins......................................................................................................................................11 Configuration Pins ......................................................................................................................................11 HDCP Pins ................................................................................................................................................ 12 Power Management Pins .......................................................................................................................... 12 Differential Signal Data Pins...................................................................................................................... 12 Reserved Pin............................................................................................................................................. 12 Power and Ground Pins ............................................................................................................................ 13

Feature Information ...................................................................................................................................... 14 HSYNC De-jitter Function ......................................................................................................................... 14 Clock Detect Function ............................................................................................................................... 14 Sync Detect Function ................................................................................................................................ 14 OCK_INV Function.................................................................................................................................... 14 TFT Panel Data Mapping .......................................................................................................................... 16 Power Management .................................................................................................................................. 22 HDCP Operation ....................................................................................................................................... 23

HDCP Authentication............................................................................................................................. 23 SiI 169 HDCP Implementation .............................................................................................................. 24 HDCP DDC / I2C Interface..................................................................................................................... 24 Video Requirement for I2C Access ........................................................................................................ 25 I2C Registers.......................................................................................................................................... 25

Using SiI 169 in SiI 161B Designs ............................................................................................................ 28 EXT_RES Resistor Choice ....................................................................................................................... 29 Power Control............................................................................................................................................ 30 Receiver DDC Bus Level-Shifting ............................................................................................................. 30 Voltage Ripple Regulation ......................................................................................................................... 31 Decoupling Capacitors .............................................................................................................................. 32 ESD Protection.......................................................................................................................................... 32 Receiver Layout ........................................................................................................................................ 33 EMI Considerations................................................................................................................................... 33 PCB Thermal Design ................................................................................................................................ 33

Determining Heat Dissipation Requirements ........................................................................................ 33 Implementation Guidelines for Thermal Land Design ........................................................................... 34 Board Mounting Guidelines ................................................................................................................... 36 Stencil Design........................................................................................................................................ 37

Package........................................................................................................................................................ 38 Ordering Information..................................................................................................................................... 38


iv SiI-DS-0049-B

LIST OF TABLES

Table 1. One Pixel per Clock Mode Data Mapping ....................................................................................... 16 Table 2. Two Pixel per Clock Mode Data Mapping ....................................................................................... 16 Table 3. One Pixel per Clock Input/Output TFT Mode – VESA P&D and FPDI-2TM Compliant.................... 17 Table 4. Two Pixels/Clock Input/Output TFT Mode ...................................................................................... 18 Table 5. 24-bit One Pixel per Clock Input with 24-bit Two Pixel per Clock Output TFT Mode...................... 19 Table 6. 18-bit One Pixel per Clock Input with 18-bit Two Pixel per Clock Output TFT Mode...................... 20 Table 7. Two Pixel per Clock Input with One Pixel per Clock Output TFT Mode.......................................... 21 Table 8. Power Management Functionality Table ......................................................................................... 22 Table 9. I2C Register Mapping ...................................................................................................................... 26 Table 10. I2C Register Definitions ................................................................................................................. 27 Table 11. Link Impedance vs EXT_RES Value (all values in Ohms) ............................................................ 29 Table 12. Power Consumption Characteristics ............................................................................................. 30 Table 13. Recommended Components ........................................................................................................ 32

LIST OF FIGURES Figure 1. SiI 169 Pin Diagram......................................................................................................................... 1 Figure 2. Functional Block Diagram................................................................................................................ 2 Figure 3. Channel-to-Channel Skew Timing................................................................................................... 8 Figure 4. Digital Output Transition Times ....................................................................................................... 8 Figure 5. Receiver Clock Cycle/High/Low Times............................................................................................ 8 Figure 6. Output Signals Setup/Hold Times.................................................................................................... 9 Figure 7. Output Signals Disabled Timing from PD# Active ........................................................................... 9 Figure 8. Output Signals Disabled Timing from Input Clock Inactive.............................................................. 9 Figure 9. Input Clock Active to Output Active ................................................................................................ 9 Figure 10. SCDT Timing from DE Inactive/Active......................................................................................... 10 Figure 11. TFT Two Pixels per Clock Staggered Output Timing Diagram.................................................... 10 Figure 12. I2C Data Valid Delay (driving Read Cycle data) ........................................................................... 10 Figure 13. Block Diagram for OCK_INV ....................................................................................................... 15 Figure 14. HDCP System Architecture ........................................................................................................ 23 Figure 15. I2C Byte Read .............................................................................................................................. 24 Figure 16. I2C Byte Write .............................................................................................................................. 24 Figure 17. Short Read Sequence ................................................................................................................. 25 Figure 18. Design Using SiI 161B or SiI 169 ................................................................................................ 29 Figure 19. DDC Bus Voltage Level-Shifting using Fairchild NDC7002N ...................................................... 30 Figure 20. Voltage Regulation using Texas Instruments TL431 ................................................................... 31 Figure 21. Voltage Regulation using National Semiconductor LM317.......................................................... 31 Figure 22. Decoupling and Bypass Schematic ............................................................................................. 32 Figure 23. Decoupling and Bypass Capacitor Placement ............................................................................ 32 Figure 24. DVI to Receiver Routing - Top View ............................................................................................ 33 Figure 25. Bottom View of Thermally Enhanced 100-pin TQFP Package.................................................... 34 Figure 26. TQFP Thermal Land Design on PCB .......................................................................................... 35 Figure 27. Thermal Pad Via Grid .................................................................................................................. 36 Figure 28. Recommended Stencil Design .................................................................................................... 37 Figure 29. Package Diagram ........................................................................................................................ 38


SiI-DS-0049-B 1

General Description Features The SiI 169 Receiver uses PanelLink Digital technology to support HDTV and high-resolution digital displays for DTV and PC applications. It features High-bandwidth Digital Content Protection (HDCP) for secure delivery of high-definition video in consumer electronics products. The SiI 169 comes with integrated, pre-programmed HDCP keys, greatly simplifying manufacturing and providing the highest level of security. For improved ease of use, the SiI 169 has enhanced jitter tolerance and a low-power standby mode. PanelLink Digital technology is the world’s leading DVI solution, providing a digital interface solution that is easy to implement and cost-effective. PanelLink further simplifies the display interface design by resolving many of the system level issues associated with high-speed mixed signal circuits.

• Integrated 25-165MHz PanelLink core to support VGA to UXGA resolutions

• Supports HDTV resolutions (720p/1080i) • Integrated HDCP decryption engine for viewing

protected content • Pre-programmed HDCP keys provide highest

level of key security, simplify manufacturing • Enhanced jitter tolerance • Time staggered data output for reduced ground

bounce • High Skew Tolerance: 1 full input clock cycle

(6ns at 165MHz) • Backwards compatible with SiI 161B • Sync Detect for “Hot Plugging” • Flexible low power modes with automatic power

down when input clock is inactive • Low power 3.3V core operation • Compliant with DVI 1.0 • Standard and Pb-free packages (see page 38).

SiI 169 Pin Diagram

RESET#1

SiI 169100-pin TQFP

(Top View)

PD#2SDA3PIXS4GND5VCC6STAG_OUT7SCDT8PDO#9QE010

QE111

QE212QE313QE414QE515QE616QE717OVCC18OGND19QE820

QE921QE1022QE1123QE1224QE1325

QE1

426

QE1

527

OG

ND

28

OVC

C29

QE1

630

QE1

731

QE1

832

QE1

933

QE2

034

QE2

135

QE2

236

QE2

337

VCC

38

GN

D39

HS_

DJT

R40

OC

K_IN

V41

CTL

342

OVC

C43

OD

CK

44O

GN

D45

DE

46

VSYN

C47

HSY

NC

48

QO

049

QO

150

75

QO21 74QO20 73

QO19 72QO18 71QO17 70QO16 69GND 68VCC 67

QO15 66

QO14 65

QO13 64

QO12 63QO11 62QO10 61QO9 60QO8 59

OGND 58OVCC 57

QO7 56

QO6 55

QO5 54QO4 53QO3 52

QO2 51

QO22

SCL

100

RES

ERVE

D99

PGN

D98

PVC

C97

EXT_

RES

96

AVC

C95

RXC

-94

RXC

+93

AGN

D92

RX0

-91

RX0

+90

AGN

D89

AVC

C88

AGN

D87

RX1

-86

RX1

+85

AVC

C84

AGN

D83

AVC

C82

RX2

-81

RX2

+80

AGN

D79

OVC

C78

QO

2377

OG

ND

76

DIFFERENTIAL SIGNALS

OD

D 8

-bits

RED

EVEN 8-bits RED

OD

D 8

-bits

GR

EEN

EVEN 8-bits G

REEN

OD

D 8

-bits

BLU

E

EVEN 8-bits B

LUE

CO

NFIG

. PINS

PLL

OU

TPU

TC

LOC

K

CONTROLS

Figure 1. SiI 169 Pin Diagram


2 SiI-DS-0049-B

Functional Description The SiI 169 is a DVI 1.0 compliant digital-output receiver with built-in High-bandwidth Digital Content Protection (HDCP). It provides a simple, cost effective solution for DTVs implementing DVI-HDCP. Pre-programmed HDCP keys simplify manufacturing while providing the highest level of security. There is no need to use encrypted keys, program EEPROMs, or cure epoxy coating.

Figure 2 shows the functional blocks of the chip.

Figure 2. Functional Block Diagram

PanelLink TMDS Core The PanelLink TMDS core accepts as inputs the three TMDS differential data lines and the differential clock. The core senses the signals on the link and properly decodes them providing accurate pixel data. The core outputs the necessary sync signals (HSYNC, VSYNC), clock (ODCK), and a display enable (DE) signal that drives high when video pixel data is present. The SCDT signal is output when there is active video on the DVI link and the PLL has locked on to the video. SCDT can be used to trigger external circuitry, indicating that an active video signal is present; or used to place the device outputs in power down when no signal is present (by tying SCDT to PDO#). A resistor tied to the EXT_RES pin is used for impedance matching.

I2C Interface and Registers The SiI 169 uses a slave I2C interface, capable of running at 400kHz, for communication with the host. HDCP authentication is managed by reading and writing to registers through the I2C interface. This bus, called DDC in the DVI specification, is also tied to the EDID EEPROM that contains information about the display’s capabilities (resolution, aspect ratio, etc.). The I2C address of the SiI 169 is 74h as specified by HDCP. This interface is not 5V tolerant and it is recommended that a voltage level shifter be used between the SiI 169 and the DVI connector as the DDC bus is specified to support 5V signaling.

Registers--------------

Configuration Logic

PanelInterface

Logic

EXT_RES

PanelLinkTMDSTM

DigitalCore

QE[23:0]

SCLS

SCDT

ODCK

DE

XORMaskRX1±

RX0±

RXC±

RX2±

QO[23:0]

HSYNC

VSYNC

CTL3

I2CSlaveSDAS

STAG

_OU

T

PIXS

OC

K_IN

V

HS_

DJT

R

HDCPKeys

EEPROMR

ESET

#

24/

encrypteddata

24/

unencrypteddata

control

PD#

PDO

#

HDCPDecryption

Engine


SiI-DS-0049-B 3

HDCP Decryption Engine and XOR Mask The HDCP decryption engine contains all the necessary logic to decrypt an incoming video signal on a pixel-by-pixel basis. The host system microcontroller initiates an authentication sequence with the receiver to initialize the SiI 169 HDCP decryption engine. Upon successful completion of the authentication process, the SiI 169 is ready to decrypt the incoming video via the XOR mask.

Encrypted and unencrypted video will be sent at different times. Therefore the host HDCP transmitter uses the CTL3 signal to indicate to the SiI 169 receiver whether the incoming video is encrypted or not.

HDCP Keys EEPROM The SiI 169 comes pre-programmed with a production set of HDCP keys in its internal EEPROM. In this way the keys are provided the highest level of protection as required by the HDCP specification. Silicon Image manages all aspects of the key purchasing and programming. There is no need for the customer to purchase HDCP keys from the licensing authority. For security reasons, the keys cannot be read out of the device.

Samples of the SiI 169 are available with the B1 public keys as listed in the back of the HDCP specification. These are marked with a -PUB part number as noted in the Ordering Information section. Make sure to request either “Public” or “Production” keys when requesting samples. Before receiving samples of the SiI 169 with production keys a customer must have signed the HDCP license agreement.

Panel Interface Logic and Configuration Logic Unencrypted video data is sent to the display logic by way of a 48-bit output interface. The functionality of this interface is affected by several of the externally strapped configuration logic options as follows.

• The data output can be presented in either one pixel per clock or two pixels per clock format, depending on the PIXS configuration setting.

• The polarity of the output clock ODCK can be inverted to accommodate both rising- and falling-edge clocking through the OCK_INV configuration setting.

• Using the STAG_OUT configuration setting, the odd and even data output groups can be staggered in time to reduce EMI.

• The HS_DJTR configuration setting can compensate for host-side jitter on the HSYNC input to the transmitter.

• The PD# and PDO# inputs select chip power down modes and allow for disabling of the outputs to the panel.

The RESET# input must be in the HIGH state during normal operation, in both HDCP and non-HDCP modes. Its primary purpose is to reset the digital block circuitries, including the HDCP engine, and registers at initial chip power-up time. The VSYNC, HSYNC, DE, and CTL3 signals will be driven low while RESET# is asserted. If it is necessary to disable the HDCP engine while leaving the chip fully operational for reception of unencrypted video, use the software reset feature located at bit 0 of register 0xFF by setting it to “1”.

ESMT M13S128168A

Elite Semiconductor Memory Technology Inc. Publication Date : Mar. 2004 Revision : 1.3 1/48

Revision History Revision 0.1 (15 Jan. 2002)

- Original

Revision 0.2 (19 Nov. 2002)

-changed ordering information & DC/AC characteristics

Revision 0.1 Revision 0.2

M13S128168A - 5T M13S128168A - 6T

M13S128168A - 6T M13S128168A - 7.5AB

Revision 0.3 (8 Aug. 2003)

-Change IDD6 from 3mA to 5mA.

Revision 0.4 (27 Aug. 2003)

-Change ordering information & DC / AC characteristics.

Revision 1.0 (21 Oct. 2003)

-Modify tWTR from 2tck to 1tck.

Revision 1.1 (10 Nov. 2003)

-Correct some refresh interval that is not revised.

-Correct some CAS Lantency that is not revised.

Revision 1.2 (12 Jan. 2004)

-Correct IDD1; IDD4R and IDD4W test condition.

-Correct tRCD; tRP unit

-Add tCCD spec.

-Add tDAL spec.

Revision 1.3 (12 Mar. 2004)

-Add Cas Latency=2; 2.5

ESMT M13S128168A


DDR SDRAM 2M x 16 Bit x 4 Banks

Double Data Rate SDRAM Features

JEDEC Standard

Internal pipelined double-data-rate architecture, two data access per clock cycle

Bi-directional data strobe (DQS)

On-chip DLL

Differential clock inputs (CLK and CLK )

DLL aligns DQ and DQS transition with CLK transition

Quad bank operation

CAS Latency : 2; 2.5; 3

Burst Type : Sequential and Interleave

Burst Length : 2, 4, 8

All inputs except data & DM are sampled at the rising edge of the system clock(CLK)

Data I/O transitions on both edges of data strobe (DQS)

DQS is edge-aligned with data for reads; center-aligned with data for WRITE

Data mask (DM) for write masking only

VDD = 2.375V ~ 2.75V, VDDQ = 2.375V ~ 2.75V

Auto & Self refresh

7.8us refresh interval

SSTL-2 I/O interface

66pin TSOPII package

Operating Frequencies :

PRODUCT NO. MAX FREQ VDD PACKAGE

M13S128168A -5T 200MHz

M13S128168A -6T 166MHz 2.5V TSOPII

ESMT M13S128168A


Con

trol L

ogic

Functional Block Diagram

Pin Arrangement

Bank A

Com

man

d D

ecod

er

Bank D

Latc

h C

ircui

t

Bank BBank C

DM

DQ

Mode Register & Extended Mode Register

ColumnAddressBuffer & RefreshCounter

Row AddressBuffer & RefreshCounter R

ow D

ecod

er

Sense Amplifier

Column Decoder

Data Control Circuit

Inpu

t & O

utpu

t B

uffe

r

Address

Clock Generator

CLK CLK CKE

CS

RAS

CAS

WE

DLL DQSCLK, CLK DQS

123456789101112131415161718192021222324252627282930313233

66 PIN TSOP(II) (400mil x 875mil)(0.65 mm PIN PITCH)

VDD

DQ0

VDDQ

DQ1

DQ2

VSSQ

DQ3

DQ4

VDDQ

DQ5

DQ6

VSSQ

DQ7

N CVDDQ

LDQSN CVDD

N CLDMWECASRASCSN CBA0

BA1

A10/APA0

A1

A2

A3

VDD

VSS

DQ15

VSSQ

DQ14

DQ13

VDDQ

DQ12

DQ11

VSSQ

DQ10

DQ9

VDDQ

DQ8

N CVSSQ

UDQSN CVREF

VSS

UDMCLKCLKCKEN CN CA11

A9

A8

A7

A6

A5

A4

VSS

666564636261605958575655545352515049484746454443424140393837363534

x16 x16

MP7720 20W Class D Mono

Single Ended Audio Amplifier

PRELIMINARY INFORMATION

MP7720 Rev 1.5 06/17/04 www.monolithicpower.com 1

Monolithic Power Systems

General Description The MP7720 is a mono 20W Class-D Audio Amplifier. It is one of MPS’ second generation of fully integrated audio amplifiers which dramatically reduces solution size by integrating the following:

180mΩ power MOSFETs Start up / shut down pop elimination Short circuit protection circuits Mute / Stand By

The MP7720 utilizes a single ended output structure capable of delivering 20W into 4Ω speakers. MPS Class-D Audio Amplifiers exhibit the high fidelity of a Class A/B amplifier at efficiencies greater than 90%. The circuit is based on the MPS’ proprietary variable frequency topology that delivers excellent PSRR, fast response time and operates on a single power supply.

Ordering Information

Part Number ∗ Package Temperature MP7720DS SOIC8 -40°C to + 85°C MP7720DP PDIP8 -40°C to + 85°C EV0030 Evaluation Board

∗ For Tape & Reel use suffix - Z (e.g. MP7720DS-Z)

∗ For Lead Free use suffix - LF (e.g. MP7720DS-LF)

ON OFF

VDD 7.5V to 24V

Audio Input

EN PIN NIN AGND

VDD PGND

BS SW

4 Ω or 8 Ω

Figure 1: Typical Application Circuit

Features

20W output at VDD=24V into a 4Ω load THD+N = 0.04% @ 1W, 8Ω 93% efficiency at 20W Low noise (190µV typical) Switching Frequency to 1MHz 9.5V to 24V operation from single supply Integrated Start Up and Shut Down Pop Elimination Circuit Thermal protection Integrated 180mΩ switches Mute / Standby-mode (Sleep) Tiny 8 Pin SOIC or PDIP Package Evaluation Board Available

Applications Surround Sound DVD Systems Televisions Flat Panel Monitors Multimedia computers Home stereo

0.01

20

0.02

0.05

0.1

0.2

0.5

1

2

5

10

%

60m

30

100m

200m

500m

1 2

5 10

20

W

4Ω8Ω

Figure 2: THD+N vs. Power (24V, 1KHz)






Absolute Maximum Ratings (Note 1) Supply Voltage VDD 26V BS Voltage VSW-0.3V to VSW+6.5V Enable Voltage VEN -0.3V to 6V VSW, VPIN, VNIN -1V to VDD+1V AGND to PGND -0.3V to 0.3V Junction Temperature 150°C Lead Temperature 260°C Storage Temperature -65°C to 150°C

Recommended Operating Conditions (Note 2) Supply Voltage VDD 9.5V to 24V Operating Temperature TA -40°C to 85°C Package Thermal Characteristics Thermal Resistance ΘJA (SOIC8) 105°C/W Thermal Resistance ΘJC (SOIC8) 50°C/W Thermal Resistance ΘJA (PDIP8) 95°C/W Thermal Resistance ΘJC (PDIP8) 55°C/W

Table 1: Electrical Characteristics (VDD=24V, VEN=5V, TA=25°C) Parameters Condition Typ Max Units Supply Current Standby Current VEN = 0V 1 5 µA Quiescent Current 1.5 3.0 mA Output Drivers SW On Resistance Sourcing and Sinking 0.18 Ω Short Circuit Current Sourcing and Sinking 5.0 A Inputs PIN, NIN Input Common Mode Voltage Range 0 VDD

2 VDD-1.5 V

PIN, NIN Input Current VPIN=VNIN=12V 1 5 µA VEN Rising 1.4 2.0 V EN Enable Threshold Voltage VEN Falling 0.4 1.2 V

EN Enable Input Current VEN = 5V 1 µA Thermal Shutdown Thermal Shutdown Trip Point TJ Rising 150 °C Thermal Shutdown Hysteresis 30 °C

Table 2: Operating Specifications (Circuit of Figure 3, VDD=24V, VEN=5V, TA=25°C) Standby Current VEN = 0V 130 µA Quiescent Current 13 mA

f=1KHz, THD+N = 10% , 4Ω Load 20 W Power Output f=1KHz, THD+N = 10% , 8Ω Load 10 W POUT=1W, f=1KHz, 4Ω Load 0.08 % THD+ Noise POUT=1W, f=1KHz, 8Ω Load 0.04 % f =1KHz, POUT=1W, 4Ω Load 90 % Efficiency f =1KHz, POUT=1W, 8Ω Load 95 %

Maximum Power Bandwidth 20 KHz Dynamic Range 93 dB Noise Floor A-Weighted 190 µV Power Supply Rejection f=1KHz 60 dB

Note 1. Exceeding these ratings may damage the device. Note 2. The device is not guaranteed to function outside its operating rating.






MP7720

ON OFF

VDD 9.5 to 24V

Audio Input

EN PIN NIN AGND

VDD

PGND

BS

SW

C1 1µF, 16V

R1, 10KΩ

R2 100KΩ

C2 4.7µF, 16V

C3, 5.6nF

R4, 82KΩ

C7, 0.1µF

C6 470µF, 35V

D2, 6.2V

D1 1A, 30V

L1, 10µH

C8 0.47µF 50V Metal

C9 1000µF

25V

C4 10pF

C5 1µF, 35V

R3 100KΩ

C10390pF

RL 4Ω

R5 10kΩ

R610KΩ

Figure 3: 20W Mono Typical Application Circuit


0. Warnings and CautionsWARNING indicates hazards that may lead to death or injury if ignored. CAUTION indicates hazards that may lead to injury or damage to property if ignored.

WARNING1) This product uses a high voltage (450 V max.). Do not touch the circuitry of this product with your hands when

power is supplied to the product or immediately after turning off the power. Be sure to confirm that the voltageis dropped to a sufficiently low level.

2) Do not supply a voltage higher than that specified to this product. This may damage the product and may cause afire.

3) Do not use this product in locations where the humidity is extremely high, where it may be splashed with water,or where flammable materials surround it. Do not install or use the product in a location that does no satisfy thespecified environmental conditions. This may damage the product and may cause a fire.

4) If a foreign substance (such as water, metal, or liquid) gets inside the product, immediately turn off the power.Continuing to use the products it may cause fire or electric shock.

5) If the product emits smoke, an abnormal smell, or makes an abnormal sound, immediately turn off the power. Ifnoting is displayed or if the display goes out during use, immediately turn off the power. Continuing to use theproduct as it is may cause fire or electric shock.

6) Do not disconnect or connect the connector while power to the product is on. It takes some time for the voltageto drop to a sufficiently low level after the power has been turned off. Confirm that the voltage has dropped to asafe level before disconnecting or connecting the connector. Otherwise, this may cause fire, electric shock, ormalfunction.

7) Do not pull out or insert the power cable from/to an outlet with wet hands. It may cause electric shock.

8) Do not damage or modify the power cable. It may cause fire or electric shock.

9) If the power cable is damaged, or if the connector is loose, do not use the product; otherwise, this can lead to fireor electric shock.

10) If the power connector or the connector of the power cable becomes dirty or dusty, wipe it with a dry cloth. Otherwise, this can lead to fire.


USE1) Because this product uses a high voltage, connecting or disconnecting the connectors while power is supplied to

the product may cause malfunctioning. Never connect or disconnect the connectors while the power is on.Immediately after power has been turned off, a residual voltage remains in the product. Be sure to confirm thatthe voltage has dropped to a sufficiently low level.

2) Watching the display for a long time can tire the eyes. Take a break at appropriate intervals.

3) PDP ’s brightness and contrast ratio is lower than that of the CRT. The picture is dimmer with surrounding light and better for viewing in dark condition.

4) Do not cover or wrap the product with a cloth or other covering while power is supplied to the product.

5) Before turning on power to the product, check the wiring of the product and confirm that the supply voltage iswithin the rated voltage range. If the wiring is wrong or if a voltage outside the rated range is applied, theproduct may malfunction or be damaged.

6) Do not store this product in a location where temperature and humidity are high. This may cause the product tomalfunction. Because this product uses a discharge phenomenon, it may take time to light (operation may bedelayed) when the product is used after it has been stored for a long time. In this case, it is recommended to lightall cells for about 2hours (aging).

7) If the glass surface of the display becomes dirty, wipe it with a soft cloth moistened with a neutral detergent. Donot use acidic or alkaline liquids, or organic solvents.

8) Do not tilt or turn upside down while the module package is carried, the product may be damaged.

9) This product is made from various materials such as glass, metal, and plastic. When discarding it, be sure tocontact a professional waste disposal operator.

Repair and MaintenanceBecause this product combines the display panel and driver circuits in a single module, it cannot be repaired ormaintained at user’s office or plant. Arrangements for maintenance and repair will be determined later


1. GENERAL DESCRIPTION

DESCRIPTIONThe PDP42V6#### is a 42-inch 16:9 color plasma display module with resolution of 852(H)× 480(V) pixels.This is the display device which offers vivid colors with adopting AC plasma technology by LG Electronics Inc.

FEARURESHigh peak brightness (1000cd/m2 Typical) and high contrast ratio (3000:1 Typical) enables user to createhigh performance PDP SETs.

APPLICATIONS

Public information display Video conference systems Education and training systems


ELECTRICAL INTERFACE OF PLASMA DISPLAYThe PDP42V6#### requires only 8bits of digital video signals for each RGB color.In addition to the video signals, six different DC voltages are required to operate the display.The PDP42V6#### is equipped with P-CUBE function which analyzes display signals to optimize systemcontrol factor for showing the best display performance.

2ndpixelcolumn

GENERAL SPECFICATIONS

Model Name Number of Pixels Pixel Pitch Cell Pitch Display Area Outline Dimension Pixel Type Number of Gradations Weight

Aspect Ratio Peak Brightness Contrast Ratio

Power Consumption Life-time

: PDP42V6#### (42V6#### Model): 852(H) × 480(V) (1pixel=3 RGB cells) : 1080 (H) × 1080 (V): 367 (H) × 1080 (V) (Green Cell basis): 920.1(H) × 518.4(V) ±0.5mm: 1005(H) × 597(V) × 61(D)±1mm: RGB Closed type: (R)256 × (G)256 × (B)256 (16.7 Mega colors): 14.8 Kg ± 0.5 Kg (Net 1EA)

111 Kg ± 5 Kg (5EA/1BOX): 16:9: Typical 1000cd/ (1/25 White Window): Average 60:1 (In a bright room with 150Lux at center): Typical 3000:1 (In a dark room 1/25 White Window pattern at center): Typical 220 W (Full White): more than 60,000 Hours of continuous operation

Life-time is defined as the time when the brightness level becomes half of its initial value.

Pixel Pitch(width) Cell pitch

cell

pixel

1stpixelcolumn

851thpixelcolumn

852thpixelcolumn

pitc

h(he

ight

)

1st pixelrow2nd pixelrow

3rd pixelrow

479th pixelrow

480th pixelrow

R:0.338G:0.367B:0.374

1.080

1.08

0

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

BGR BGR

Display Dot Diagram


7. CONNECTORS and CONNECTIONS Power Input Connector

Pin No. Symbol

1

2

3

4

Vs

Vs

nc

GND

Pin No. Symbol

5

6

7

8

GND

Va

GND

+5V

Connector P3001 Pin Assignment

Module side connector : 1-1123723-8 (Header)Mating Connector : 1-1123722-8 (Housing) Connector Supplier : AMP

1-1123723-8 Pin numbers(Top View, viewed from the pin connection side)

12345678


Module side connector : 1-1123723-10 (Header)Mating Connector : 1-1123722 –10 (Housing) Connector Supplier : AMP


12345678910


Module side connector : 1-1123723-4 (Header)Mating Connector : 1-1123722-4 (Housing) Connector Supplier : AMP


Pin No. Symbol

1

2

5V

5V

Pin No. Symbol

3

4GND

GND 1234

Pin No. Symbol

1

2

3

4 nc

Pin No. Symbol

6

7

GND

GND5

8

VS

9

10

nc

GND

GND

nc

VS

VS

Product Specification of Power Supply Unit

8. Input/Output pin assignment & specification

Pin Assignment

1 2

8 7 6 5 4 3 2 1

10 9 8 7 6 5 4 3 2 1

4 3 2 1 12345678

123456789

123456789101112

1234

1234567

#1 : Vs#2 : Vs#3 : NC#4 : GND#5 : GND#6 : Va#7 : GND#8 : +5V

CN807CN806

#1 : Va#2 : Va#3 : GND#4 : GND#5 : GND#6 : GND#7 : NC#8 : Vs#9 : Vs#10 : Vs

#1 ~#2: 5Vctrl#3 ~ #4: GND

CN805CN808#1 ~ #4: +5Vctrl#5 ~ #8: GND

CN804

CN803

#1 ~ #3 : 5Vsc#4 ~ #6 : GND#7, #8 : 12Vsc#9, #10 : GND #11, #12 : NC

CN802 #1 ~#2: 30V or 24V #3 ~ #4: GND

CN801 #1 : ACD#2 : RLY ON#3 : 5Vst_by#4 : GND#5 : Vs ON#6 : 5VD#7 : NC

CN02 CN03CN01

Before connecting with S/W

From inlet

AMP171825-2CN809

AMP171825-8CN808

AMP1-1123723-8CN807

AMP1-1123723-0CN806

AMP1-1123723-4CN805

AMP171825-9CN804

AMP1-171825-2CN803

AMP171825-4CN802

AMP171825-7CN801

AMP3-176976-1(Natural)CN03

AMP3-176976-1(Natural)CN02

AMP3-176976-2(Red)CN01

VendorSpecificationLocation No.

Live

Neutral

Live

Neutral After connecting with S/W

CN8091

2

#1 : 9Vsc#2: GND

1 2

* PSU operation method S/W

Normal : On/Off with Vsc B/D

Auto : Automatic On/Off without Vsc B/D

Selection S/W

24V 30V

#1 : 9Vsc#2 : 9Vsc#3 : GND#4 : 5Vsc#5 : 5Vsc#6 : 5Vsc#7 : GND#8 : GND#9 : GND

1 2

1 2

Product Specification of Power Supply Unit

9. Adjustment detail

Adjustment detail

8 7 6 5 4 3 2 1

123456789

123456789101112

1234

1234567

CN807

CN804

CN803

CN802

CN801

CN8091

2

Selection S/W

24V 30V

1 2

* PSU driving method S/W

Normal(Mode1) : Driving with interface B/D

Auto(Mode2) : Driving without interface B/D

CN02 CN03

CN01

* Connect with Noisefilter Cable

Live

Neutral

Live

Neutral

1 2 1 2

1 2

* You can select output Audio Voltage(24V or 30V)

Vs adj.

Va adj.

* Vs Voltage Variabe Resistor- Turn right, increase VoltageTurn left, decrease Voltage

* Va Voltage Variabe Resistor- Turn right, increase VoltageTurn left, decrease Voltage

* Connect with S/W Cable

※ The color of CN01 is red.(The color of CN02, CN03 are natural.)

Selection S/W

Normal(Mode1)

Auto(Mode2)

* Connect with S/W Cable

12345678

CN80810 9 8 7 6 5 4 3 2 1

CN806CN8054 3 2 1


Y-SUS

E/X Tube

X right

CONTROLLERSignal Input

(R,G,B,H/Vsync.)X left

Z - SUS

3211QKE008A

Coner Plate

P/N(carved)

8. LABEL LABEL Sticking Position

Identification Label : LABEL

①Model Name② Bar Code (Code 128, Contains the manufacture No.)③Manufacture No.④ The trade name of LG Electronics⑤Manufactured date (Year & Month)⑥Manufactured place

7.0

2.5⑦

①

②

③

④ ⑤ ⑥

Trouble Shooting Manual of PDP Module

- Introduction - Precautions - Basic - Trouble shooting

COMPOSITION OF PDP BOARDS

CONTROL B/D

Y-DRIVE

BOTTOM

Y-SUS

B/D

Y-DRIVE

TOP

X-LEFT B/DX-RIGHT B/D

Z-SUS B/D

COFCOF

IPMIPM

1. Introduction

PSU42” V6 MODEL.

Definitions

Exhaust hole

long 1

long 2short 1

short 2

COF long2-1 • • • • • • • • COF long 2-7

Definition of MODULE position

6####

2004.02402K242V6000266.ASLGA

Identification label

① Model Name② Bar Code (Code 128, Contains the manufacture No.)③ Manufacture No.④ The trade name of LG Electronics⑤ Manufactured date (Year & Month)⑥ The place Origin⑦ Model Suffix

①

②

③

④ ⑤ ⑥

⑦

1. Introduction

* Back side of module

Vsc-VyVsetup

Voltage label (Attached on back side of module)

Part No. label (Attached on board)

COF serial No. label (attached on COF)

1. Introduction

PCB PART NO.

BOARD ASS`Y PART NO.

BOARD NAME

BOARD SERIAL NO.

COF SERIAL NO.

8 /40

Terms of defect

Add short (line on)

Sus open (line off)

Sus short (line on)

Add open (line off)

AppearanceTerm

1. Introduction

9 /40

1. Before repairing there must be a preparation for 10 min.

2. Do not impress a voltage that higher than represented on the product.

3. Since PDP module uses high voltages, Be careful a electric shock

and after removing power some current remains in drive circuit.

so you can touch circuit after 1 min.

4. Drive circuits must be protected from static electricity.

5. The PDP module must be Moved by two man.

6. Be careful with short circuit of PDP boards when measuring any voltages.

2. Precaution

Be sure to read this before service. When using/ handling this PDP module, Please pay attention to the

below warning and cautions.

Safety precautions

Before request service

2. Check the model label. Whether it is boards of same model with label.

3. Before requesting Service, please inform us a detail defect phenomenon and history of module.

it can be helpful to us for a smooth sevice.

Ex) COF long 2-1 fail ,address 1 line open, Y b/d problem , mis-discharge.

1. Check panel surface and appearance of B/D.

SCRATCHING TEARING BEING PUSHED

BENDING CHOPING

2. Precaution

COF is the most important component in the PDP module.

Even a little imperfection of COF can make a serious screen problem.

Handle with care (COF)

X LEFT B/D X LEFT B/D X RIGHT B/D X RIGHT B/D

3. Basic

1. X B/D

<COF Separating>

: receiving LOGIC signal from CONTROL B/D and make ADDRESS

PULSE(generates Address discharge)by ON/OFF operation,

and supplies this waveform to COF(data) Power partSignal part

Lift up lock as shownin narrow.

Pull COF as shown in narrow.

12/40

: make SUSTAIN PULSE and ERASE PULSE that generates

SUSTAIN discharge in panel by receiving LOGIC signal from

CONTROL B/D.

this waveform is supplied to panel through FPC(Z).

*composed with IPM,FET,DIODE, electrolytic capacitor ,E/R coil.

* IPM (Intelligent Power Module)

E/R(Energy recovery)

Separate the fixed Screw of Z-Board.Pull out Lock as shown in arrow.

Condition in Lock part is pulled Pull FPC Connector as shown in arrow.

<FPC Separating>

2. Z sustain B/D

3. Basic

13/40

1) This is a path to supply SUSTAIN ,RESET waveform which made

from Y SUSTAIN B/D to panel through SCAN DRIVER IC.

2) Supply a wave form that select Horizontal electrode (Y SUSTAIN electrode)

sequentially.

- potential difference is 0V between GND and Vpp of DRIVER IC

in SUSTAIN period.

- being generated potential difference between GND and Vpp only

in SCAN period.

* In case of 42” V6 use DRIVER IC IC 8 EA (TOP, BOTTOM: each 4EA)

3. Y drive B/D

3. Basic

14/40

: generates SUSTAIN,RESET waveform, Vsc(SCAN)voltage.

and supplies it Y DRIVER B/D.

* Composed with IPM,DIODE, electrolytic capacitor ,FET.

: creates signal processing (Contour noise,reduction ISM,..)

and an order of many FET on/off of each DRIVER B/D with

R,G,B each 8bit input.

* Use 3.3V/5V 2 kinds of power .

5. Control Board

4. Y sustain B/D

3. Basic

15/40

: Being impressed 5V, Va ,Vs,

DC/DC converter makes

5V,Va,Vs,Vset_up,Vsc

which is essential for each B/D.

There is no DC/DC B/D in

model 40 〞 /42 〞(1 POWER B/D).

* 50 〞 60 〞embedded DC/DC B/D

separately because of high power

consumption.

DC/DC con. part6. DC/DC Converter part

3. Basic

16/40

: supply a driving waveform to PANEL by connecting a PAD electrode of PANEL with PCB(Y and Z).

* there is two type of this for Y B/D. One is single-sided,another is double-side. These are having pattern on it

* for Z B/D, there is no pattern , single-sided, and Betatype(all of copper surface).

: for connecting a Logic signal between B/D and B/D.*There is 0.5mm pitch,50pin type

1mm pitch ,30pin type.

7. FPC (Flexible Printed Circuit)

8. FFC (Flat Flexible Cable)

3. Basic

: supply a waveform which made from X B/D to panel and select

a output pin that is controlled by COF when be on or off.

96 output pin per IC.

the more the resolution higher, the less spare space where

can set IC on it in B/D. without using IC PACKAGE,

we can use a BARE IC , so we can get IC with LOW COST

because we do not solder IC on PCB directly,

a soldering defect rate decrease.

* composition

1) FPC + Heat /Sink

⇒ FPC for COF must have a Low Spec decline with getting damp

2) CHIP resistor + CHIP CAPACITOR

3) BARE IC (STV7610A/WAF) + GOLD WIRE/AL WIRE

4) EPOXY MOLDING

9. COF (Chip On Film)

Bare IC

* 42 V6 COF is the same as 42V5.

3. Basic

18/40

: composition

HEATSINK,CAPACITOR

DIODE

IC LINEAR

RESISTORTANSISTOR,FETS.

: description

Attached at Z B/D and Y B/D, make Sustain waveform.

Sustainer : supply a square wave to panel to make a video.

10. IPM(Intelligent Power Module)

IPM

3. Basic

19/40

4. Trouble shooting.

what kind of defect?Fast check up

Horizontal defect?

vertical defect?

Mis –dischargeon screen?

No display?

defectCheck model No. of module ,all connectors and cables.

Check panel appearance Check PSU output (Va,Vs,5v) Check Y, Z b/dinput voltage

Replace ctrl b/d Replace Y, Z b/d

Check panel appearance Check COF Replace ctrl b/dReplace X b/d

Check FPC Replace Y drv b/d Replace Y sus b/d Replace ctrl b/d

Replace Y drv b/d Replace Y sus b/d Replace ctrl b/d

20/40

what kind of defect?


Horizontal defect?

vertical defect?

Mis –dischargeon screen?

No display?

Logical judgment

What kind of defect ?

Please follow the no display trouble shooting.

Bar defect appeared?

Line defect

Please follow the mis discharge trouble shooting.

Please follow bar defect trouble shooting.

Please follow the line defect trouble shooting.

21/40

Confirm every Connector (PSU, Y-SUS, CTRL, Z-SUS)

⇒ module may not be normal by mis-connection which can not send signal and power.

Also Mis connection for a long time has a specific b/d failed.

1. Connector


No display

CTRL B/D + Y-SUS CTRL B/D + Z-SUS CTRL B/D + X-B/D Signal input(LVDS)

Check each section with following method if there is problem, replace or repair that part.

If not go to the next section.

22/40

Confirm exhausting Tip and find Crack with naked eyes to check vacuum state.

If there is problem replace the module .

⇒ in case of vacuum breakdown, module makes a shaking noise because of inside gas ventilation.

(there may be a small crack which could not see with naked eyes. And this noise is different from Capacitor noise. )

2. Exhaust tip Crack

CRACKEDNORMAL


1. Check each unit part of PSU inside with naked eyes.

(capacitor, FET, a kind of IC, resistor)

2. Check FUSE and SW1 (on Normal).

3. Check Output voltage which is converted from AC V

to DC V.

voltage Check (5V, Va, Vs)

※When PSU Protection occurred. Check Short

between Y-SUS, Z-SUS B/D .

3. PSU(Power Supply Unit)

Fuse open check

SW1 Normal

Multi-meter Touch point(5V, Va ,Vs must accord with Module Label)

Vs Voltage ADJ(Vs : About 180 ~195 V)

Va, 5V(VCC) Voltage ADJ Va : About 55 ~65 V 5V(VCC) : 5V~5.5V)


if not sameConfirm

input voltage

Adjust

voltages

1. Confirm LED D17(flashing) ,13 lighting

2. If not CHECK OSC X1 output.

3. Check CTRL input voltage

(CONNECTOR P300)

4. CHECK 3.3V, 5V,15V.

5. Check IC 11 3.3V

IC 3 2.5V

4. Ctrl B/D


Check oscillating state.

(normal 100 MHZ)

Be careful with physical shock.

Probe

Touching

point

Input voltage

Diode

OSC(X1)

Check IC 11,13

DMM +

DMM – (GND)

25/40

5. Y-sus B/D1. Check FUSE [FS1(5v) ,FS2(Vs)].

2. Check voltages(Vsetup,-Vy, Vscw)

3. Check DIODE between GND and Y SUS output.

[SUSUP(OC2) SUSDN(OC1)].

forward=0.4 ,reverse=OVERLOAD.

4. Check whether output voltages agrees

with voltage that represented in label.

Vsetupsetdn

-Vy

Vscw

setup


FS2

FS1

Normal diode value = OL (reverse)Normal diode value= 0.4 (forward)

Check whether output voltages agrees with voltage that represented in label.


Check diode value GND between Y-SUS output.

6. Z-sus B/D

Va FUSE 6.3A Vs FUSE 2A or 4A

5V FUSE

1. Check the FUSE.

2. Check input voltages.(Va, 5V,15V)

3. Check FPC out put diode value.

4. Check ramp waveform.


Check the FUSE Check input voltages

caution: check certainly after removing FPC.

Normal diode value=OVER LOAD(reverse)

Check FPC output diode value.

Normal diode value=0.375(forward)

Variable resistance of Z RAMP

waveform slope.


29/40

4. Trouble shooting. Power protection

It is power protection when power is off automatically within 2~3 min. from power on.

Power protection function protect the boards when occurred short on circuits of PDP module or power problem.

If can not impress power even after replacing PSU, find out where the short occurred.

UNICON PSUDAEGIL PSU

* PSU makers.

30/40


Vertical defect (bar)

1. ConnectorCheck COF connector.

If not connected well,it will Make a bar defect .

BarCheck here

2. Checking COFConfirm whether COF was torn. And then check input of COF resistor and IC.

TearingCOF 6 is torn partly

Check here Off

Check each section with following method if there is problem, replace or repair that part.

If not go to the next section.

31/40

Checking address COF input of resistor and IC


COF resistor checking

Check the both side of resistor With Digital multi meter(DMM) .

If the resistor is normal, the resistor value will be 10.2 ~ 10.8 Ω

But if not, the value will be 0 or infinity and replace the resistor.

DMM( + terminal)

DMM(- terminal)

DMM (- terminal)

` DMM (+ terminal)

IC input checking

Inside of IC , there is 4 ea diodes which separated in 2 series .

(input 2, output 2)

*how to check

1.contact DMM - terminal to a right terminal of condenser(GND)

and DMM + terminal to a right terminal of IC, normal value 0.66 (fig.1)

2.contact DMM - terminal to Output terminal of resistor, and

DMM + terminal to a right terminal of IC , normal value 0.73 (fig.2)

Fig. 1 Fig. 2

4. Trouble shooting. Checking address COF input of resistor and IC

Buffer IC

MCM

COF IC1 COF IC2 COF IC3 COF IC4

각각 16 line

Array저항

96 output

A flow of address signalIn this figure, we can easily suppose

what will be appeared on screen when a specific part failed.

<Diagram of ctrl b/d>

3. Ctrl B/DCTRL B/D supplies video signal to COF. So if there is a bar defect on screen,

It may be the ctrl b/d problem.


Vertical defect (line)

This phenomenon is due to COF IC inside short or adherence part of the Film and rear panel electrode problem. In this case, replace the panel.


This is MCM of Ctrl b/d defect. MCM can not be replaced separately. So replace the ctrl b/d.

1 line open or short

Line open or short with same distance.

MCM (Multi Chip Module)

1 line open

In case of 1 line open or short , check foreign substances in COF connector.

First blow up foreign substances with your mouth. And then if the same line appears, replace the panel.

1 electrode open

/40

• Case 1: Buffer IC fail

COF IC 1,2 ⇒ 192 line(96+96) open.

COF IC 3,4 ⇒ 64 line open (with fixed interval there is on,off ……. Repetition)

• case 2 : Array resistor fail

COF IC1 ⇒ 16 line , COF IC2 ⇒ 16 line open

• case3 : COF IC fail

96 line open.

line defect from each parts


96 line open

16 line open

Horizontal (bar)


1. ConnectorIt can make a horizontal bar that connector on Y b/d and Z b/d did not plugged well. Because sustain voltage

can not be supplied to panel. So check connectors (FPC, Y drv –Y drv) first.

Most horizontal defects can be repaired. In case of adherence part of the Film and rear panel

electrode defect or panel electrode open,short , replace the panel.

Disconnected

Disconnected Screen off

Horizontal bar

37/40

Normal diode value. (in case of Panasonic IC=1.035)

* It can be different from each IC Maker. (in case of TI IC= 0.6~0.7)

Defect diode value= 0.018

Check diode value of the right side part of output pin.

2. Scan IC check


Check here with DMM(either forward or reverse is ok)DMM + DMM -

38/40


Horizontal (line)

1. Check FPCIn case of horizontal 1 or more line, it is due to FPC or panel inside .

ctrl b/d, Y b/d is just normal.

2. Check scan ICCheck with same method that presented in Horizontal (bar).

FPC electrode open

Panel electrode

Insulation break downHorizontal 1 line.

40/40

Forward : test 1 GND(＋) , Sus-out(－) 2 Sus-out(＋),Vs(－)3 ER-DN(－),ER-COM(＋)4 ER-COM(－),ER-UP(＋)

when each 4 TEST Diode value is over 0.4V => OK

Reverse : test 1 GND(－) , Sus-out(＋) 2 Sus-out(－),Vs(＋)3 ER-DN(＋),ER-COM(－)4 ER-COM(＋),ER-UP(－)

when each 4 nodes TEST Diode value is infinity => OK

※ Specially, the value of ER-UP,COM,DN in the Y/Z board, should be

checked all of them. but, the terminal of Vs,Sus-out,GND,

we must aware to know after check one of IPM because it is parallel.

if no problems, check 15V(Y,Z B/D) with GND, Forward value 0.3V,

Reverse value infinite. If no problems,


How to check IPM


CAUTION General

1) Do not place this product in a location that is subject to heavy vibration, or on an unstable surface such as aninclined surface. The product may fall off or fall over, causing injuries.

2) When moving the product, be sure to turn off the power and disconnect all the cables. While moving theproduct, watch your step. The product may be dropped or fall, leading to injuries of electric shock.

3) Do not place this product in a location that is subject to heavy vibration, or on an unstable surface such as aninclined surface. The product may fall off or fall over, causing injuries.

4) Before disconnecting cable from the product, be sure to turn off the power. Be sure to hold the connector whendisconnecting cables. Pulling a cable with excessive force may cause the core of the cable to be exposed orbreak the cable, and this can lead to fire or electric shock.

5) This product should be moved by two or more persons. If one person attempts to carry this product alone, he/shemay be injured.

6) This product contains glass. The glass may break, causing injuries, if shock, vibration, heat, or distortion isapplied to the product.

7) The temperature of the glass surface of the display may rise to 80°C or more depending on the conditions of use.If you touch the glass inadvertently, you may be burned.

8) Do not poke or strike the glass surface of the display with a hard object. The glass may break or be scratched. Ifthe glass breaks, you may be injured.

9) If you glass surface of the display breaks or is scratched, do not touch the broken pieces or the scratches withbare hands. You may be injured.

10) Do not place an object on the glass surface of the display. The glass may break or be scratched.

IB-He

Rectangle

user

附注


Spare Part List for PDP4210EA

Item

Part Number Part Description Usage / Unit

Unit

1 E6205-001003 42” ED PDP Module 1 Piece

2 900-420103-01B 42” Glass Filter 1 piece 3 E7801-100001 Main PCBA 1 set 4 E7801-100002 Audio PCBA 1 set 5 771S42D101-01 ATSC PCBA 1 set 7 771-42D111-01 Control PCBA 1 set 8 771-42D111-02 IR PCBA 1 set 9 E4101-027001 Power Switch 1 piece 10 E4801-116002 Speaker 2 piece 11 E3301-028005 Speaker Terminal (without cable) 1 piece 12 E3404-157004 AC Power Cord 1 piece 13 E3421-926080 LVDS Cable 1 piece 14 E3421-925049 Connection Cable 1 1 piece 15

E3421-926083 Connection Cable 3 1 piece

16 E3421-926084 Connection Cable 4 1 piece 17 E3421-927001 Power Switch Cable 1 1 piece 18 E3421-927002 Power Switch Cable 2 1 piece 19 E3421-926081 Control PCBA Cable 1 piece 20 E3421-926094 IR PCBA Cable 1 piece 21 E7501-051007 Remote Control 1 set 22 E7301-010002 AAA size Battery 1 pair


Item


Unit

23 200-42D131-MTK02AV Front Plastic Frame 1 piece 24 277-42D101-01S Function Knob 1 piece 25 263-42D101-01S Power Lens 1 piece 26 269-42D101-01L IR Lens 1 piece 27 481-42D107-01S PCBA Shield Box 1 piece 28 483-42D103-01 PCBA Shield Top Cover 1 piece 29 436-42D118-01S Terminal Frame 1 piece 30 402-42D114-01S Metal Back Cover 1 piece 31 423-42D11E-01S Power Switch Metal Frame 1 piece 32 510-42D101-MTU02K Top Carton Box 1 piece 33 511-42D111-01K Bottom Carton Box 1 piece 34 300-42D106-02C Top Cushion 1 piece 35 300-42D105-02C Bottom Cushion 1 piece 36 244-34B811-01 Carton Box Handle 2 piece 37 310-504004-01 Poly bag for Main Unit 1 piece 38 310-111404-07V Poly bag for Instruction Manual 1 piece 39 580-P42AAEM-TU02L Instruction Manual 1 piece 40 388-42SB04-01H Power Socket Plate 1 piece 41 388-42D103-01H Caution Plate 1 piece 42 387-42AA01-MTU02H Model Plate 1 piece 43 388-42SB02-01H Speaker Terminal Plate 1 piece 44 384-42D103-MTU01H Terminal Plate 1 piece 45 590-42AA01-04 Warranty Sheet 1 piece


Item


Unit

46 579-42D102-09 Model Plate Serial Number 1 piece 47 579-42AA01-05 Bar Code Label 1 pair 48 579-42D103-02 ON/OFF Label 1 piece 49 568-P46T02-02 Warning Label 1 piece 50 734-BP0302-01 Duck Feet Stand 1 set

user

附注

“user”设置的“Unmarked”

user

附注

“user”设置的“None”

user

文本框

Exploded View

Using the “Change Password” item When enter the “Parental” menu, select “Change Password”. Press or button to highlight the “Change Password” item. Press Enter button to confirm and pop up a menu.

Use 0~9 buttons input the omnipotence password(8205), then Press Enter button to enter and pop up a menu.

Use 0~9 buttons input your new password. Press button to move to confirm blank. Use 0~9 buttons input your new password again. Press Enter button to confirm

-Suggest: Change to your familiar Password again.

If you forget your V-Chip Password - Omnipotence V-Chip Password: 363200. - Suggest: Change to your familiar Password again.

If you forget your V-Chip Password - Omnipotence V-Chip Password: 8205.

Software upgrade

Process of update MT8205AE

Preparing : 1) Connect RS232-VGA download line, One connector is connected to VGA connect port of Plasma TV while another side is connected to PC COM port. 2) Store the MtkTool into the PC .

Downloading : 3) Turn on AC power and wait TV entering standby mode, while the color of the power indicator is Red. 4) Execute MTKtool and select the chipset as MT8205. (the software of MTKtool will be sent to your side)

5) Select current COM port. (please try to check the COM port of your PC).

6) Choose the bit rate as 115200. 7) Select the update binary by pressing browse button. For exemple,the binary file name is

PDP4210EA_VIORE_XXXXXX_XXXX_VXX.bin. (this update firmware will be sent to your side)

8) Press Upgrade button and start update process.

9) The update process is successful as the progress bar is 100%. After the update process is ok, turn off power and wait indicator light is off. Turn on power and TV can work.

Checking It is needed to check the version of the firmware for MT8205AE which has been

download into the Plasma TV . Press Menu button of the remote control for a little long time and the OSD menu

for Factory Setting is appeared on the screen . Use the remote control and select the mode of the Factory Setting then enter the

mode of the Factory Setting . Use the remote control and select the mode of Firmware Version and then enter the

mode of Firmware Version . It is easy to be found the version of the current firmware for MT8205AE is as the following : “Firmware Version : VXX ”

Process of update MT5351AG

Preparing : 1) Connect RS232-VGA download line, One connector is connected to VGA connect port of Plasma TV while another side is connected to PC COM port. 2) Store the MtkTool into the PC

Downloading : 3) Turn on AC power switch of the Plasma TV and then press the button “standby” of the remote

control . The image could be found on the screen of the Plasma TV while the color of the power indicator is green . (the mode of the Plasma TV will be standby mode if after turn on the main power switch only . )

4) Execute MTKtool and select the chipset as MT5351AG. (the software of MTKtool will be sent to your side)

5) Select current COM port. (please try to check the COM port of your PC).

6) Choose the bit rate as 115200. 7) Select the update binary by pressing browse button. For exemple,the binary file name is

XXXX_PDP4210EA_ATSC_IT_000000XX_X_P.bin. (this update firmware will be sent to your side)

8) Press Upgrade button and start update process.

9) The update process is successful as the progress bar is 100%. After the update process is ok, turn off power and wait indicator light is off. Turn on power and TV can work.

Checking : It is needed to check the version of the firmware for MT5351AG which has been

download into the Plasma TV . Press Menu button of the remote control and the main OSD menu is appeared on

the screen . Use the remote control and select the mode of the adjustment . Use the remote control and select the mode of DTV Entry the mode of DTV Input “0000” (zero , zero , zero , zero) of the remote control while the Plsama TV is

under the above condition . Then enter the mode of factory after input the digits . It is easy to be found the version of the current firmware for MT5351AG is

“XXXX_PDP4210EA_ATSC_IT_000000XX_X_P”under the mode of factory .

235

RXDTXDGND

RXDTXDGND

PC

D-Sub 9(RS232)

1145

PDP

D-Sub 15A(VGA)

RS232-VGA download line

42 service manual - supertvservis.cz · cabinet, on the chassis or picture tube. 3. to avoid a...

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