2/06/2015cmput 229 1 exception handling exceptions (when things go wrong) things that are not...
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04/18/23 CMPUT 229 1
Exception HandlingException Handling Exceptions (when things go wrong)Exceptions (when things go wrong)
Things that are not expectedThings that are not expected Things that are not a part of normal Things that are not a part of normal
operationsoperations Exceptions Exceptions
Multiple threads with controls Multiple threads with controls exchanged frequently exchanged frequently
Based on Chapter 12, Goodman, James and Miller Karen
04/18/23 CMPUT 229 2
Exception handling Exception handling techniquestechniques
What we do if things go wrong?What we do if things go wrong? Send out bad resultsSend out bad results let it crashlet it crash Try to recoverTry to recover
How to shift controls between two How to shift controls between two regular programs?regular programs? All information must be savedAll information must be saved Me able to resume normal execution Me able to resume normal execution
after shiftafter shift
04/18/23 CMPUT 229 3
Exception handlingException handling JavaJava
Two classes for modeling problemsTwo classes for modeling problems• ErrorError• ExceptionException
Exception handlingException handling• Raise an exceptionRaise an exception• Catch an exceptionCatch an exception• Throw an exception Throw an exception
Multiple threads synchronizationMultiple threads synchronization
04/18/23 CMPUT 229 4
CC No forced exception handling No forced exception handling
mechanism mechanism Error noError no Signal handlingSignal handling
• A protocol for two processes to A protocol for two processes to communicate about errors and communicate about errors and exceptionsexceptions
Modules developed for exception Modules developed for exception handlinghandling
Multiple processes and/ threads Multiple processes and/ threads
04/18/23 CMPUT 229 5
Database management systemsDatabase management systems Logs for recording update informationLogs for recording update information Check point for periodically enforcing Check point for periodically enforcing
log writinglog writing Recovery for recovering the database Recovery for recovering the database
into a consistent state after any type into a consistent state after any type of errors and crashof errors and crash
04/18/23 CMPUT 229 6
PollingPolling Has to stop working every once in a while to
see if there is someone in need of attention. Advantages
• Never interrupted in the middle of a task, thus can plan when to stop to check.
Disadvantages• Will stop working several times to check when
there is nobody there.• Someone might have to wait for a while until the
next pooling opportunity to be noticed.
How to detect How to detect exceptions?exceptions?
04/18/23 CMPUT 229 7
InterruptionWhen someone needs attention that person will interrupt the work.
Advantages• Never need to stop working if nobody needs
attention.
DisadvantagesDisadvantages• Will be stopped in the middle of a task. More
difficult to save/restore state (context switching can be expensive).
• Hardware and software must be involvedto provide a context switching mechanism.
How to detect How to detect exceptions?exceptions?
04/18/23 CMPUT 229 8
MIPS ExceptionsMIPS Exceptions
TrapTrap Synchronous exceptions, resulting directly Synchronous exceptions, resulting directly
from the execution of the program, such asfrom the execution of the program, such as• Arithmetic overflowArithmetic overflow• Out of bond memory accessOut of bond memory access
InterruptionInterruption Asynchronous exceptions, resulting from Asynchronous exceptions, resulting from
external events, such as external events, such as • IO requestIO request• Control shiftControl shift
04/18/23 CMPUT 229 9
The MIPS Exception The MIPS Exception MechanismMechanism
A MIPS processor operates in one of two modes: kernel and user.( Kernel can be viewed as the exception handler of the operating system)
When running in the kernel mode, a program has access to anadditional set of registers that are not accessible to a programrunning in the user mode.
Memory locations in the upper half of the address space, i.e.memory locations whose most significant bit is 1, can only beaccessed in the kernel mode.
This region include:- Exception handler code- Data that is only accessible by the operating system- Memory-mapped I/O addresses
04/18/23 CMPUT 229 10
Co-processor C0Co-processor C0
Co-processor C0 only canbe accessed when executingin the kernel mode.
The registers of coprocessor C0 are accessed, when executing in the kernel mode,through the instructionsmtc0 and mfc0
Exception Program Counter
04/18/23 CMPUT 229 11
CP0 RegistersCP0 Registers
Register Name Reg. NumberContext 4BadVAddr (Bad Virtual Address) 8Count 9Compare register 11Status 12Cause 13EPC (Exception Program Counter) 14WatchLo (Mem. Ref. Trap Addr. Low) 18WatchHi (Mem. Ref. Trap Addr. High) 19Xcontext 20ECC 26CacheErr (Cache Error Status) 27ErrorEPC (Erroe Except. Prog. Counter) 30
04/18/23 CMPUT 229 12
The Cause RegisterThe Cause Register
0ExcCode0IP(1) IP(0)IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) 0CE0BD 0•••0
31 30 29 28 27 16 9 8 7 6 5 4 3 2 1101112131415 0
04/18/23 CMPUT 229 13
The Cause RegisterThe Cause Register
0ExcCode0IP(1) IP(0)IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) 0CE0BD 0•••0
31 30 29 28 27 16 9 8 7 6 5 4 3 2 1101112131415 0
Exception Mnemonic Meaning Code 0 Int Interruption 1-3 TLB exceptions 4 AdEL Address error exception (load) 5 AdES Address error exception (store) 6 IBE Bus error on instruction fetch 7 DBE Bus error on data reference 8 Sys Syscall instruction 9 Break Break instruction 10 RI Reserved 11 CpU Co-processor unusable 12 Ov Arithmetic overflow 13 Tr Trap Exception 15 FPE Floating Point Exception 16-31 (future use)
04/18/23 CMPUT 229 14
The Cause RegisterThe Cause Register
0ExcCode0IP(1) IP(0)IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) 0CE0BD 0•••0
31 30 29 28 27 16 9 8 7 6 5 4 3 2 1101112131415 0
ExternalInterrupts
SoftwareInterrupts
04/18/23 CMPUT 229 15
The Status RegisterThe Status Register
CU
31-28
•••
24-16
IM(1) IM(0)
9 8
•••
7-6
KUo
5
IM(7) IM(6) IM(5) IM(4) IM(3) IM(2)
101112131415
ExternalInterrupts
SoftwareInterrupts
IEo
4
PUp
3
IEp
2
KUc
1
IEc
0
RP
27
FR
26
RE
25
04/18/23 CMPUT 229 16
The Status RegisterThe Status Register
KUc: Is the program running in kernel mode or user mode?PUp: Was the processor in kernel or user mode when the last exception occurred? IM(0)-IM(7): Interrupt Mask. It controls which interrupts are enabled.RE: Reverse-Endian (RE) bit. Reverses the endianess of the machine.FR: Enables additional floating point registersCU: 4 bits to control co-processor usability
CU
31-28
•••
24-16
IM(1) IM(0)
9 8
•••
7-6
KUo
5
IM(7) IM(6) IM(5) IM(4) IM(3) IM(2)
101112131415
ExternalInterrupts
SoftwareInterrupts
IEo
4
PUp
3
IEp
2
KUc
1
IEc
0
RP
27
FR
26
RE
25
04/18/23 CMPUT 229 17
The Status RegisterThe Status Register
KUc: Is the program running in kernel mode or user mode?PUp: Was the processor in kernel or user mode when the last exception occurred? IM(0)-IM(7): Interrupt Mask. It controls which interrupts are enabled.RE: Reverse-Endian (RE) bit. Reverses the endianess of the machine.FR: Enables additional floating point registersCU: 4 bits to control co-processor usability
CU
31-28
•••
24-16
IM(1) IM(0)
9 8
•••
7-6
KUo
5
IM(7) IM(6) IM(5) IM(4) IM(3) IM(2)
101112131415
ExternalInterrupts
SoftwareInterrupts
IEo
4
PUp
3
IEp
2
KUc
1
IEc
0
RP
27
FR
26
RE
25
04/18/23 CMPUT 229 18
The Status RegisterThe Status Register
KUc: Is the program running in kernel mode or user mode?PUp: Was the processor in kernel or user mode when the last exception occurred? IM(0)-IM(7): Interrupt Mask. It controls which interrupts are enabled.RE: Reverse-Endian (RE) bit. Reverses the endianess of the machine.FR: Enables additional floating point registersCU: 4 bits to control co-processor usability
CU
31-28
•••
24-16
IM(1) IM(0)
9 8
•••
7-6
KUo
5
IM(7) IM(6) IM(5) IM(4) IM(3) IM(2)
101112131415
ExternalInterrupts
SoftwareInterrupts
IEo
4
PUp
3
IEp
2
KUc
1
IEc
0
RP
27
FR
26
RE
25
04/18/23 CMPUT 229 19
The Status RegisterThe Status Register
KUc: Is the program running in kernel mode or user mode?PUp: Was the processor in kernel or user mode when the last exception occurred? IM(0)-IM(7): Interrupt Mask. It controls which interrupts are enabled.RE: Reverse-Endian (RE) bit. Reverses the endianess of the machine.FR: Enables additional floating point registersCU: 4 bits to control co-processor usability
CU
31-28
•••
24-16
IM(1) IM(0)
9 8
•••
7-6
KUo
5
IM(7) IM(6) IM(5) IM(4) IM(3) IM(2)
101112131415
ExternalInterrupts
SoftwareInterrupts
IEo
4
PUp
3
IEp
2
KUc
1
IEc
0
RP
27
FR
26
RE
25
04/18/23 CMPUT 229 20
The Status RegisterThe Status Register
KUc: Is the program running in kernel mode or user mode?PUp: Was the processor in kernel or user mode when the last exception occurred? IM(0)-IM(7): Interrupt Mask. It controls which interrupts are enabled.RE: Reverse-Endian (RE) bit. Reverses the endianess of the machine.FR: Enables additional floating point registersCU: 4 bits to control co-processor usability
CU
31-28
•••
24-16
IM(1) IM(0)
9 8
•••
7-6
KUo
5
IM(7) IM(6) IM(5) IM(4) IM(3) IM(2)
101112131415
ExternalInterrupts
SoftwareInterrupts
IEo
4
PUp
3
IEp
2
KUc
1
IEc
0
RP
27
FR
26
RE
25
04/18/23 CMPUT 229 21
The Status RegisterThe Status Register
KUc: Is the program running in kernel mode or user mode?PUp: Was the processor in kernel or user mode when the last exception occurred? IM(0)-IM(7): Interrupt Mask. It controls which interrupts are enabled.RE: Reverse-Endian (RE) bit. Reverses the endianess of the machine.FR: Enables additional floating point registersRP: Enables reduced-power operation (reduce clock freq.)CU: 4 bits to control co-processor usability
CU
31-28
•••
24-16
IM(1) IM(0)
9 8
•••
7-6
KUo
5
IM(7) IM(6) IM(5) IM(4) IM(3) IM(2)
101112131415
ExternalInterrupts
SoftwareInterrupts
IEo
4
PUp
3
IEp
2
KUc
1
IEc
0
RP
27
FR
26
RE
25
04/18/23 CMPUT 229 22
The Status RegisterThe Status Register
KUc: Is the program running in kernel mode or user mode?PUp: Was the processor in kernel or user mode when the last exception occurred? IM(0)-IM(7): Interrupt Mask. It controls which interrupts are enabled.RE: Reverse-Endian (RE) bit. Reverses the endianess of the machine.FR: Enables additional floating point registersRP: Enables reduced-power operation (reduce clock freq.)CU: 4 bits to control co-processor usability
CU
31-28
•••
24-16
IM(1) IM(0)
9 8
•••
7-6
KUo
5
IM(7) IM(6) IM(5) IM(4) IM(3) IM(2)
101112131415
ExternalInterrupts
SoftwareInterrupts
IEo
4
PUp
3
IEp
2
KUc
1
IEc
0
RP
27
FR
26
RE
25
04/18/23 CMPUT 229 23
Invocation and Return Invocation and Return from the Exception from the Exception
HandlerHandler
The MIPS architecture fix a single address --- 0x8000 0080 --- to bethe starting address of the exception handler.
When an exception is invoked, control is transferred to this location.
The exception invocation must also save the returning address forthe exception. But it cannot save this address in $ra, because $ra contains the returning address for the routine that is currently executing.
The Exception Program Counter (EPC) is loaded with the address atwhich processing resumes after an exception is serviced.
The (EPC) is a register of the co-processor C0. The content of theEPC can be transferred to a general register using the instruction:
mfc0 $ri, $14
04/18/23 CMPUT 229 24
Exception HandlingException Handling
HandleInterrupt
HandleSyscall
HandleOverflow
Restore registers
ExecCode?
Save registers
Load Cause Register
Load EPC into $k0
Clean Up State
Return
04/18/23 CMPUT 229 25
$k0 = bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb
0x7c = 0000 0000 0000 0000 0000 0000 0111 1100
$k0 = 0000 0000 0000 0000 0000 0000 0bbb bb00
AND
0ExcCode0IP(1) IP(0)IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) 0CE0BD 0•••0
31 30 29 28 27 16 9 8 7 6 5 4 3 2 1101112131415 0
Examining the Exception Examining the Exception CodeCode
Exception Handler:<preliminary check for reentrance>
OK: <set flag><save registers>mfc0 $k0, $13 # Get the Cause Registerandi $k0, $k0, $0x7c # Mask out the ExcCode bitslw $k0, JumpTable($k0) # Read address from jump tablejr $k0 # Jump to exception handler
04/18/23 CMPUT 229 26
Exception Handler:<preliminary check for reentrance>
OK: <set flag><save registers>mfc0 $k0, $13 # Get the Cause Registerandi $k0, $k0, $0x7c # Mask out the ExcCode bitslw $k0, JumpTable($k0) # Read address from jump tablejr $k0 # Jump to exception handler
Examining the Exception Examining the Exception CodeCode
Return: <restore registers><clear flag>mfc0 $k0, $14 # Get EPC registerrfe # clean up state registerjr $k0 # return to the address in EPC
04/18/23 CMPUT 229 27
Building the Jump Table Building the Jump Table (The Cause Register)(The Cause Register)
0ExcCode0IP(1) IP(0)IP(7) IP(6) IP(5) IP(4) IP(3) IP(2) 0CE0BD 0•••0
31 30 29 28 27 16 9 8 7 6 5 4 3 2 1101112131415 0
Exception Mnemonic Meaning Code 0 Int Interruption 1-3 TLB exceptions 4 AdEL Address error exception (load) 5 AdES Address error exception (store) 6 IBE Bus error on instruction fetch 7 DBE Bus error on data reference 8 Sys Syscall instruction 9 Break Break instruction 10 CpU Co-processor unusable 12 Ov Arithmetic overflow 13 Tr Trap Exception 15 FPE Floating Point Exception 16-31 (future use)
04/18/23 CMPUT 229 28
Exception Handler:JumpTable:
.word HandleInt # Interrupt
.word HandleMOD # TLB modification exception
.word HandleTLBL # TLB miss exception (load or fetch)
.word HandleTLBS # TLB miss exception (store)
.word HandleAdEL # Address error exception (load or fetch)
.word HandleAdES # Address error exception (store)
.word HandleIBE # Bus error exception (for a fetch)
.word HandleDBE # Bus error exception (for a load or store)
.word HandleSys # Syscall exception
.word HandleBp # Breakpoint exception
.word HandleRI # Reserved Instruction Exception
.word HandleCpU # Co-processor Unusable exception
.word HandleOvf # Arithmetic overflow exception
.word HandleFPInexact # Inexact floating point result
.word HandleDivideBy0 # Divide by 0
.word HandleFPOvf # FP Overflow
.word HandleFPUnder # FP Underflow
.word HandleRes, HandleRes, HandleRes, HandleRes
.word HandleRes, HandleRes, HandleRes, HandleRes
.word HandleRes, HandleRes, HandleRes, HandleRes
.word HandleRes, HandleRes, HandleRes, HandleRes
Building the Jump TableBuilding the Jump Table
04/18/23 CMPUT 229 29
The Syscall HandleThe Syscall Handle
In order to obtain one of this services, the user’s program must pass the following codes in $v0:
$v0 syscall service 12 getc 11 putc 10 exit 4 puts
We assume that the value of $v0 was saved at the beginning ofthe exception service in the memory location tmpv0
In this example of exception handling, lets assume that we want to handle the following syscall functions: putc, puts, exit, and getc.
04/18/23 CMPUT 229 30
The Syscall HandleThe Syscall Handle
Exception Handler:HandleSys:
mfc0 $k1, $14 # Get the EPC Registeraddi $k1, $k1, 4 # Increment PC past syscall instructionmtc0 $k1, $14 # Set the EPC Register
lw $v0, tmpv0 # get the previously saved value of $v0li $a0, 11 # Is it putc?beq $v0, $a0, Putcli $a0, 4 # Is it puts?beq $v0, $a0, Putsli $a0, 12 # Is it getc?beq $v0, $a0, Getcli $a0, 10 # Is it exit?beq $v0, $a0, Exit
la $a0, SysMessage # Bad number in $v0jal Print String # Print messagej Return
04/18/23 CMPUT 229 31
The Syscall HandleThe Syscall Handle
Exception Handler:Exit: <code for Exit>
Putc: <code for Putc>
Puts: <code for Putc>
Getc: <code for Getc>
04/18/23 CMPUT 229 32
Checking for ReentranceChecking for Reentrance
Exception Handler:flag: .word 0 # remembers if it was already in the
# exception handler when the exception# occurred
BadReentry:.asciiz “Bad re-entry into kernel\nHalting\n”.ktext.space 0x80 # skip space so that the handler is at 0x80000080add $k1, $at, $zero # immediately save $atlw $k0, flag # SPIM translates this instruction to:
# lui $at, 4097# lw $k0, 0($at)
beq $k0, $zero, OKla $a0, BadReentryj Panic
OK: <set flag><save registers>mfc0 $k0, $13 # Get the Cause Registerandi $k0, $k0, 0x7c # Mask out the ExcCode bitslw $k0, JumpTable($k0) # Read address from jump tablejr $k0 # Jump to exception handler
04/18/23 CMPUT 229 33
Code for PanicCode for Panic
The code for Panic has to print the following message:
Panic: Bad re-entry into kernel\nHalting\n
04/18/23 CMPUT 229 34
PanicPanicException Handler:
DisplayData = 0xbfff0008DisplayStatus = 0xbfff000c.kdata
Pmess: .asciiz “Panic: “.ktext # Panic prints a message and quits
Panic: la $a1, PmessPRead1: lb $a2, ($a1) # read letter to print
beq $a2, $zero, PRead2 # done when we find a nullPWait1: lw $a3, DisplayStatus # Read the status of the display
bge $a3,$zero, PWait1 # keep reading until it is readysw $a2, DisplayData # output characteraddi $a1, $a1, 1 # advance characterj PRead1
PRead2: lb $a2, ($a0) # Print message pointed by $a0beq $a2, $zero, Pcontinue # done when we find a null
PWait2: lw $a3, DisplayStatus # Read the status of the displaybge $a3, $zero, PWait2 # keep reading until it is readysw $a2, DisplayData # output characteraddi $a0, $a0, 1 # advance characterj PRead2
Pcontinue: li $v0, 0 # clear re-entrance flagsw $v0, flagli $v0, 13 # the quit_now syscallsyscall
04/18/23 CMPUT 229 35
Save/Restore RegistersSave/Restore RegistersException Handler:
<preliminary check for reentrance>OK: <set flag>
<save registers>mfc0 $k0, $13 # Get the Cause Registerandi $k0, $k0, $0x7c # Mask out the ExcCode bitslw $k0, JumpTable($k0) # Read address from jump tablejr $k0 # Jump to exception handler
Return: <restore registers><clear flag>mfc0 $k0, $14 # Get EPC registerrfe # clean up state registerjr $k0 # return to the address in EPC
.kdatatmpat: .word 0tmpv0: .word 0tmpa0: .word 0tmpa1: .word 0tmpa2: .word 0tmpa3: .word 0tmpra: .word 0
04/18/23 CMPUT 229 36
Save/Restore RegistersSave/Restore Registers
# code to save registerssw $k1, tmpatsw $v0, tmpv0sw $a0, tmpa0sw $a1, tmpa1sw $a2, tmpa2sw $a3, tmpa3sw $ra, tmpra
# code to restore registerslw $v0, tmpv0lw $a0, tmpa0lw $a1, tmpa1lw $a2, tmpa2lw $a3, tmpa3lw $ra, tmprasw $zero, flag # clear re-entry flaglw $k1, tmpat # restore $atadd $at, $k1, $zeromfc0 $k0, $14 # Get EPC registerrfe # clean up state registerjr $k0 # return to the address in EPC
.kdatatmpat: .word 0tmpv0: .word 0tmpa0: .word 0tmpa1: .word 0tmpa2: .word 0tmpa3: .word 0tmpra: .word 0
04/18/23 CMPUT 229 37
Code for PutcCode for PutcException Handler:
.kdatatmpputra: .word 0
.ktextPutc: lw $a0, tmpa0
jal Puta0j Return
Puta0: lw $k0, pqhead # load head of put queuelw $k1, pqtail # load tail of put queueaddi $k1, 1 # increment tailandi $k1, $k1, 0x00ff # module counterbeq $k1, $k0, Full # try to print a charn if queue is fullsb $a0, putqueue($k1) # add byte to the queuesw $k1, pqtail # save new tailmfc0 $k1, $12 # Get status registerori $k1, 0x5000 # Turn on display interruptsmtc0 $k1, $12 # Set status registersw $ra, tmpputra # Save return addressjal DP_handler # try to printlw $ra, tmpputra # Restore return addressjr $ra
Full: sw $ra, tmpputra # Save return addressjal DP_handler # Try to printlw $ra, tmpputra # Restore return addressj Puta0
04/18/23 CMPUT 229 38
Code for DP_handlerCode for DP_handler
Exception Handler:.kdata
putqueue: .space 256.align 2.ktext
pqtail: .word 0pqhead: .word 0
.ktextDP_handler:
lw $k0, DisplayStatus # Get display status wordbge $k0, $zero, DPRet # Return if it is not Readylw $k0, pqhead # lw $k1, pqtailbeq $k0, $k1, DPRet # Return if put queue is emptyaddi $k0, $k0, 1 # Increment headandi $k0, $k0, 0x00ff # Module countersw $k0, pqhead # Save new headlb $k0, putqueue($k0) # get character from put queuesb $k0, DisplayData # Send character to display
DPRet: jr $ra # Return to caller
04/18/23 CMPUT 229 39
Code for PutsCode for Puts
Exception Handler:.kdata
tmpputsra: .word 0Puts: lw $k0, tmpa0 # Get address of first characterPutsLoop: lbu $a0, ($k0) # Get a character
beq $a0, $zero, PutsRet # If character is null, we are donesw $ra, tmpputsra # Save return addressjal Puta0 # Print the charactersw $ra, tmpputsra # Save return addressaddi $k0, $k0, 1 # Move pointer to next characterj PutsLoop # Loop back
PutsRet: jr $ra
04/18/23 CMPUT 229 40
Bad Virtual Address Bad Virtual Address RegisterRegister
The register $8 of the coprocessor 0 is the BadVAddr (Bad Virtual Address)register. It is a read only address register that contains the most recentvirtual address that caused one of the following exceptions:
TLB InvalidTLB ModifiedTLB RefillVirtual Coherency Data AccessVirtual Coherency Instruction Fetch
The BadVAddr does not save any information for bus errors, since bus errors are not addressing errors.