1gb parallel nor flash - micross components ecommerce system · 8 read and auto select ... internal...

MYX28F00AM29EWHRevision 1.0 - 11/14/2014

*Advanced information. Subject to change without notice.

1

1Gb Parallel NOR FlashMYX28F00AM29EWH*

Form #: CSI-D-685 Document 003

1Gb - 64M x 16 Parallel NOR Flash Embedded Memory

Features

• TinLeadBallmetallurgySn63Pb37

• Supplyvoltage

� VCC=2.7–3.6V(program,erase,read)

� VCCQ=1.65–VCC(I/Obuffers)

• Asynchronousrandom/pageread

� Pagesize:16wordsor32bytes

� Pageaccess:25ns

� Randomaccess:100ns(FortifiedBGA)

• Bufferprogram:512-wordprogrambuffer

• Programtime

� 0.88μsperbyte(1.14MB/s)TYPwhenusingfull512-wordbuffersizeinbufferprogram

• Memoryorganization

� Uniformblocks:128-Kbytesor64-Kwordseach

• Program/erasecontroller

� Embeddedbyte(x8)/word(x16)programalgorithms

• Program/erasesuspendandresumecapability

� ReadfromanotherblockduringaPROGRAMSUSPENDoperation

� ReadorprogramanotherblockduringanERASESUSPENDoperation

• BLANKCHECKoperationtoverifyanerasedblock

• Unlockbypass,blockerase,chiperase,andwritetobuffercapability

� Fastbuffered/batchprogramming

� Fastblock/chiperase

• VPP/WP#pinprotection

• Protectsfirstorlastblockregardlessofblockprotectionsettings

Options Marking

• Configuration

� 64Megx16 00A

• FBGApackage(Sn63/Pb37) BG

� 64-ballFBGA(13mmx11mm) PC

• Operatingtemperature

� Industrial(–40°C≤TC≤+85°C) IT

• Softwareprotection

� Volatileprotection

� Nonvolatileprotection

� Passwordprotection

� Passwordaccess

• Extendedmemoryblock

� 128-word(256-byte)blockforpermanent,secureidentification

� Programmedorlockedatthefactoryorbythecustomer

• Lowpowerconsumption:Standbymode

• JESD47-compliant

� 100,000minimumERASEcyclesperblock

� Dataretention:20years(TYP)

• 65nmmultilevelcell(MLC)processtechnology

• Greenpackage(Halogen-free)



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Contents

1 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .3

2 Signal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

3 Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5

4 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . .64.1 MemoryConfiguration . . . . . . . . . . . . . . . . . . . . . . . . . 6

5 Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75.1 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5.2 Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.3 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.4 OutputDisable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

5.5 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

6 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96.1 DataPollingRegister . . . . . . . . . . . . . . . . . . . . . . . . . . 9

6.2 LockRegister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

7 StandardCommandDefinitions Address-Data Cycles . . . . . . . . . . . . . . . . . . . . . . . . . .12

8 READ and AUTO SELECT Operations . . . . . . . . . . . . . . .148.1 READ/RESETCommand . . . . . . . . . . . . . . . . . . . . . . . 14

8.2 READCFICommand . . . . . . . . . . . . . . . . . . . . . . . . . 14

8.3 AUTOSELECTCommand . . . . . . . . . . . . . . . . . . . . . . 15

9 Bypass Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . .159.1 UNLOCKBYPASSCommand . . . . . . . . . . . . . . . . . . . . 15

9.2 UNLOCKBYPASSRESETCommand . . . . . . . . . . . . . . 16

10 Program Operations . . . . . . . . . . . . . . . . . . . . . . . . . . .1610.1 PROGRAMCommand . . . . . . . . . . . . . . . . . . . . . . . . . 16

10.2 UNLOCKBYPASSPROGRAMCommand . . . . . . . . . . . 16

10.3 WRITETOBUFFERPROGRAMCommand . . . . . . . . . . 16

10.4 UNLOCKBYPASSWRITETOBUFFERPROGRAM Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

10.5 WRITETOBUFFERPROGRAMCONFIRMCommand . . . 17

10.6 BUFFEREDPROGRAMABORTANDRESETCommand . . 17

10.7 PROGRAMSUSPENDCommand . . . . . . . . . . . . . . . . . 17

10.8 PROGRAMRESUMECommand . . . . . . . . . . . . . . . . . . 18

11 Erase Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1811.1 CHIPERASECommand . . . . . . . . . . . . . . . . . . . . . . . 18

11.2 UNLOCKBYPASSCHIPERASECommand . . . . . . . . . . 18

11.3 BLOCKERASECommand . . . . . . . . . . . . . . . . . . . . . . 18

11.4 UNLOCKBYPASSBLOCKERASECommand . . . . . . . . . 18

11.5 ERASESUSPENDCommand . . . . . . . . . . . . . . . . . . . . 19

11.6 ERASERESUMECommand . . . . . . . . . . . . . . . . . . . . . 19

12 BLANK CHECK Operation . . . . . . . . . . . . . . . . . . . . . . . .1912.1 BLANKCHECKCommands . . . . . . . . . . . . . . . . . . . . . 19

13 BlockProtectionCommandDefinitions Address-Data Cycles . . . . . . . . . . . . . . . . . . . . . . . . . .20

14 Protection Operations . . . . . . . . . . . . . . . . . . . . . . . . . .2214.1 LOCKREGISTERCommands . . . . . . . . . . . . . . . . . . . . 23

14.2 PASSWORDPROTECTIONCommands . . . . . . . . . . . . . 23

14.3 NONVOLATILEPROTECTIONCommands . . . . . . . . . . . 23

14.4 NONVOLATILEPROTECTIONBITLOCKBITCommands . 24

14.5 VOLATILEPROTECTIONCommands . . . . . . . . . . . . . . 24

14.6 EXTENDEDMEMORYBLOCKCommands . . . . . . . . . . . 24

14.7 EXITPROTECTIONCommand . . . . . . . . . . . . . . . . . . . 24

15 Device Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2515.1 HardwareProtection . . . . . . . . . . . . . . . . . . . . . . . . . 25

15.2 SoftwareProtection . . . . . . . . . . . . . . . . . . . . . . . . . . 25

15.3 VolatileProtectionMode . . . . . . . . . . . . . . . . . . . . . . . 26

15.4 NonvolatileProtectionMode . . . . . . . . . . . . . . . . . . . . 26

15.5 PasswordProtectionMode . . . . . . . . . . . . . . . . . . . . . 27

15.6 PasswordAccess . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

16 Common Flash Interface . . . . . . . . . . . . . . . . . . . . . . . .27

17 Power-Up and Reset Characteristics . . . . . . . . . . . . . .28

18 Absolute Ratings and Operating Conditions . . . . . . . .30

19 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .32

20 Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .34

21 Write AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .37

22 Accelerated Program, Data Polling/Toggle AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

23 Program/Erase Characteristics . . . . . . . . . . . . . . . . . .48

24 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . .49

25 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . .50



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1 General Description

The device is an asynchronous, uniform block, parallel NOR Flash memory device. READ, ERASE, andPROGRAMoperationsareperformedusingasinglelow-voltagesupply.Uponpower-up,thedevicedefaultstoreadarraymode.

Themainmemoryarray isdivided intouniformblocks thatcanbeerased independentlyso thatvaliddatacanbepreservedwhileolddataispurged.PROGRAMandERASEcommandsarewrittentothecommandinterfaceofthememory.Anon-chipprogram/erasecontrollersimplifiestheprocessofprogrammingorerasingthememorybytakingcareofallspecialoperationsrequiredtoupdatethememorycontents.TheendofaPROGRAMorERASEoperationcanbedetectedandanyerrorconditioncanbeidentified.ThecommandsetrequiredtocontrolthedeviceisconsistentwithJEDECstandards.

CE#, OE#, and WE# control the bus operation of the device and enable a simple connection to mostmicroprocessors,oftenwithoutadditionallogic.

Thedevicesupportsasynchronousrandomreadandpagereadfromallblocksofthearray.Italsofeaturesaninternalprogrambufferthatimprovesthroughputbyprogramming512wordsviaonecommandsequence.A128-wordextendedmemoryblockoverlapsaddresseswitharrayblock0.Userscanprogramthisadditionalspace and thenprotect it to permanently secure the contents. Thedevice also features different levels ofhardwareandsoftwareprotectiontosecureblocksfromunwantedmodification.

Figure 1: Logic Diagram

General DescriptionThe device is an asynchronous, uniform block, parallel NOR Flash memory device.READ, ERASE, and PROGRAM operations are performed using a single low-voltage sup-ply. Upon power-up, the device defaults to read array mode.

The main memory array is divided into uniform blocks that can be erased independent-ly so that valid data can be preserved while old data is purged. PROGRAM and ERASEcommands are written to the command interface of the memory. An on-chip program/erase controller simplifies the process of programming or erasing the memory by takingcare of all special operations required to update the memory contents. The end of aPROGRAM or ERASE operation can be detected and any error condition can be identi-fied. The command set required to control the device is consistent with JEDEC stand-ards.

CE#, OE#, and WE# control the bus operation of the device and enable a simple con-nection to most microprocessors, often without additional logic.

The device supports asynchronous random read and page read from all blocks of thearray. It also features an internal program buffer that improves throughput by program-ming 512 words via one command sequence. A 128-word extended memory block over-laps addresses with array block 0. Users can program this additional space and thenprotect it to permanently secure the contents. The device also features different levels ofhardware and software protection to secure blocks from unwanted modification.

Refer to TN-13-30, System Design Considerations with Micron Flash Memory, for de-tails on system design and VCC and VCCQ signals.

Figure 1: Logic Diagram

VCC VCCQ

A[MAX:0]

WE#

VPP/WP#

DQ[14:0]

DQ15/A-1

VSS

15

CE#

OE#

RST#

BYTE#

RY/BY#

256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR FlashGeneral Description

PDF: 09005aef849b4b09m29ew_256mb_2gb.pdf - Rev. C 9/14 EN 8 Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 2012 Micron Technology, Inc. All rights reserved.



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2 Signal Assignments

Figure 2: 64-Ball Fortified BGAFigure 5: 64-Ball Fortified BGA

A

B

C

D

E

F

G

H

1

RFU

A26

RFU

RFU

RFU

VCCQ

RFU

RFU

2

A3

A4

A2

A1

A0

CE#

OE#

VSS

3

A7

A17

A6

A5

D0

D8

D9

D1

4

RY/BY#

VPP/WP#

A18

A20

D2

D10

D11

D3

5

WE#

RST#

A21

A19

D5

D12

VCC

D4

6

A9

A8

A10

A11

D7

D14

D13

D6

7

A13

A12

A14

A15

A16

BYTE#

D15/A-1

VSS

8

RFU

A22

A23

VCCQ

VSS

A24

A25

RFU

Top view – ball side down

Notes: 1. A-1 is the least significant address bit in x8 mode.2. A23 is valid for 256Mb and above; otherwise, it is RFU.3. A24 is valid for 512Mb and above; otherwise, it is RFU.4. A25 is valid for 1Gb and above; otherwise, it is RFU.5. A26 is valid for 2Gb only; otherwise it is RFU.

256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR FlashSignal Assignments



Notes:

1. A-1istheleastsignificantaddressbitinx8mode.

2. A25isvalidfor1Gbandabove;otherwise,itisRFU.

3. A26isvalidfor2Gbonly;otherwiseitisRFU.



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3 Signal Descriptions

Thesignaldescriptiontablebelowisacomprehensivelistofsignalsforthisdevicefamily.Allsignalslistedmaynotbesupportedonthisdevice.SeeSignalAssignmentsforinformationspecifictothisdevice.

Table 1: Signal Descriptions

Name Type Description

A[MAX:0] InputAddress:SelectsthecellsinthearraytoaccessduringREADoperations.DuringWRITEoperations,theycontrolthecommandssenttothecommandinterfaceoftheprogram/erasecontroller.

CE# InputChip enable:Activatesthedevice,enablingREADandWRITEoperationstobeperformed.WhenCE#isHIGH,thedevicegoestostandbyanddataoutputsareHigh-Z.

OE# Input Output enable:ActiveLOWinput.OE#LOWenablesthedataoutputbuffersduringREADcycles.WhenOE#isHIGH,dataoutputsareHigh-Z.

WE# Input Write enable:ControlsWRITEoperationstothedevice.AddressislatchedonthefallingedgeofWE#anddataislatchedontherisingedge.

VPP/WP# InputVPP/Write Protect:ProvidesWRITEPROTECTfunctionandVPPHfunction.Thesefunctionsprotectthelowestorhighestblockandenablethedevicetoenterunlockbypassmode,respectively.(RefertoHardwareProtectionandBypassOperationsfordetails.)

BYTE# InputByte/word organization select:Switchesbetweenx8andx16busmodes.WhenBYTE#isLOW,thedeviceisinx8mode;whenHIGH,thedeviceisinx16mode.Underbyteconfiguration,BYTE#shouldnotbetoggledduringanyWRITEoperation.Caution:Thispincannotbefloated.

RST# InputReset:Appliesahardwareresettothedevicecontrollogicandplacesitinstandby,whichisachievedbyholdingRST#LOWforatleasttPLPH.AfterRST#goesHIGH,thedeviceisreadyforREADandWRITEoperations(aftertPHELortPHWL,whicheveroccurslast).

DQ[7:0] I/OData I/O:OutputsthedatastoredattheselectedaddressduringaREADoperation.DuringWRITEoperations,theyrepresentthecommandssenttothecommandinterfaceoftheinternalstatemachine.

DQ[14:8] I/OData I/O:OutputsthedatastoredattheselectedaddressduringaREADoperationwhenBYTE#isHIGH.WhenBYTE#isLOW,thesepinsarenotusedandareHigh-Z.DuringWRITEoperations,thesebitsarenotused.Whenreadingthedatapollingregister,thesebitsshouldbeignored.

DQ15/A-1 I/OData I/O or address input:Whenthedeviceoperatesinx16busmode,thispinbehavesasdataI/O,togetherwithDQ[14:8].Whenthedeviceoperatesinx8busmode,thispinbehavesastheleastsignificantbitoftheaddress.Exceptwherestatedexplicitlyotherwise,DQ15=dataI/O(x16mode);A-1=addressinput(x8mode).

RY/BY# Output

Ready busy:Open-drainoutputthatcanbeusedtoidentifywhenthedeviceisperformingaPROGRAMorERASEoperation.DuringPROGRAMorERASEoperations,RY/BY#isLOW,andisHigh-Zduringreadmode,autoselectmode,anderasesuspendmode.Theuseofanopen-drainoutputenablestheRY/BY#pinsfromseveraldevicestobeconnectedtoasinglepull-upresistortoVCCQ.Alowvaluewillthenindicatethatone(ormore)ofthedevicesis(are)busy.A10KOhmorbiggerresistorisrecommendedaspull-upresistortoachieve0.1VVOL.

VCC Supply

Supply voltage:ProvidesthepowersupplyforREAD,PROGRAM,andERASEoperations.ThedeviceisdisabledwhenVCC ≤ VLKO.Iftheprogram/erasecontrollerisprogrammingorerasingduringthistime,thentheoperationabortsandthecontentsbeingalteredwillbeinvalid. A0.1μFand0.01μFcapacitorshouldbeconnectedbetweenVCCandVSStodecouplethecurrentsurgesfromthepowersupply.ThePCBtrackwidthsmustbesufficienttocarrythecurrentsrequiredduringPROGRAMandERASEoperations(seeDCCharacteristics).

VCCQ SupplyI/O supply voltage:ProvidesthepowersupplytotheI/OpinsandenablesalloutputstobepoweredindependentlyfromVCC.A0.1μFand0.01μFcapacitorshouldbeconnectedbetweenVCCQandVSStodecouplethecurrentsurgesfromthepowersupply.

VSS Supply Ground:AllVSSpinsmustbeconnectedtothesystemground.

RFU —Reserved for future use:ReservedbyMicrossforfuturedevicefunctionalityandenhancement.TheseshouldbetreatedinthesamewayasaDNUsignal.

DNU — Do not use:Donotconnecttoanyothersignal,orpowersupply;mustbeleftfloating.

NC — No connect:Nointernalconnection;canbedrivenorfloated.



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4 Memory Organization

4 .1 MemoryConfiguration

Themainmemoryarrayisdividedinto128KBor64KWuniformblocks.

Table 2: Blocks [1023:0]

Block Block SizeAddress Range (x8)

Block SizeAddress Range (x16)

Start End Start End

1023 128KB 7FE0000h 7FFFFFFh 64KW 3FF0000h 7FFFFFFh

⋮ ⋮ ⋮ ⋮ ⋮

511 3FE0000h 3FFFFFFh 1FF0000h 1FFFFFFh

⋮ ⋮ ⋮ ⋮ ⋮

255 1FE0000h 1FFFFFFh 0FF0000h 0FFFFFFh

⋮ ⋮ ⋮ ⋮ ⋮

127 0FE0000h 0FFFFFFh 07F0000h 07FFFFFh

⋮ ⋮ ⋮ ⋮ ⋮

63 07E0000h 07FFFFFh 03F0000h 03FFFFFh

⋮ ⋮ ⋮ ⋮ ⋮

8 0000000h 001FFFFh 0000000h 000FFFFh

Note:

1. 1Gbdevice=Blocks0–1023



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5 Bus Operations

Table 3: Bus Operations

Notes1and2applytoentiretable.

Operation CE# OE# WE# RST#VPP/WP#

8-Bit Mode 16-Bit Mode

A[MAX:0],DQ15/A-1

DQ[14:8] DQ[7:0] A[MAX:0]DQ15/A-1,DQ[14:0]

READ L L H H X Celladdress High-Z Dataoutput Celladdress Dataoutput

WRITE L H L H H3 Commandaddress

High-Z Datainput4Commandaddress

Datainput4

STANDBY H X X H X X High-Z High-Z X High-Z

OUTPUTDISABLE

L H H H X X High-Z High-Z X High-Z

RESET X X X L X X High-Z High-Z X High-Z

Notes:

1. Typicalglitchesoflessthan3nsonCE#,OE#,WE#,andRST#areignoredbythedeviceanddonotaffectbusoperations.

2. H=LogiclevelHIGH(VIH);L=LogiclevelLOW(VIL);X=HIGHorLOW.

3. IfWP#isLOW,thenthehighestorthelowestblockremainsprotected,dependingonlineitem.

4. Datainputisrequiredwhenissuingacommandsequenceorwhenperformingdatapollingorblockprotection.

5 .1 Read

BusREADoperationsreadfromthememorycells,registers,orCFIspace.ToacceleratetheREADoperation,thememoryarraycanbereadinpagemodewheredataisinternallyreadandstoredinapagebuffer.

Pagesizeis16words(32bytes)andisaddressedbyaddressinputsA[3:0]inx16busmodeandA[3:0]plusDQ15/A-1inx8busmode.TheextendedmemoryblocksandCFIareadonotsupportpagereadmode.



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AvalidbusREADoperationinvolvessettingthedesiredaddressontheaddressinputs,takingCE#andOE#LOW,andholdingWE#HIGH.ThedataI/Oswilloutputthevalue.IfCE#goesHIGHandreturnsLOWforasubsequentaccess,arandomreadaccessisperformandtACCortCEisrequired.(SeeACCharacteristicsfordetailsaboutwhentheoutputbecomesvalid.)

5 .2 Write

BusWRITEoperationswritetothecommandinterface.AvalidbusWRITEoperationbeginsbysettingthedesiredaddressontheaddressinputs.TheaddressinputsarelatchedbythecommandinterfaceonthefallingedgeofCE#orWE#,whicheveroccurslast.ThedataI/OsarelatchedbythecommandinterfaceontherisingedgeofCE#orWE#,whicheveroccursfirst.OE#mustremainHIGHduringtheentirebusWRITEoperation(SeeACCharacteristicsfortimingrequirementdetails).

5 .3 Standby

DrivingCE#HIGH in readmodecauses thedevice toenterstandbyanddata I/Os tobeHigh-Z (SeeDCCharacteristics).

DuringPROGRAMorERASEoperations, thedevicewillcontinue touse theprogram/erasesupplycurrent(ICC3)untiltheoperationcompletes.WhenCE#isHIGH,thedevicecannotbeplacedintostandbymodeduringaPROGRAM/ERASEoperation.

5 .4 Output Disable

DataI/OsareHigh-ZwhenOE#isHIGH.

5 .5 Reset

DuringresetmodethedeviceisdeselectedandtheoutputsareHigh-Z.Thedeviceis inresetmodewhenRST#isLOW.Thepowerconsumptionisreducedtothestandbylevel,independentlyfromCE#,OE#,orWE#inputs.

WhenRST#isHIGH,atimeoftPHELisrequiredbeforeaREADoperationcanaccessthedevice,andadelayoftPHWLisrequiredbeforeawritesequencecanbeinitiated.

Afterthiswake-upinterval,normaloperationisrestored,thedevicedefaultstoreadarraymode,andthedatapollingregisterisreset.

IfRST#isdrivenLOWduringaPROGRAM/ERASEoperationoranyotheroperationthatrequireswritingtothedevice,theoperationwillabortwithintPLRH,andmemorycontentsattheabortedblockoraddressarenolongervalid.



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6 Registers

6 .1 Data Polling Register

Table 4: Data Polling Register Bit Definitions

Note1appliestoentiretable.

Bit Name Settings Description Notes

DQ7Datapolling

bit

0or1,depending

onoperations

Monitorswhethertheprogram/erasecontrollerhassuccessfullycompleteditsoperation,orhasrespondedtoanERASESUSPENDoperation.

2,4

DQ6 TogglebitToggles:0to1;1to0;and

soon

Monitorswhethertheprogram,erase,orblankcheckcontrollerhassuccessfullycompleteditsoperations,orhasrespondedtoanERASESUSPENDoperation.DuringaPROGRAM/ERASE/BLANKCHECKoperation,DQ6togglesfrom0to1,1to0,andsoon,witheachsuccessiveREADoperationfromanyaddress.

3,4,5

DQ5 Errorbit0=Success 1=Failure

Identifieserrorsdetectedbytheprogram/erasecontroller.DQ5issetto1whenaPROGRAM,BLOCKERASE,orCHIPERASEoperationfailstowritethecorrectdatatothememory,orwhenaBLANKCHECKoperationfails.

4,6

DQ3Erasetimer

bit

0=Erasenotinprogress 1=Eraseinprogress

Identifiesthestartofprogram/erasecontrolleroperationduringaBLOCKERASEcommand.Beforetheprogram/erasecontrollerstarts,thisbitsetto0,andadditionalblockstobeerasedcanbewrittentothecommandinterface.

4

DQ2Alternativetogglebit

Toggles:0to1;1to0;and

soon

DuringCHIPERASE,BLOCKERASE,andERASESUSPENDoperations,DQ2togglesfrom0to1,1to0,andsoon,witheachsuccessiveREADoperationfromaddresseswithintheblocksbeingerased.

3,4

DQ1Bufferedprogramabortbit

1=AbortIndicatesaBUFFERPROGRAMoperationabort.TheBUFFEREDPROGRAMABORTandRESETcommandmustbeissuedtoreturnthedevicetoreadmode(seeWRITETOBUFFERPROGRAMcommand).

Notes:

1. ThedatapollingregistercanbereadduringPROGRAM,ERASE,orERASESUSPENDoperations;theREADoperationoutputsdataonDQ[7:0].

2. ForaPROGRAMoperationinprogress,DQ7outputsthecomplementofthebitbeingprogrammed.ForaBUFFERPROGRAMoperation,DQ7outputsthecomplementofthebitforthelastwordbeingprogrammedinthewritebuffer.ForaREADoperationfromtheaddresspreviouslyprogrammedsuccessfully,DQ7outputsexistingDQ7data.ForaREADoperationfromaddresseswithblockstobeerasedwhileanERASESUSPENDoperationisinprogress,DQ7outputs0;uponsuccessfulcompletion



10



oftheERASESUSPENDoperation,DQ7outputs1.ForanERASEoperationinprogress,DQ7outputs0;uponERASEoperation’ssuccessfulcompletion,DQ7outputs1.

3. AftersuccessfulcompletionofaPROGRAM,ERASE,orBLANKCHECKoperation,thedevicereturnstoreadmode.

4. Duringerasesuspendmode,READoperationstoaddresseswithinblocksnotbeingerasedoutputmemoryarraydataasifinreadmode.Aprotectedblockistreatedthesameasablocknotbeingerased.SeetheToggleFlowchartformoreinformation.

5. Duringerasesuspendmode,DQ6toggleswhenaddressingacellwithinablockbeingerased.Thetogglingstopswhentheprogram/erasecontrollerhassuspendedtheERASEoperation.SeetheToggleFlowchartformoreinformation.

6. WhenDQ5issetto1,aREAD/RESET(F0h)commandmustbeissuedbeforeanysubsequentcommand.

Table 5: Operations and Corresponding Bit Settings


Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 DQ1 RY/BY# Notes

PROGRAM Anyaddress DQ7# Toggle 0 – – 0 0 2

BLANK CHECK Anyaddress 1 Toggle 0 – – 0 0

CHIPERASE Anyaddress 0 Toggle 0 1 Toggle – 0

BLOCK ERASE beforetime-out

Erasingblock 0 Toggle 0 0 Toggle – 0

Non-erasingblock 0 Toggle 0 0 Notoggle – 0

BLOCK ERASEErasingblock 0 Toggle 0 1 Toggle – 0

Non-erasingblock 0 Toggle 0 1 Notoggle – 0

PROGRAMSUSPENDProgrammingblock Invalidoperation High-Z

Nonprogrammingblock Outputsmemoryarraydataasifinreadmode High-Z

ERASESUSPENDErasingblock 1 NoToggle 0 – Toggle – High-Z

Non-erasingblock Outputsmemoryarraydataasifinreadmode High-Z

PROGRAMduringERASESUSPEND

Erasingblock DQ7# Toggle 0 – Toggle – 0 2

Non-erasingblock DQ7# Toggle 0 – NoToggle – 0 2

BUFFEREDPROGRAMABORT Anyaddress DQ7# Toggle 0 – – 1 High-Z

PROGRAMError Anyaddress DQ7# Toggle 1 – – – High-Z 2

ERASE Error Anyaddress 0 Toggle 1 1 Toggle – High-Z

BLANK CHECK Error Anyaddress 0 Toggle 1 1 Toggle – High-Z

Notes:

1. Unspecifieddatabitsshouldbeignored.

2. DQ7#forbufferprogramisrelatedtothelastaddresslocationloaded.



11



6 .2 Lock Register

Table 6: Lock Register Bit Definitions


Bit Name Settings Description Notes

DQ2

Passwordprotectionmodelock

bit

0=Passwordprotectionmodeenabled;1=Passwordprotectionmodedisabled

(Default)

Placesthedevicepermanentlyin passwordprotectionmode.

2

DQ1

Nonvolatileprotectionmodelock

bit

0=Nonvolatileprotectionmodeenabledwithpasswordprotectionmodepermanentlydisabled;1=Nonvolatileprotectionmode

enabled(Default)

Placesthedeviceinnonvolatileprotectionmodewithpasswordprotectionmodepermanentlydisabled.When

shippedfromthefactory,thedevicewilloperateinnonvolatileprotectionmode,andthememoryblocksareunprotected.

2

DQ0

Extendedmemory block

protectionbit

0=Protected 1=Unprotected(Default)

Ifthedeviceisshippedwiththeextendedmemoryblockunlocked,theblockcanbeprotectedbysettingthisbitto0.TheextendedmemoryblockprotectionstatuscanbereadinautoselectmodebyissuinganAUTOSELECTcommand.

Notes:

1. Thelockregisterisa16-bit,one-timeprogrammableregister.DQ[15:3]arereservedandaresettoadefaultvalueof1.

2. Thepasswordprotectionmodelockbitandnonvolatileprotectionmodelockbitcannotbothbeprogrammedto0.Anyattempttoprogramonewhiletheotherisprogrammedcausestheoperationtoabort,andthedevicereturnstoreadmode.Thedeviceisshippedfromthefactorywiththedefaultsetting.



12



7 Standard Command Definitions – Address-Data Cycles

Table 7: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit


Command and Code/Subcode

Bus Size

Address and Data Cycles

Notes1st 2nd 3rd 4th 5th 6th

A D A D A D A D A D A D

READ and AUTO SELECT Operations

READ/RESET(F0h)

x8X F0 2

AAA AA 555 55 X F0

x16X F0

555 AA 2AA 55 X F0

READCFI(98h)x8 AAA

98x16 555

AUTOSELECT(90h)x8 AAA

AA555

55AAA

90 Note3 Note34,5

x16 555 2AA 555

BYPASS Operations

UNLOCKBYPASS(20h)x8 AAA

AA555

55AAA

20x16 555 2AA 555

UNLOCKBYPASSRESET(90h/00h)

x8X 90 X 0

x16

PROGRAM Operations

PROGRAM(A0h)x8 AAA

AA555

55AAA

A0 PA PDx16 555 2AA 555

UNLOCKBYPASS PROGRAM(A0h)

x8X A0 PA PD 6

x16

WRITETOBUFFER PROGRAM(25h)

x8 AAAAA

55555 BAd 25 BAd N PA PD 7,8,9

x16 555 2AA

UNLOCKBYPASSWRITETOBUFFERPROGRAM(25h)

x8BAd 25 BAd N PA PD 6

x16



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Bus Size

Address and Data Cycles

Notes1st 2nd 3rd 4th 5th 6th

A D A D A D A D A D A D

WRITETOBUFFERPROGRAMCONFIRM(29h)

x8BAd 29 7

x16

BUFFEREDPROGRAM ABORTandRESET(F0h)

x8 AAAAA

55555

AAAF0

x16 555 2AA 555

PROGRAMSUSPEND(B0h)x8

X B0x16

PROGRAMRESUME(30h)x8

X 30x16

ERASE Operations

CHIPERASE(80/10h)x8 AAA

AA555

55AAA

80AAA

AA555

55AAA

10x16 555 2AA 555 555 2AA 555

UNLOCKBYPASS CHIPERASE(80/10h)

x8X 80 X 10

6

x16

BLOCKERASE(80/30h)x8 AAA

AA555

55AAA

80AAA

AA555

55 BAd 30 10x16 555 2AA 555 555 2AA

UNLOCKBYPASSBLOCKERASE(80/30h)

x8X 80 BAd 30 6

x16

ERASESUSPEND(B0h)x8

X B0x16

ERASERESUME(30h)x8

X 30x16

BLANK CHECK Operations

BLANK CHECK SETUP(EB/76h)

x8 AAAAA

55555 BAd EB BAd 76 BAd 0 BAd 0

x16 555 2AA

BLANKCHECKCONFIRM andREAD(29h)

x8BAd 29

x16

Notes:

1. A=Address;D=Data;X=“Don’tCare;”BAd=Anyaddressintheblock;N+1=numberofwords(x16)/bytes(x8)tobeprogrammed;PA=Programaddress;PD=Programdata;Grayshading=Not



14



applicable.Allvaluesinthetablearehexadecimal.Somecommandsrequirebothacommandcodeandsubcode.Forthe2Gbdevice,theset-upcommandmustbeissuedforeachselecteddie.

2. Afullthree-cycleRESETcommandsequencemustbeusedtoresetthedeviceintheeventofabufferedprogramaborterror(DQ1=1).

3. ThesecellsrepresentREADcycles(versusWRITEcyclesfortheothers).

4. AUTOSELECTenablesthedevicetoreadthemanufacturercode,devicecode,blockprotectionstatus,andextendedmemoryblockprotectionindicator.

5. AUTOSELECTaddressesanddataarespecifiedintheElectronicSignaturetableandtheExtendedMemoryBlockProtectiontable.

6. ForanyUNLOCKBYPASSERASE/PROGRAMcommand,thefirsttwoUNLOCKcyclesareunnecessary.

7. BAdmustbethesameastheaddressloadedduringtheWRITETOBUFFERPROGRAM3rdand4thcycles.

8. WRITETOBUFFERPROGRAMoperation:maximumcycles=261(x8)and517(x16).UNLOCKBYPASSWRITETOBUFFERPROGRAMoperation:maximumcycles=259(x8),515(x16).WRITETOBUFFERPROGRAMoperation:N+1=numberofwords(x16)/bytes(x8)tobeprogrammed;maximumbuffersize=256bytes(x8)and1024bytes(x16).

9. Forx8,A[MAX:7]addresspinsshouldremainunchangedwhileA[6:0]andA-1pinsareusedtoselectabytewithintheN+1bytepage.Forx16,A[MAX:9]addresspinsshouldremainunchangedwhileA[8:0]pinsareusedtoselectawordwithintheN+1wordpage.

10. BLOCKERASEaddresscyclescanextendbeyondsixaddress-datacycles,dependingonthenumberofblockstoerase.

8 READ and AUTO SELECT Operations

8 .1 READ/RESET Command

TheREAD/RESET(F0h)commandreturnsthedevicetoreadmodeandresetstheerrorsinthedatapollingregister.OneorthreebusWRITEoperationscanbeusedtoissuetheREAD/RESETcommand.Note:Afullthree-cycleRESETcommandsequencemustbeusedtoresetthedeviceintheeventofabufferedprogramaborterror(DQ1=1).

8 .2 READ CFI Command

TheREADCFI(98h)commandputsthedeviceinreadCFImodeandisonlyvalidwhenthedeviceisinreadarrayorautoselectmode.OnebusWRITEcycleisrequiredtoissuethecommand.



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8 .3 AUTO SELECT Command

Atpower-uporafterahardwarereset,thedeviceisinreadmode.ItcanthenbeputinautoselectmodebyissuinganAUTOSELECT(90h)command.Autoselectmodeenablesthefollowingdeviceinformationtoberead:

• Electronicsignature,whichincludesmanufactureranddevicecodeinformation.

• Blockprotection,whichincludestheblockprotectionstatusandextendedmemoryblockprotectionindicator.

ThedevicecannotenterautoselectmodewhenaPROGRAMorERASEoperation is inprogress(RY/BY#LOW).However,autoselectmodecanbeenteredifthePROGRAMorERASEoperationhasbeensuspendedbyissuingaPROGRAMSUSPENDorERASESUSPENDcommand.

Autoselectmodeisexitedbyperformingareset.ThedevicereturnstoreadmodeunlessitenteredautoselectmodeafteranERASESUSPENDorPROGRAMSUSPENDcommand, inwhichcase it returnstoeraseorprogramsuspendmode.

9 Bypass Operations

9 .1 UNLOCK BYPASS Command

TheUNLOCKBYPASS(20h)commandisusedtoplacethedeviceinunlockbypassmode.ThreebusWRITEoperationsarerequiredtoissuetheUNLOCKBYPASScommand.

Whenthedeviceentersunlockbypassmode,thetwoinitialUNLOCKcyclesrequiredforastandardPROGRAMorERASEoperationarenotneeded,thusenablingfastertotalprogramorerasetime.

TheUNLOCKBYPASScommand isused in conjunctionwithUNLOCKBYPASSPROGRAMorUNLOCKBYPASSERASEcommandstoprogramorerasethedevicefasterthanwithstandardPROGRAMorERASEcommands.Whenthecycletimetothedeviceislong,considerabletimesavingscanbegainedbyusingthesecommands.Wheninunlockbypassmode,onlythefollowingcommandsarevalid:

• TheUNLOCKBYPASSPROGRAMcommandcanbeissuedtoprogramaddresseswithinthedevice.

• TheUNLOCKBYPASSBLOCKERASEcommandcanthenbeissuedtoeraseoneormorememoryblocks.

• TheUNLOCKBYPASSCHIPERASEcommandcanbeissuedtoerasethewholememoryarray.

• TheUNLOCKBYPASSWRITETOBUFFERPROGRAMcommandcanbeissuedtospeeduptheprogrammingoperation.

• TheUNLOCKBYPASSRESETcommandcanbeissuedtoreturnthedevicetoreadmode.



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9 .2 UNLOCK BYPASS RESET Command

TheUNLOCKBYPASSRESET(90/00h)commandisusedtoreturntoread/resetmodefromunlockbypassmode.TwobusWRITEoperationsarerequiredtoissuetheUNLOCKBYPASSRESETcommand.TheREAD/RESETcommanddoesnotexitfromunlockbypassmode.

10 Program Operations

10 .1 PROGRAM Command

ThePROGRAM(A0h)commandcanbeusedtoprogramavaluetooneaddressinthememoryarray.ThecommandrequiresfourbusWRITEoperations,andthefinalWRITEoperationlatchestheaddressanddataintheinternalstatemachineandstartstheprogram/erasecontroller.Afterprogramminghasstarted,busREADoperationsoutputthedatapollingregistercontent.

10 .2 UNLOCK BYPASS PROGRAM Command

Whenthedeviceisinunlockbypassmode,theUNLOCKBYPASSPROGRAM(A0h)commandcanbeusedtoprogramone address in thememory array. The command requires twobusWRITEoperations insteadof four required by a standard PROGRAMcommand; the finalWRITE operation latches the address anddataandstartstheprogram/erasecontroller (ThestandardPROGRAMcommandrequiresfourbusWRITEoperations).ThePROGRAMoperationusingtheUNLOCKBYPASSPROGRAMcommandbehavesidenticallytothePROGRAMoperationusingthePROGRAMcommand.Theoperationcannotbeaborted.AbusREADoperationtothememoryoutputsthedatapollingregister.

10 .3 WRITE TO BUFFER PROGRAM Command

The WRITE TO BUFFER PROGRAM (25h) command makes use of the program buffer to speed upprogramminganddramatically reducessystemprogramming timecompared to thestandardnon-bufferedPROGRAMcommand.256Mbthrough2Gbdevicessupporta512-wordmaximumprogrambuffer.

10 .4 UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command

Whenthedeviceisinunlockbypassmode,theUNLOCKBYPASSWRITETOBUFFER(25h)commandcanbeusedtoprogramthedeviceinfastprogrammode.ThecommandrequirestwobusWRITEoperationsfewerthanthestandardWRITETOBUFFERPROGRAMcommand.



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10 .5 WRITE TO BUFFER PROGRAM CONFIRM Command

TheWRITETOBUFFERPROGRAMCONFIRM (29h) command is used toconfirmaWRITETOBUFFERPROGRAMcommandandtoprogramthen+1words/bytesloadedintheprogrambufferbythiscommand.

10 .6 BUFFERED PROGRAM ABORT AND RESET Command

ABUFFEREDPROGRAMABORTANDRESET(F0h)commandmustbeissuedtoresetthedevicetoreadmodewhentheBUFFERPROGRAMoperationisaborted.Thebufferprogrammingsequencecanbeabortedinthefollowingways:

• LoadavaluethatisgreaterthanthepagebuffersizeduringthenumberoflocationstoprogramintheWRITETOBUFFERPROGRAMcommand.

• WritetoanaddressinadifferentblockthantheonespecifiedduringtheWRITEBUFFERLOADcommand.

• Writeanaddress/datapairtoadifferentwritebufferpagethantheoneselectedbythestartingaddressduringtheprogrambufferdataloadingstageoftheoperation.

• WritedataotherthantheCONFIRMcommandafterthespecifiednumberofdataloadcycles.

The abort condition is indicatedbyDQ1=1,DQ7=DQ7# (for the last address location loaded),DQ6=toggle,andDQ5=0(allofwhicharedatapollingregisterbits).ABUFFEREDPROGRAMABORTandRESETcommandsequencemustbewrittentoresetthedeviceforthenextoperation.

Note:Thefullthree-cycleBUFFEREDPROGRAMABORTandRESETcommandsequenceisrequiredwhenusingbufferprogrammingfeaturesinunlockbypassmode.

10 .7 PROGRAM SUSPEND Command

ThePROGRAMSUSPEND(B0h)commandcanbeusedtointerruptaprogramoperationsothatdatacanbereadfromanotherblock.WhenthePROGRAMSUSPENDcommandisissuedduringaprogramoperation,thedevicesuspends theoperationwithin theprogramsuspend latency timeandupdates thedatapollingregisterbits.

Aftertheprogramoperationhasbeensuspended,datacanbereadfromanyaddress.However,dataisinvalidwhenreadfromanaddresswhereaprogramoperationhasbeensuspended.

ThePROGRAMSUSPENDcommandmayalsobe issuedduringaPROGRAMoperationwhileanerase issuspended.Inthiscase,datamaybereadfromanyaddressnotinerasesuspendorprogramsuspendmode.



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10 .8 PROGRAM RESUME Command

ThePROGRAMRESUME(30h)commandmustbeissuedtoexitaprogramsuspendmodeandresumeaPROGRAMoperation.ThecontrollercanuseDQ7orDQ6datapollingbits todetermine thestatusof thePROGRAMoperation.AfteraPROGRAMRESUMEcommandis issued,subsequentPROGRAMRESUMEcommands are ignored. Another PROGRAM SUSPEND command can be issued after the device hasresumedprogramming.

11 Erase Operations

11 .1 CHIP ERASE Command

TheCHIPERASE(80/10h)commanderasestheentirechip.SixbusWRITEoperationsarerequiredtoissuethecommandandstarttheprogram/erasecontroller.

Protectedblocksarenoterased.Ifallblocksareprotected,thedataremainsunchanged.Noerrorisreportedwhenprotectedblocksarenoterased.

DuringtheCHIPERASEoperation, thedevice ignoresallothercommands, includingERASESUSPEND. Itisnotpossibletoaborttheoperation.AllbusREADoperationsduringCHIPERASEoutputthedatapollingregisteronthedataI/Os.

11 .2 UNLOCK BYPASS CHIP ERASE Command

Whenthedeviceisinunlockbypassmode,theUNLOCKBYPASSCHIPERASE(80/10h)commandcanbeusedtoeraseallmemoryblocksatonetime.ThecommandrequiresonlytwobusWRITEoperationsinsteadofsixusingthestandardCHIPERASEcommand.ThefinalbusWRITEoperationstartstheprogram/erasecontroller.

11 .3 BLOCK ERASE Command

TheBLOCKERASE(80/30h)commanderasesa listofoneormoreblocks. Itsetsallbits in theselected,unprotectedblocksto1.Allprevious,selected,unprotectedblocksdataintheselectedblocksislost.

11 .4 UNLOCK BYPASS BLOCK ERASE Command

Whenthedeviceisinunlockbypassmode,theUNLOCKBYPASSBLOCKERASE(80/30h)commandcanbeusedtoeraseoneormorememoryblocksatatime.ThecommandrequirestwobusWRITEoperationsinsteadofsixusingthestandardBLOCKERASEcommand.ThefinalbusWRITEoperationlatchestheaddressoftheblockandstartstheprogram/erasecontroller.



19



Toerasemultipleblocks(afterthefirsttwobusWRITEoperationshaveselectedthefirstblockinthelist),eachadditionalblockinthelistcanbeselectedbyrepeatingthesecondbusWRITEoperationusingtheaddressoftheadditionalblock.

11 .5 ERASE SUSPEND Command

TheERASESUSPEND(B0h)commandtemporarilysuspendsaBLOCKERASEoperation.OnebusWRITEoperationisrequiredtoissuethecommand.Theblockaddressis“Don’tCare.”

11 .6 ERASE RESUME Command

The ERASE RESUME (30h) command restarts the program/erase controller after an ERASESUSPENDoperation.

Thedevicemustbe inreadarraymodebeforetheRESUMEcommandwillbeaccepted.Anerasecanbesuspendedandresumedmorethanonce.

12 BLANK CHECK Operation

12 .1 BLANK CHECK Commands

TwocommandsarerequiredtoexecuteaBLANKCHECKoperation:BLANKCHECKSETUP(EB/76h)andBLANKCHECKCONFIRMANDREAD(29h).

TheBLANKCHECKoperationdetermineswhetheraspecifiedblockisblank(thatis,completelyerased).ItcanalsobeusedtodeterminewhetherapreviousERASEoperationwassuccessful,includingERASEoperationsthatmighthavebeeninterruptedbypowerloss.

TheBLANKCHECKoperationchecksforcellsthatareprogrammedorover-erased.Ifitfindsany,itreturnsafailurestatus,indicatingthattheblockisnotblank.Ifitreturnsapassingstatus,theblockisguaranteedblank(all1s)andisreadytoprogram.



20



13 Block Protection Command Definitions – Address-Data Cycles

Table 8: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit

Notes1and2applytoentiretable.


Bus Size

Address and Data CyclesNotes1st 2nd 3rd 4th

…nth

A D A D A D A D A D

LOCK REGISTER Commands

ENTERLOCKREGISTER COMMANDSET(40h)

x8 AAA AA 555 55 AAA40 3

x16 555 AA 2AA 55 555

PROGRAMLOCK REGISTER(A0h)

x8X A0 X Data 5

x16

READLOCKREGISTERx8

X Data 4,5,6x16

EXITLOCKREGISTER(90h/00h)

x8X 90 X 00 3

x16

PASSWORD PROTECTION Commands

ENTERPASSWORDPROTECTIONCOMMAND

SET(60h)

x8 AAA AA 555 55 AAA60 3

x16 555 AA 2AA 55 555

PROGRAMPASSWORD(A0h)

x8X A0 PWAn PWDn 7

x16

READPASSWORDx8 00 PWD0 01 PWD1 2 PWD2 3 PWD3

…7 PWD7 4,6,8,

9x16 00 PWD0 01 PWD1 2 PWD2 3 PWD3

UNLOCKPASSWORD(25h/03h)

x800 25 00 3 00 PWD0 01 PWD1 … 00 29 8,10

x16

EXITPASSWORDPROTECTION(90h/00h)

x8X 90 X 0 3

x16

NONVOLATILE PROTECTION Commands

ENTERNONVOLATILEPROTECTIONCOMMAND

SET(C0h)

x8 AAA AA 555 55 AAAC0 3

x16 555 AA 2AA 55 555

PROGRAMNONVOLATILEPROTECTIONBIT(A0h)

x8X A0 BAd 00 11

x16

READNONVOLATILEPROTECTIONBITSTATUS

x8BAd

READ(DQ0)

4,6,11x16

CLEARALLNONVOLATILEPROTECTIONBITS

(80h/30h)

x8X 80 00 30 12

x16



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Bus Size

Address and Data CyclesNotes1st 2nd 3rd 4th

…nth

A D A D A D A D A D

NONVOLATILE PROTECTION BIT LOCK BIT Commands

ENTERNONVOLATILEPROTECTIONBITLOCKBIT

COMMANDSET(50h)

x8 AAA AA 555 55 AAA50 3

x16 555 AA 2AA 55 555

PROGRAMNONVOLATILEPROTECTIONBIT LOCKBIT(A0h)

x8X A0 X 00

x16

READNONVOLATILEPROTECTIONBITLOCK

BITSTATUS

x8X

READ(DQ0)

4,6, 11x16

EXITNONVOLATILEPROTECTIONBITLOCKBIT

(90h/00h)

x8X 90 X 00 3

x16

VOLATILE PROTECTION Commands

ENTERVOLATILEPROTECTIONCOMMAND

SET(E0h)

x8 AAA AA 555 55 AAAE0 3

x16 555 AA 2AA 55 555

PROGRAMVOLATILEPROTECTIONBIT(A0h)

x8X A0 BAd 00 11

x16

READVOLATILEPROTECTIONBITSTATUS

x8BAd

READ(DQ0)

4,6x16

CLEARVOLATILEPROTECTIONBIT(A0h)

x8X A0 BAd 01 11

x16

EXITVOLATILEPROTECTION(90h/00h)

x8X 90 X 00 3

x16

EXTENDED MEMORY BLOCK Operations

ENTEREXTENDEDMEMORYBLOCK(88h)

x8 AAAAA

55555

AAA88

x16 555 2AA 555

PROGRAMEXTENDEDMEMORYBLOCK(A0h)

x8 AAAAA

55555

AAAA0

Wordaddress

datax16 555 2AA 555

READEXTENDED MEMORY BLOCK

x8 Wordaddress

datax16

EXITEXTENDEDMEMORYBLOCK(90h/00h)

x8 AAAAA

55555 555 90 X 00

x16 555 2AA

Notes:

1. Key:A=AddressandD=Data;X=“Don’tCare;”BAd=Anyaddressintheblock;PWDn=Passwordbytes,n=0to7(×8)/words0to3(×16);PWAn=Passwordaddress,n=0to7(×8)/0to3(×16);PWDn=Passwordwords,n=0to3(×16);PWAn=Passwordaddress,n=0to3(×16);Gray=Notapplicable.Allvaluesinthetablearehexadecimal.



22



2. DQ[15:8]are“Don’tCare”duringUNLOCKandCOMMANDcycles.A[MAX:16]are“Don’tCare”duringUNLOCKandCOMMANDcycles,unlessanaddressisrequired.

3. TheENTERcommandsequencemustbeissuedpriortoanyoperation.ItdisablesREADandWRITEoperationsfromandtoblock0.READandWRITEoperationsfromandtoanyotherblockareallowed.Also,whenanENTERCOMMANDSETcommandisissued,anEXITCOMMANDSETcommandmustbeissuedtoreturnthedevicetoREADmode.

4. READREGISTER/PASSWORDcommandshavenocommandcode;CE#andOE#aredrivenLOWanddataisreadaccordingtoaspecifiedaddress.

5. Data=Lockregistercontent.

6. AlladdresscyclesshownforthiscommandareREADcycles.

7. OnlyoneportionofthepasswordcanbeprogrammedorreadbyeachPROGRAMPASSWORDcommand.

8. Eachportionofthepasswordcanbeenteredorreadinanyorderaslongastheentire64-bitpasswordisenteredorread.

9. Forthex8READPASSWORDcommand,thenth(andfinal)addresscycleequalsthe8thaddresscycle.Fromthe5thtothe8thaddresscycle,thevaluesforeachaddressanddatapaircontinuethepatternshowninthetableasfollows:forx8,addressanddata=04andPWD4;05andPWD5;06andPWD6;07andPWD7.

10. Forthex8UNLOCKPASSWORDcommand,thenth(andfinal)addresscycleequalsthe11thaddresscycle.Fromthe5thtothe10thaddresscycle,thevaluesforeachaddressanddatapaircontinuethepatternshowninthetableasfollows:addressanddata=02andPWD2;03andPWD3;04andPWD4;05andPWD5;06andPWD6;07andPWD7.Forthex16UNLOCKPASSWORDcommand,thenth(andfinal)addresscycleequalsthe7thaddresscycle.Forthe5thand6thaddresscycles,thevaluesfortheaddressanddatapaircontinuethepatternshowninthetableasfollows:addressanddata=02andPWD2;03andPWD3.

11. Bothnonvolatileandvolatileprotectionbitsettingsareasfollows:Protectedstate=00;Unprotectedstate=01.

12. TheCLEARALLNONVOLATILEPROTECTIONBITScommandprogramsallnonvolatileprotectionbitsbeforeerasure.Thispreventsover-erasureofpreviouslyclearednonvolatileprotectionbits.

14 Protection Operations

BlockscanbeprotectedindividuallyagainstaccidentalPROGRAM,orERASEoperationsonboth8-bitand16-bitconfigurations.

Memory block and extended memory block protection is configured through the lock register (see LockRegistersection).



23



14 .1 LOCK REGISTER Commands

After the ENTER LOCK REGISTER COMMAND SET (40h) command has been issued, all bus READ orPROGRAMoperationscanbeissuedtothelockregister.ThePROGRAMLOCKREGISTER(A0h)commandallowsthelockregistertobeconfigured.

TheprogrammeddatacanthenbecheckedwithaREADLOCKREGISTERcommandbydrivingCE#andOE#LOWwiththeappropriateaddressdataontheaddressbus.

14 .2 PASSWORD PROTECTION Commands

After the ENTER PASSWORD PROTECTION COMMAND SET (60h) command has been issued, thecommandsrelatedtopasswordprotectionmodecanbeissuedtothedevice.ThePROGRAMPASSWORD(A0h)commandisusedtoprogramthe64-bitpasswordusedinthepasswordprotectionmode.

TheREADPASSWORDcommandisusedtoverifythepasswordusedinpasswordprotectionmode.

TheUNLOCKPASSWORD(25/03h)commandisusedtoclearthenonvolatileprotectionbitlockbit,allowingthenonvolatileprotectionbitstobemodified.TheUNLOCKPASSWORDcommandmustbe issued,alongwiththecorrectpassword,andrequiresa1μsdelaybetweensuccessiveUNLOCKPASSWORDcommandsinordertopreventhackersfromcrackingthepasswordbytryingallpossible64-bitcombinations.Ifthisdelaydoesnotoccur,thelatestcommandwillbeignored.Approximately1μsisrequiredforunlockingthedeviceafterthevalid64-bitpasswordhasbeenprovided.

14 .3 NONVOLATILE PROTECTION Commands

After the ENTER NONVOLATILE PROTECTION COMMAND SET (C0h) command has been issued, thecommandsrelatedtononvolatileprotectionmodecanbeissuedtothedevice.

AblockcanbeprotectedfromprogramorerasebyissuingaPROGRAMNONVOLATILEPROTECTIONBIT(A0h)command,alongwiththeblockaddress.Thiscommandsetsthenonvolatileprotectionbit to0 foragivenblock.

ThestatusofanonvolatileprotectionbitforagivenblockorgroupofblockscanbereadbyissuingaREADNONVOLATILEMODIFYPROTECTIONBITcommand,alongwiththeblockaddress.

ThenonvolatileprotectionbitsareerasedsimultaneouslybyissuingaCLEARALLNONVOLATILEPROTECTIONBITS(80/30h)command.Nospecificblockaddressisrequired.Ifthenonvolatileprotectionbitlockbitissetto0,thecommandfails.



24



14 .4 NONVOLATILE PROTECTION BIT LOCK BIT Commands

After theENTERNONVOLATILEPROTECTIONBITLOCKBITCOMMANDSET (50h)commandhasbeenissued,thecommandsthatallowthenonvolatileprotectionbitlockbittobesetcanbeissuedtothedevice.

ThePROGRAMNONVOLATILEPROTECTIONBITLOCKBIT(A0h)commandisusedtosetthenonvolatileprotectionbitlockbitto0,thuslockingthenonvolatileprotectionbitsandpreventingthemfrombeingmodified.

TheREADNONVOLATILEPROTECTIONBITLOCKBITSTATUScommandisusedtoreadthestatusofthenonvolatileprotectionbitlockbit.

14 .5 VOLATILE PROTECTION Commands

After theENTERVOLATILEPROTECTIONCOMMANDSET (E0h)commandhasbeen issued,commandsrelatedtothevolatileprotectionmodecanbeissuedtothedevice.

ThePROGRAMVOLATILEPROTECTIONBIT(A0h)commandindividuallysetsavolatileprotectionbitto0foragivenblock.Ifthenonvolatileprotectionbitforthesameblockisset,theblockislockedregardlessofthevalueofthevolatileprotectionbit.(SeetheBlockProtectionStatustable.)

ThestatusofavolatileprotectionbitforagivenblockcanbereadbyissuingaREADVOLATILEPROTECTIONBITSTATUScommandalongwiththeblockaddress.

TheCLEARVOLATILEPROTECTIONBIT(A0h)commandindividuallyclears(setsto1)thevolatileprotectionbitforagivenblock.Ifthenonvolatileprotectionbitforthesameblockisset,theblockislockedregardlessofthevalueofthevolatileprotectionbit.(SeetheBlockProtectionStatustable.)

14 .6 EXTENDED MEMORY BLOCK Commands

The device has one extra 128-word extendedmemory block that can be accessed only by the ENTEREXTENDEDMEMORYBLOCK(88h)command.Theextendedmemoryblockis128words(x16)or256bytes(x8). It isusedasasecurityblocktoprovideapermanent128-bitsecurity identificationnumberortostoreadditionalinformation.

14 .7 EXIT PROTECTION Command

The EXIT PROTECTION COMMAND SET (90/00h) command is used to exit the lock register, passwordprotection, nonvolatile protection, volatile protection, and nonvolatile protection bit lock bit command setmodesandreturnthedevicetoreadmode.



25



15 Device Protection

15 .1 Hardware Protection

The VPP/WP# function provides a hardware method of protecting either the highest/lowest block. WhenVPP/WP#isLOW,PROGRAMandERASEoperationsoneitheroftheseblockoptionsis ignoredtoprovideprotection.WhenVPP/WP#isHIGH,thedevicerevertstothepreviousprotectionstatusforthehighest/lowestblock.PROGRAMandERASEoperationscanmodifythedataineitheroftheseblockoptionsunlessblockprotectionisenabled.

Note:MicrosshighlyrecommendsdrivingVPP/WP#HIGHorLOW.IfasystemneedstofloattheVPP/WP#pin,withoutapull-up/pull-downresistorandnocapacitor,thenaninternalpull-upresistorisenabled.

Table 9: VPP/WP# Functions

VPP/WP# Settings Function

VILHighest/lowestblockisprotected;fora2Gbdevice,boththehighestandthelowestblocksarehardware-protected(block0andblock2047).

VIH Highest/lowestblockorthetop/bottomtwoblocksareunprotectedunlesssoftwareprotectionisactivated.

15 .2 Software Protection

Foursoftwareprotectionmodesareavailable:

• Volatileprotection

• Nonvolatileprotection

• Passwordprotection

• Passwordaccess

Thedeviceisshippedwithallblocksunprotected.Onfirstuse,thedevicedefaultstothenonvolatileprotectionmodebutcanbeactivatedineitherthenonvolatileprotectionorpasswordprotectionmode.

The desired protectionmode is activated by setting either the nonvolatile protectionmode lock bit or thepasswordprotectionmodelockbitofthelockregister.Bothbitsareone-time-programmableandnonvolatile;therefore,aftertheprotectionmodehasbeenactivated,itcannotbechanged,andthedeviceissetpermanentlytooperateintheselectedprotectionmode.Itisrecommendedthatthedesiredsoftwareprotectionmodebeactivatedwhenfirstprogrammingthedevice.



26



Forthelowestandhighestblocks,ahigherlevelofblockprotectioncanbeachievedbylockingtheblocksusingnonvolatileprotectionmodeandholdingVPP/WP#LOW.Blockswithvolatileprotectionandnonvolatileprotectioncancoexistwithinthememoryarray.Iftheuserattemptstoprogramoreraseaprotectedblock,thedeviceignoresthecommandandreturnstoreadmode.

Theblockprotectionstatuscanbe readbyperforminga readelectronicsignatureorby issuinganAUTOSELECTcommand.

15 .3 Volatile Protection Mode

Volatileprotectionenablesthesoftwareapplicationtoprotectblocksagainstinadvertentchangeandcanbedisabledwhenchangesareneeded.Volatileprotectionbitsareuniqueforeachblockandcanbeindividuallymodified.Volatileprotectionbitscontroltheprotectionschemeonlyforunprotectedblockswhosenonvolatileprotection bits are cleared to 1. Issuing a PROGRAMVOLATILE PROTECTIONBIT or CLEAR VOLATILEPROTECTIONBITcommandsets to0orclears to1 thevolatileprotectionbitsandplacestheassociatedblocksintheprotected(0)orunprotected(1)state,respectively.Thevolatileprotectionbitcanbesetorclearedasoftenasneeded.

Whenthedeviceisfirstshipped,orafterapower-uporhardwarereset,thevolatileprotectionbitsdefaultto1(unprotected).

15 .4 Nonvolatile Protection Mode

Anonvolatileprotectionbitisassignedtoeachblock.EachofthesebitscanbesetforprotectionindividuallybyissuingaPROGRAMNONVOLATILEPROTECTIONBITcommand.Also,eachdevicehasoneglobalvolatilebitcalledthenonvolatileprotectionbitlockbit;itcanbesettoprotectallnonvolatileprotectionbitsatonce.Thisglobalbitmustbesetto0onlyafterallnonvolatileprotectionbitsareconfiguredtothedesiredsettings.Whensetto0,thenonvolatileprotectionbitlockbitpreventschangestothestateofthenonvolatileprotectionbits.Whenclearedto1,thenonvolatileprotectionbitscanbesetandclearedusingthePROGRAMNONVOLATILEPROTECTIONBITandCLEARALLNONVOLATILEPROTECTIONBITScommands,respectively.

Nosoftwarecommandunlocksthenonvolatileprotectionbitlockbitunlessthedeviceisinpasswordprotectionmode;innonvolatileprotectionmode,thenonvolatileprotectionbitlockbitcanbeclearedonlybytakingthedevicethroughahardwareresetorpower-up.

Nonvolatileprotectionbitsstatuscannotbechangedthroughahardwareresetorapower-down/power-upsequence.Nonvolatileprotectionbitscannotbeclearedindividually;theymustbeclearedallatonceusingaCLEARALLNONVOLATILEPROTECTIONBITScommand.

Ifoneofthenonvolatileprotectionbitsneedstobecleared(unprotected),additionalstepsarerequired:First,thenonvolatileprotectionbitlockbitmustbeclearedto1,usingeitherapower-cycleorhardwarereset.Then,thenonvolatileprotectionbitscanbechangedtoreflectthedesiredsettings.Finally,thenonvolatileprotectionbitlockbitmustbesetto0tolockthenonvolatileprotectionbits.Thedevicenowwilloperatenormally.



27



Toachievethebestprotection,thePROGRAMNONVOLATILEPROTECTIONLOCKBITcommandshouldbeexecutedearlyinthebootcode,andthebootcodeshouldbeprotectedbyholdingVPP/WP#LOW.

NonvolatileprotectionbitsandvolatileprotectionbitshavethesamefunctionwhenVPP/WP#isHIGHorwhenVPP/WP#isatthevoltageforprogramacceleration(VPPH).

15 .5 Password Protection Mode

Thepasswordprotectionmodeprovidesahigher levelofsecurity than thenonvolatileprotectionmodebyrequiring a 64-bit password to unlock the nonvolatile protection bit lock bit. In addition to this passwordrequirement,thenonvolatileprotectionbitlockbitissetto0afterpower-upandresettomaintainthedeviceinpasswordprotectionmode.

Executing the UNLOCK PASSWORD command by entering the correct password clears the nonvolatileprotectionbitlockbit,enablingtheblocknonvolatileprotectionbitstobemodified.Ifthepasswordprovidedisincorrect,thenonvolatileprotectionbitlockbitremainslocked,andthestateofthenonvolatileprotectionbitscannotbemodified.

Note:Thereisnomeanstoverifythepasswordafterpasswordprotectionmodeisenabled.Ifthepasswordislostafterenablingthepasswordprotectionmode,thereisnowaytoclearthenonvolatileprotectionbitlockbit.

15 .6 Password Access

Password access is a security enhancement that protects information stored in themain array blocks bypreventing content alteration or reads until a valid 64-bit password is received.Password accessmaybecombinedwithnonvolatileand/orvolatileprotectiontocreateamulti-tieredsolution.

16 Common Flash Interface

ThecommonFlashinterface(CFI)isaJEDEC-approved,standardizeddatastructurethatcanbereadfromtheFlashmemorydevice.Itallowsasystem’ssoftwaretoquerythedevicetodeterminevariouselectricalandtimingparameters,density information,and functionssupportedby thememory.Thesystemcan interfaceeasilywiththedevice,enablingthesoftwaretoupgradeitselfwhennecessary.

WhentheREADCFIcommandisissued,thedeviceentersCFIquerymodeandthedatastructureisreadfrommemory.Thequerydataisalwayspresentedonthelowestorderdataoutputs(DQ[7:0]),andtheotherdataoutputs(DQ[15:8])aresetto0.



28



17 Power-Up and Reset Characteristics

Table 10: Power-Up Specifications

ParameterSymbol

Min Unit NotesLegacy JEDEC

VCCHIGHtoVCCQHIGH – tVCHVCQH 0 μs 1

VCCHIGHtorisingedgeofRST# tVCS tVCHPH 300 μs 2,3

VCCQHIGHtorisingedgeofRST# tVIOS tVCQHPH 0 μs 2,3

RST#HIGHtochipenableLOW tRH tPHEL 50 ns

RST#HIGHtowriteenableLOW – tPHWL 150 ns

Figure 3: Power-Up Timing

Power-Up and Reset Characteristics

Table 22: Power-Up Specifications

Parameter

Symbol

Min Unit NotesLegacy JEDEC

VCC HIGH to VCCQ HIGH – tVCHVCQH 0 µs 1

VCC HIGH to rising edge of RST# tVCS tVCHPH 300 µs 2, 3

VCCQ HIGH to rising edge of RST# tVIOS tVCQHPH 0 µs 2, 3

RST# HIGH to chip enable LOW tRH tPHEL 50 ns

RST# HIGH to write enable LOW – tPHWL 150 ns

Notes: 1. VCC should attain VCC,min from VSS simultaneously with or prior to applying VCCQ, VPPduring power up. VCC should attain VSS during power down.

2. If RST# is not stable for tVCS or tVIOS, the device will not allow any READ or WRITE oper-ations, and a hardware reset is required.

3. Power supply transitions should only occur when RST# is LOW.

Figure 14: Power-Up Timing

tRH

tVIOS

tVCS

tPHWL

tVCHVCQH

VCCQ

VCC

CE#

RST#

WE#

VSSQ

VSS

256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR FlashPower-Up and Reset Characteristics





29



Table 11: Reset AC Specifications

Condition/ParameterSymbol

Min Max Unit NotesLegacy JEDEC

RST#LOWtoreadmodeduringprogramorerase tREADY tPLRH – 32 μs 1

RST#pulsewidth tRP tPLPH 100 – ns

RST#HIGHtoCE#LOW,OE#LOW tRH tPHEL,tPHGL 50 – ns 1

RST#LOWtostandbymodeduringreadmodetRPD

– 10 – μs

RST#LOWtostandbymodeduringprogramorerase 50 – μs

RY/BY#HIGHtoCE#LOW,OE#LOW tRB tRHEL,tRHGL 0 – ns 1

Note1:Sampledonly;not100%tested.

Figure 4: Reset AC Timing – No PROGRAM/ERASE Operation in Progress


Condition/Parameter

Symbol


RST# LOW to read mode during program orerase

tREADY tPLRH – 32 µs 1

RST# pulse width tRP tPLPH 100 – ns

RST# HIGH to CE# LOW, OE# LOW tRH tPHEL, tPHGL 50 – ns 1

RST# LOW to standby mode during read mode tRPD – 10 – µs

RST# LOW to standby mode during program orerase

50 – µs

RY/BY# HIGH to CE# LOW, OE# LOW tRB tRHEL, tRHGL 0 – ns 1

Note: 1. Sampled only; not 100% tested.


tRH

RY/BY#

CE#, OE#

RST#

tRP

Figure 16: Reset AC Timing During PROGRAM/ERASE Operation

tRB

RY/BY#

CE#, OE#

RST#

tRP

tRH

tREADY






Condition/Parameter

Symbol


RST# LOW to read mode during program orerase

tREADY tPLRH – 32 µs 1

RST# pulse width tRP tPLPH 100 – ns

RST# HIGH to CE# LOW, OE# LOW tRH tPHEL, tPHGL 50 – ns 1

RST# LOW to standby mode during read mode tRPD – 10 – µs

RST# LOW to standby mode during program orerase

50 – µs

RY/BY# HIGH to CE# LOW, OE# LOW tRB tRHEL, tRHGL 0 – ns 1



tRH

RY/BY#

CE#, OE#

RST#

tRP


tRB

RY/BY#

CE#, OE#

RST#

tRP

tRH

tREADY






30



18 Absolute Ratings and Operating Conditions

Stressesgreaterthanthoselistedmaycausepermanentdamagetothedevice.Thisisastressratingonly,andfunctionaloperationofthedeviceattheseoranyotherconditionsoutsidethoseindicatedintheoperationalsectionsof this specification isnot implied.Exposure toabsolutemaximum ratingconditions forextendedperiodsmayadverselyaffectreliability.

Table 12: Absolute Maximum/Minimum Ratings

Parameter Symbol Min Max Unit Notes

Temperatureunderbias TBIAS –50 125 °C

Storagetemperature TSTG –65 150 °C

Supplyvoltage VCC –2 VCC + 2 V 1,2

Input/outputsupplyvoltage VCCQ –2 VCCQ + 2 V 1,2

Programvoltage VPPH –0 .6 14 .5 V 3

Notes:

1. Duringsignaltransitions,minimumvoltagemayundershootto−2Vforperiodslessthan20ns.

2. Duringsignaltransitions,maximumvoltagemayovershoottoVCC+2Vforperiodslessthan20ns.

3. VPPHmustnotremainat12Vformorethan80hourscumulative.

Table 13: Operating Conditions

Parameter Symbol Min Max Unit

Supplyvoltage VCC 2 .7 3 .6 V

Input/outputsupplyvoltage(VCCQ ≤ VCC) VCCQ 1 .65 3 .6 V

Programvoltage VPP –2 .0 12 .5 V

Ambientoperatingtemperature TA –40 85 °C

Loadcapacitance CL 30 pF

Inputriseandfalltimes – – 10 ns

Inputpulsevoltages – 0toVCCQ V

Inputandoutputtimingreferencevoltages – VCCQ/2 V



31



Figure 6: AC Measurement Load Circuit


CL

VCCQ

25kΩ

Deviceundertest

0.1µF

VCC

25kΩ

Note: 1. CL includes jig capacitance.

Figure 18: AC Measurement I/O Waveform

VCCQ

0V

VCCQ/2

Table 26: Input/Output Capacitance

Parameter Symbol Test Condition Min Max Unit

Input capacitance for 256Mb and 512Mb CIN VIN = 0V 3 8 pF

Input capacitance for 1Gb 4 9 pF


Output capacitance COUT VOUT = 0V 3 6 pF

256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR FlashAbsolute Ratings and Operating Conditions





CL

VCCQ

25kΩ

Deviceundertest

0.1µF

VCC

25kΩ

Note: 1. CL includes jig capacitance.


VCCQ

0V

VCCQ/2



Input capacitance for 256Mb and 512Mb CIN VIN = 0V 3 8 pF



Output capacitance COUT VOUT = 0V 3 6 pF

256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR FlashAbsolute Ratings and Operating Conditions





Inputcapacitancefor256Mband512Mb

CIN VIN=0V

3 8 pF

Inputcapacitancefor1Gb 4 9 pF

Inputcapacitancefor2Gb 8 18 pF

Outputcapacitance COUT VOUT=0V 3 6 pF



32



19 DC Characteristics

Table 15: DC Current Characteristics

Parameter Symbol Conditions Min Typ Max Unit Notes

Inputleakagecurrent ILI 0V ≤ VIN ≤ VCC – – ±1 µA 1

Outputleakagecurrent ILO 0V ≤ VOUT ≤ VCC – – ±1 µA

VCCreadcurrent

RandomreadICC1

CE#=VIL,OE#=VIH,f=5MHz – 26 31 mA

Pageread CE#=VIL,OE#=VIH,f=13MHz – 12 16 mA

VCCstandbycurrent

256Mb

ICC2CE#=VCCQ±0.2V, RST#=VCCQ ±0 .2V

– 65 210 µA

512Mb – 70 225 µA

1Gb – 75 240 µA

2Gb – 150 480 µA

VCCprogram/erase/ blankcheckcurrent

ICC3Program/erasecontrolleractive

VPP/WP#=VIL or VIH – 35 50 mA 2

VPP/WP#=VPPH – 35 50 mA

VPPcurrent

ReadIPP1 VPP/WP#≤ VCC

– 0 .2 5 µA

Standby – 2 15 µA

Reset IPP2 RST#=VSS ±0 .2V – 0 .2 5 µA

PROGRAMoperationongoing

IPP3VPP/WP#=12V±5% – 0 .05 0 .10 mA

VPP/WP#=VCC – 0 .05 0 .10 mA

ERASEoperationongoing

IPP4VPP/WP#=12V±5% – 0 .05 0 .10 mA

VPP/WP#=VCC – 0 .05 0 .10 mA

Notes:

1. Themaximuminputleakagecurrentis±5μAontheVPP/WP#pin.

2. Sampledonly;not100%tested.



33



Table 16: DC Voltage Characteristics

Parameter Symbol Conditions Min Typ Max Unit Notes

InputLOWvoltage VIL VCC ≥ 2 .7V –0 .5 - 0 .8 V

InputHIGHvoltage VIH VCC ≥ 2 .7V 0 .7VCCQ - VCCQ + 0 .4 V

OutputLOWvoltage VOL

IOL=100μA,VCC=VCC,min,

VCCQ=VCCQ,min

0 .85VCCQ - 0 .15VCCQ V

OutputHIGHvoltage VOH

IOH=100μA,VCC=VCC,min,

VCCQ=VCCQ,min

- V

VoltageforVPP/WP#programacceleration VPPH - 11 .5 - 12 .5 V

Program/eraselockoutsupplyvoltage VLKO - 2 .3 - V 1

Note:




34



20 Read AC Characteristics

Table 17: Read AC Characteristics

ParameterSymbol

Condition Package Min Max Unit NotesLegacy JEDEC

Addressvalidtonextaddressvalid tRC tAVAV CE#=VIL,OE#=VILFortifiedBGA 100 – ns

TSOP 110 – ns

Addressvalidtooutputvalid tACC tAVQV CE#=VIL,OE#=VILFortifiedBGA – 100 ns

TSOP – 110 ns

Addressvalidtooutputvalid(page) tPAGE tAVQV1 CE#=VIL,OE#=VILFortifiedBGA – 25 ns

TSOP – 25 ns

CE#LOWtooutputtransition tLZ tELQX OE#=VILFortifiedBGA 0 – ns 1

TSOP 0 – ns 1

CE#LOWtooutputvalid tCE tELQV OE#=VILFortifiedBGA – 100 ns

TSOP – 110 ns

OE#LOWtooutputtransition tOLZ tGLQX CE#=VILFortifiedBGA 0 – ns 1

TSOP 0 – ns 1

OE#LOWtooutputvalid tOE tGLQV CE#=VILFortifiedBGA – 25 ns

TSOP – 25 ns

CE#HIGHtooutputHigh-Z tHZ tEHQZ OE#=VILFortifiedBGA – 20 ns 1

TSOP – 20 ns 1

OE#HIGHtooutputHigh-Z tDF tGHQZ CE#=VILFortifiedBGA – 15 ns 1

TSOP – 15 ns 1

CE#HIGH,OE#HIGH,oraddresstransitiontooutputtransition

tOH

tEHQX,tGHQX,tAXQX

–FortifiedBGA 0 – ns

TSOP 0 – ns

CE#LOWtoBYTE#LOW tELFL tELBL –FortifiedBGA – 10 ns

TSOP – 10 ns

CE#LOWtoBYTE#HIGH tELFH tELBH –FortifiedBGA – 10 ns

TSOP – 10 ns

BYTE#LOWtooutputvalid tFLQV tBLQV –FortifiedBGA – 1 μs

TSOP – 1 μs

BYTE#HIGHtooutputvalid tFHQV tBHQV –FortifiedBGA – 1 μs

TSOP – 1 μs

Note:




35



Figure 8: Random Read AC Timing (8-Bit Mode)Figure 19: Random Read AC Timing (8-Bit Mode)

Valid

Valid

tACC

tRC

tOH

tCE

tELFL

tLZ

tOH

tHZ

tOLZ tOH

tOE tDF

A[MAX:0]/A-1

CE#

OE#

DQ[7:0]

BYTE#

Figure 20: Random Read AC Timing (16-Bit Mode)

Valid

Valid

tACC

tRC

tOH

tCE

tELFH

tLZ

tOH

tHZ

tOLZ tOH

tOE tDF

A[MAX:0]

CE#

OE#

DQ[15:0]

BYTE#

256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR FlashRead AC Characteristics





Valid

Valid

tACC

tRC

tOH

tCE

tELFL

tLZ

tOH

tHZ

tOLZ tOH

tOE tDF

A[MAX:0]/A-1

CE#

OE#

DQ[7:0]

BYTE#


Valid

Valid

tACC

tRC

tOH

tCE

tELFH

tLZ

tOH

tHZ

tOLZ tOH

tOE tDF

A[MAX:0]

CE#

OE#

DQ[15:0]

BYTE#






36



Figure 10: BYTE# Transition Read AC TimingFigure 21: BYTE# Transition Read AC Timing

Data-out

Data-out

Valid

Valid

tACC tOH

tFHQV

tBLQX

High-Z

A[MAX:0]

A–1

BYTE#

DQ[7:0]

DQ[15:8]1

Figure 22: Page Read AC Timing

Valid

Valid Valid Valid ValidValid Valid Valid

tACC

tCE

tPAGE

tOH

tHZ

tOHtOE

tDF

A[MAX:4]

A[3:0]

CE#

OE#

DQ[15:0] Valid Valid Valid Valid Valid Valid Valid

Note: 1. Page size is 16 words (32 bytes) and is addressed by address inputs A[3:0] in x16 busmode and A[3:0] plus DQ15/A−1 in x8 bus mode.





Figure 21: BYTE# Transition Read AC Timing

Data-out

Data-out

Valid

Valid

tACC tOH

tFHQV

tBLQX

High-Z

A[MAX:0]

A–1

BYTE#

DQ[7:0]

DQ[15:8]1


Valid

Valid Valid Valid ValidValid Valid Valid

tACC

tCE

tPAGE

tOH

tHZ

tOHtOE

tDF

A[MAX:4]

A[3:0]

CE#

OE#

DQ[15:0] Valid Valid Valid Valid Valid Valid Valid

Note: 1. Page size is 16 words (32 bytes) and is addressed by address inputs A[3:0] in x16 busmode and A[3:0] plus DQ15/A−1 in x8 bus mode.




Note:

1. Pagesizeis16words(32bytes)andisaddressedbyaddressinputsA[3:0]inx16busmodeandA[3:0]plusDQ15/A−1inx8busmode.



37



21 Write AC Characteristics

Table 18: WE#-Controlled Write AC Characteristics

ParameterSymbol

Package Min Typ Max Unit NotesLegacy JEDEC

Addressvalidtonextaddressvalid tWC tAVAVFortifiedBGA 100 – – ns

TSOP 110 – – ns

CE#LOWtoWE#LOW tCS tELWLFortifiedBGA 0 – – ns

TSOP 0 – – ns

WE#LOWtoWE#HIGHtWP tWLWH FortifiedBGA 35 – – ns

TSOP 35 – – ns

InputvalidtoWE#HIGH tDS tDVWHFortifiedBGA 30 – – ns 1

TSOP 30 – – ns 1

WE#HIGHtoinputtransition tDH tWHDXFortifiedBGA 0 – – ns

TSOP 0 – – ns

WE#HIGHtoCE#HIGH tCH tWHEHFortifiedBGA 0 – – ns

TSOP 0 – – ns

WE#HIGHtoWE#LOW tWPH tWHWLFortifiedBGA 20 – – ns

TSOP 20 – – ns

AddressvalidtoWE#LOW tAS tAVWLFortifiedBGA 0 – – ns

TSOP 0 – – ns

WE#LOWtoaddresstransition tAH tWLAXFortifiedBGA 45 – – ns

TSOP 45 – – ns

OE#HIGHtoWE#LOW – tGHWLFortifiedBGA 0 – – ns

TSOP 0 – – ns

WE#HIGHtoOE#LOW tOEH tWHGLFortifiedBGA 0 – – ns

TSOP 0 – – ns

Program/erasevalidtoRY/BY#LOW tBUSY tWHRLFortifiedBGA – – 30 ns 2

TSOP – – 30 ns 2

VCCHIGHtoCE#LOW tVCS tVCHELFortifiedBGA 300 – – μs

TSOP 300 – – μs

WRITETOBUFFERPROGRAM opera-tion(512words)

tWHWH1 tWHWH1

FortifiedBGA – 900 – μs

TSOP – 900 – μs

PROGRAMoperation (singlewordorbyte)



Notes:

1. Theuser’swritetimingmustcomplywiththisspecification.AnyviolationofthiswritetimingspecificationmayresultinpermanentdamagetotheNORFlashdevice.




38



Figure 12: WE#-Controlled Program AC Timing (8-Bit Mode)Figure 23: WE#-Controlled Program AC Timing (8-Bit Mode)

AAAh PA PA

3rd Cycle 4th Cycle READ CycleData PollingtWC tWC

tAS

tWP

tDStWHWH1

tDF

tWPH

tAH

tCEtCS

tGHWL tOE

tDH

tOH

tCH

A[MAX:0]/A-1

CE#

OE#

WE#

DQ[7:0] A0h PD DQ7# DOUT DOUT

Notes: 1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-GRAM command is followed by checking of the data polling register bit and by a READoperation that outputs the data (DOUT) programmed by the previous PROGRAM com-mand.

2. PA is the address of the memory location to be programmed. PD is the data to be pro-grammed.

3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit[DQ7]).

4. See the following tables for timing details: Read AC Characteristics, WE#-ControlledWrite AC Characteristics, and CE#-Controlled Write AC Characteristics.

256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR FlashWrite AC Characteristics



Notes:

1. OnlythethirdandfourthcyclesofthePROGRAMcommandarerepresented.ThePROGRAMcommandisfollowedbycheckingofthedatapollingregisterbitandbyaREADoperationthatoutputsthedata(DOUT)programmedbythepreviousPROGRAMcommand.

2. PAistheaddressofthememorylocationtobeprogrammed.PDisthedatatobeprogrammed.

3. DQ7isthecomplementofthedatabitbeingprogrammedtoDQ7(SeeDataPollingBit[DQ7]).

4. Seethefollowingtablesfortimingdetails:ReadACCharacteristics,WE#-ControlledWriteACCharacteristics,andCE#-ControlledWriteACCharacteristics.



39



Figure 13: WE#-Controlled Program AC Timing (16-Bit Mode)Figure 24: WE#-Controlled Program AC Timing (16-Bit Mode)

555h PA PA

3rd Cycle 4th Cycle READ CycleData PollingtWC tWC

tAS

tWP

tDS

tDFtWHWH1

tWPH

tAH

tCEtCS

tGHWL tOE

tDH

tOH

tCH

A[MAX:0]

CE#

OE#

WE#

DQ[15:0] A0h PD DQ7# DOUT DOUT

Notes: 1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-GRAM command is followed by checking of the data polling register bit and by a READoperation that outputs the data (DOUT) programmed by the previous PROGRAM com-mand.







Notes:

1. OnlythethirdandfourthcyclesofthePROGRAMcommandarerepresented.ThePROGRAMcommandisfollowedbycheckingofthedatapollingregisterbitandbyaREADoperationthatoutputsthedata(DOUT)programmedbythepreviousPROGRAMcommand.






40



Table 19: CE#-Controlled Write AC Characteristics

ParameterSymbol

Package Min Typ Max Unit NotesLegacy JEDEC

Addressvalidtonextaddressvalid tWC tAVAVFortifiedBGA 100 – – ns

TSOP 110 – – ns

WE#LOWtoCE#LOW tWS tWLELFortifiedBGA 0 – – ns

TSOP 0 – – ns

CE#LOWtoCE#HIGH tCP tELEHFortifiedBGA 35 – – ns

TSOP 35 – – ns

InputvalidtoCE#HIGH tDS tDVEHFortifiedBGA 30 – – ns 1

TSOP 30 – – ns 1

CE#HIGHtoinputtransition tDH tEHDXFortifiedBGA 0 – – ns

TSOP 0 – – ns

CE#HIGHtoWE#HIGH tWH tEHWHFortifiedBGA 0 – – ns

TSOP 0 – – ns

CE#HIGHtoCE#LOW tCPH tEHELFortifiedBGA 20 – – ns

TSOP 20 – – ns

AddressvalidtoCE#LOW tAS tAVELFortifiedBGA 0 – – ns

TSOP 0 – – ns

CE#LOWtoaddresstransition tAH tELAXFortifiedBGA 45 – – ns

TSOP 45 – – ns

OE#HIGHtoCE#LOW – tGHELFortifiedBGA 0 – – ns

TSOP 0 – – ns

WRITETOBUFFERPROGRAM operation(512words)

tWHWH1 tWHWH1



PROGRAMoperation (singlewordorbyte)



Note:

1. Theuser’swritetimingmustcomplywiththisspecification.AnyviolationofthiswritetimingspecificationmayresultinpermanentdamagetotheNORFlashdevice.



41



Figure 14: CE#-Controlled Program AC Timing (8-Bit Mode)Figure 25: CE#-Controlled Program AC Timing (8-Bit Mode)

AAAh PA PA

3rd Cycle 4th Cycle Data PollingtWC

tAS

tCP

tDStWHWH1

tCPH

tAH

tWS

tGHEL

tDH

tWH

A[MAX:0]/A-1

WE#

OE#

CE#

DQ[7:0] A0h PD DQ7# DOUT

Notes: 1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-GRAM command is followed by checking of the data polling register bit.







Notes:

1. OnlythethirdandfourthcyclesofthePROGRAMcommandarerepresented.ThePROGRAMcommandisfollowedbycheckingofthedatapollingregisterbit.






42



Figure 15: CE#-Controlled Program AC Timing (16-Bit Mode)Figure 26: CE#-Controlled Program AC Timing (16-Bit Mode)

555h PA PA

3rd Cycle 4th Cycle Data PollingtWC

tAS

tCP

tDStWHWH1

tCPH

tAH

tWS

tGHEL

tDH

tWH

A[MAX:0]

WE#

OE#

CE#

DQ[15:0] A0h PD DQ7# DOUT

Notes: 1. Only the third and fourth cycles of the PROGRAM command are represented. The PRO-GRAM command is followed by checking of the data polling register bit.







Notes:

1. OnlythethirdandfourthcyclesofthePROGRAMcommandarerepresented.ThePROGRAMcommandisfollowedbycheckingofthedatapollingregisterbit.






43



Figure 16: Chip/Block Erase AC Timing (8-Bit Mode)Figure 27: Chip/Block Erase AC Timing (8-Bit Mode)

AAAh

tWC

tAS

tWP

tDS

tWPH

tAH

tCS

tGHWL

tDH

tCH

A[MAX:0]/A–1

CE#

OE#

WE#

DQ[7:0] AAh

555h AAAh AAAhBAh1555hAAAh

55h 55hAAh80h 10h/30h

Notes: 1. For a CHIP ERASE command, the address is 555h, and the data is 10h; for a BLOCK ERASEcommand, the address is BAd, and the data is 30h.

2. BAd is the block address.3. See the following tables for timing details: Read AC Characteristics, WE#-Controlled

Write AC Characteristics, and CE#-Controlled Write AC Characteristics.




Notes:

1. ForaCHIPERASEcommand,theaddressis555h,andthedatais10h;foraBLOCKERASEcommand,theaddressisBAd,andthedatais30h.

2. BAdistheblockaddress.




44



Figure 17: Chip/Block Erase AC Timing (16-Bit Mode)Figure 28: Chip/Block Erase AC Timing (16-Bit Mode)

555h

tWC

tAS

tWP

tDS

tWPH

tAH

tCS

tGHWL

tDH

tCH

A[MAX:0]

CE#

OE#

WE#

DQ[15:0] AAh

2AAh 555h 555hBAh12AAh555h

55h 55hAAh80h 10h/30h

Notes: 1. For a CHIP ERASE command, the address is 555h, and the data is 10h; for a BLOCK ERASEcommand, the address is BAd, and the data is 30h.

2. BAd is the block address.3. See the following tables for timing details: Read AC Characteristics, WE#-Controlled

Write AC Characteristics, and CE#-Controlled Write AC Characteristics.




Notes:

1. ForaCHIPERASEcommand,theaddressis555h,andthedatais10h;foraBLOCKERASEcommand,theaddressisBAd,andthedatais30h.

2. BAdistheblockaddress.




45



22 Accelerated Program, Data Polling/Toggle AC Characteristics

Table 20: Accelerated Program and Data Polling/Data Toggle AC Characteristics

ParameterSymbol

Min Max UnitLegacy JEDEC

VPP/WP#risingorfallingtime – tVHVPP 250 – ns

AddresssetuptimetoCE#orOE#LOW tASO tAXGL 15 – ns

AddressholdtimefromOE#orCE#HIGH tAHT tGHAX,tEHAX 0 – ns

CE#HIGHtime tEPH tEHEL2 30 – ns

WE#HIGHtoOE#log(toggleanddatapolling) tOEH tWHGL2 20 – ns

OE#HIGHtime tOPH tGHGL2 20 – ns

Program/erasevalidtoRY/BY#LOW tBUSY tWHRL – 90 ns

Note:


Figure 18: Accelerated Program AC Timing

Accelerated Program, Data Polling/Toggle AC Characteristics


Parameter

Symbol


VPP/WP# rising or falling time – tVHVPP 250 – ns

Address setup time to CE# or OE# LOW tASO tAXGL 15 – ns

Address hold time from OE# or CE# HIGH tAHT tGHAX, tEHAX 0 – ns

CE# HIGH time tEPH tEHEL2 30 – ns

WE# HIGH to OE# log (toggle and data polling) tOEH tWHGL2 20 – ns

OE# HIGH time tOPH tGHGL2 20 – ns

Program/erase valid to RY/BY# LOW tBUSY tWHRL – 90 ns



tVHVPPtVHVPP

VPPH

VIL or VIH

VPP/WP#

Figure 30: Data Polling AC Timing

DQ7#Data DQ7# Valid DQ7Data

Output flagData Output flag ValidDQ[6:0] Data

tHZ/tDFtCE

tOEtOPH

tCH

tBUSY

tOEH

CE#

OE#

WE#

DQ[6:0]

DQ7

RY/BY#

Notes: 1. DQ7 returns a valid data bit when the PROGRAM or ERASE command has completed.

256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR FlashAccelerated Program, Data Polling/Toggle AC Characteristics





46




Accelerated Program, Data Polling/Toggle AC Characteristics


Parameter

Symbol


VPP/WP# rising or falling time – tVHVPP 250 – ns

Address setup time to CE# or OE# LOW tASO tAXGL 15 – ns

Address hold time from OE# or CE# HIGH tAHT tGHAX, tEHAX 0 – ns

CE# HIGH time tEPH tEHEL2 30 – ns

WE# HIGH to OE# log (toggle and data polling) tOEH tWHGL2 20 – ns

OE# HIGH time tOPH tGHGL2 20 – ns

Program/erase valid to RY/BY# LOW tBUSY tWHRL – 90 ns



tVHVPPtVHVPP

VPPH

VIL or VIH

VPP/WP#


DQ7#Data DQ7# Valid DQ7Data

Output flagData Output flag ValidDQ[6:0] Data

tHZ/tDFtCE

tOEtOPH

tCH

tBUSY

tOEH

CE#

OE#

WE#

DQ[6:0]

DQ7

RY/BY#

Notes: 1. DQ7 returns a valid data bit when the PROGRAM or ERASE command has completed.




Notes:

1. DQ7returnsavaliddatabitwhenthePROGRAMorERASEcommandhascompleted.

2. Seethefollowingtablesfortimingdetails:ReadACCharacteristics,AcceleratedProgramandDataPolling/DataToggleACCharacteristics.



47



Figure 20: Toggle/Alternative Toggle Bit Polling AC Timing

2. See the following tables for timing details: Read AC Characteristics, Accelerated Pro-gram and Data Polling/Data Toggle AC Characteristics.

Figure 31: Toggle/Alternative Toggle Bit Polling AC Timing

Toggle Toggle ToggleData Stoptoggling

OutputValid

tBUSY

tOPH tEPH

tOEH

CE#

WE#

OE#

DQ6/DQ2

RY/BY#

tOPH

tAHT tASO

tAHT

tDH

tASO

A[MAX:0]/A–1

tOE tCE

Notes: 1. DQ6 stops toggling when the PROGRAM or ERASE command has completed. DQ2 stopstoggling when the CHIP ERASE or BLOCK ERASE command has completed.

2. See the following tables for timing details: Read AC Characteristics, Accelerated Pro-gram and Data Polling/Data Toggle AC Characteristics.




Notes:

1. DQ7returnsavaliddatabitwhenthePROGRAMorERASEcommandhascompleted.

2. Seethefollowingtablesfortimingdetails:ReadACCharacteristics,AcceleratedProgramandDataPolling/DataToggleACCharacteristics.



48



23 Program/Erase Characteristics

Table 21: Program/Erase Characteristics

Notes1and2applytotheentiretable.

Parameter Buffer Size Byte Word Min Typ Max Unit Notes

Blockerase(128KB) – – – – 0 .8 4 s

Erasesuspendlatencytime – – – – 27 37 μs

Blockerasetimeout – – – – – 50 μs

Byteprogram

Single-byteprogram – – – – 210 456 μs

Bytewritetobufferprogram

64 64 – – 270 716 μs

128 128 – – 310 900 μs

256 256 – – 375 1140 μs

Effectivewritetobufferprogramperbyte

64 1 – – 4 .22 11 .2 μs

128 1 – – 2 .42 7 μs

256 1 – – 1 .46 4 .45 μs

Wordprogram

Single-wordprogram – – – – 210 456 μs

Wordwritetobufferprogram

32 – 32 – 270 716 μs

64 – 64 – 310 900 μs

128 – 128 – 375 1140 μs

256 – 256 – 505 1690 μs

512 – 512 – 900 3016 μs

Effectivewritetobufferprogramperword

32 – 1 – 8 .44 22 .4 μs

64 – 1 – 4 .84 14 .1 μs

128 – 1 – 2 .93 8 .9 μs

256 – 1 – 1 .97 6 .6 μs

512 – 1 – 1 .76 5 .89 μs

Programsuspendlatencytime – – – – 27 37 μs

Blankcheck – – – – 3 .2 – ms

Setnonvolatileprotectionbittime – – – – 210 456 μs

Clearnonvolatileprotectionbittime – – – – 0 .8 4 s

PROGRAM/ERASEcycles(perblock) – – – 100,000 – – cycles

Erasetosuspend – – – – 500 – μs 3

Notes:

1. Typicalvaluesmeasuredatroomtemperatureandnominalvoltages.

2. Typicalandmaximumvaluesaresampled,butnot100%tested.

3. ErasetosuspendisthetypicaltimebetweenaninitialBLOCKERASEorERASERESUMEcommandandasubsequentERASESUSPENDcommand.Violatingthespecificationrepeatedlyduringanyparticularblockerasemaycauseerasefailures.



49



24 Package Dimensions

Figure 21: 64-Ball Fortified BGA – 11mm x 13mmFigure 33: 64-Ball Forti�ed BGA – 11mm x 13mm

Seatingplane

0.80 TYP

0.10

13.00 ±0.10

0.60 ±0.05

1.00TYP

3.00TYP

A

B

C

D

E

F

G

H

7.00 TYP

1.40 MAX1.00TYP

2.00 TYP 0.48 ±0.05

11.00 ±0.10

7.00 TYP

64X

8 7 6 5 4 3 2 1

Notes: 1. All dimensions are in millimeters.2. Only 2Gb (1Gb/1Gb) has A1 mark at the bottom.

256Mb, 512Mb, 1Gb, 2Gb: 3V Embedded Parallel NOR FlashPackage Dimensions

PDF: 09005aef849b4b09m29ew_256mb_2gb.pdf - Rev. C 9/14 EN 75 Micron Technology, Inc. reserves the right to change products or speci�cations without notice.


Notes:

1. Alldimensionsareinmillimeters.



50



25 Ordering Information

Table 22: Ordering Information

Part Number Device Grade

MYX28F00AM29EWHBG-ITRL Industrial



51



Document Title

1Gb - 64M x 16 Parallel NOR Flash Embedded Memory

Revision History

Revision # History Release Date Status

1 .0 Initialrelease November14,2014 Preliminary

1gb parallel nor flash - micross components ecommerce system · 8 read and auto select ... internal...

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