1/8/2007 - l23 project step 9 - sequential machine copyright 2006 - joanne degroat, ece, osu1...

1/8/2007 - L23 Project Step 9 - Sequential Machine

Copyright 2006 - Joanne DeGroat, ECE, OSU 1

Project Step 9 Beyond the ALU and Datapath.

Sequential Machine Modeling exercise.



The sequential machine modeling style In the lecture on state machine modeling

introduces how three processes can be used to model the state machine.

This style is good for documentation, simulation, and synthesis.

And it also maps across multiple HDLs.



The machine to be modeled This exercise is to model a Successive

Approximation A-to-D converter. This also introduces the ability of VHDL to

model mixed signal systems at a high level of abstraction.



More on the controller Modeling to the

SAR Controller and SAR Control Register This is the heart of

a successive approximation A-to-D unit

SAR

SAR Controller/Reg.

D to A converter

8analog input

over_under

start

sarclk

eoc

sar_val 8digital_val



Analog units D-to-A converter is

analog Analog comparator for

comparison of value to the input

These units are modeled in the testbench algorithmically

SAR

SAR Controller/Reg.

D to A converter

8analog input

over_under

start

sarclk

eoc

sar_val 8digital_val



The digital portion You are to model the digital portion Inputs

An over/under signal a 1 indicates the value generated by the SAR is

currently too high A 0 indicates the value generated by the SAR is too

low Start – begin a new conversion. The analog value

has been captured. sarclk – the clock for the unit



The digital portion -2 The outputs

eoc indicator signal line – indicates the end of the conversion and that the value on digital_val is valid

digital_val – the 8-bit digital conversion value sar_val – an 8-bit output that is sent to the D-to-A

converter internal to the entire unit

Note that part of the entire unit is modeled by the testbench. The assignment is only modeling of the controller, the digital portion.



Conversion basics The input range is 0-5Volts Starting state for converter state machine

(1st approximation) is 1000 0000 or 2.5V If this is less than input the next bit is set to 1,

1100 0000 and again a comparison is made. If this is greater than the input the bit is set 0

before the next bit position is set to 1, 0100 0000



Conversion example 1 Input 4.3 V Start 1000 0000 = 2.5

Under so keep NS 1100 0000 = 3.75

Under so keep NS 1110 0000 = 4.375

Over so revert to 0 NS 1101 0000 =

4.0675 Under so keep

NS 1101 1000 = 4.22625 Under so keep

NS 1101 1100 = 4.305625 Over so revert

NS 1101 1010 = 4.2659375 Under so keep

NS 1101 1011 = 4.28578125 Under so keep

Result is 1101 1011 EOC asserted



State machine State machine has multiple states

Ready to convert S1, S2, S3, S4, S5, S6, S7 while converting EOC – done converting



Notes on operation Notes on operation

Start will transition high when the analog input is valid and remains high during the conversion

EOC is asserted and system asserting start will de-assert it Once start returns low, EOC is to be reset.

DO NOT SIMULATE UNTIL time’high TESTBENCH NEVER GOES QUIESENT Testbench has a free running clock, sarclk run 20 us instead

The Waveform



1/8/2007 - l23 project step 9 - sequential machine copyright 2006 - joanne degroat, ece, osu1...

Documents