1/8/2007 - l17 resolved siganlscopyright 2006 - joanne degroat, ece, osu1 resolved signals what are...

1/8/2007 - L17 Resolved Siganls Copyright 2006 - Joanne DeGroat, ECE, OSU 1

Resolved SignalsWhat are resolved signals and how do they work.

Resolution??? Isn’t that for solving conflicts???

1/8/2007 - L17 Resolved Siganls

Copyright 2006 - Joanne DeGroat, ECE, OSU 2

Overview – Resolved Signals Why resolved signals? Steps to creating a resolved signal in VHDL Resolution Functions



Busses and Wires What is the difference between a bus and a wire? Wires – have only one driving source

wires



Busses and Wires Busses on the other hand

can be driven by one or more sources

In both cases there can be more than one destination for the signal

With busses, only the device acting as source will actually drive a value. All others will have their output set at high impedance (Z).

ENB

ENB

ENB



How do you handle Busses in an HDL? First must consider the information present on

a wire and on a bus in a digital circuit. Information present on a wire:

Wire is limited to 2 states using TYPE BIT High or 1 or ‘1’ Low or 0 or ‘0’ There is a transition period between the two but

High and Low are the only 2 stable states.



Information on a Bus Possible state for a BUS

Driven high (driven to a 1) Driven low (driven to a 0) No driving value (Z or high impedance) Capacitive high (H) Capacitive low (L) Conflict (one driver driving it to a 1, another a 0) (X) Conflict of capacitive values (W)

And other useful values U – Uninitialized – - a Don’t Care



In an HDL need Resolution With multiple drivers of a signal how do you

resolve the value seen by devices using the bus?

RESOLUTION How to determine the value when two or more

drivers are driving the same signal Must look at all drivers and determine the

appropriate value to use.



Step needed in VHDL Declare a type for the multi-value logic system

type mv4_logic is (‘X’,’Z’,’0’,’1’): type mv4_logic_vector is array (natural range <>) of mv4_logic;

Then declare a resolution function function resolved (s:mv4_logic_vector) RETURN mv4_logic;

And then the resolved signal subtype mv4r_logic is resolved mv4_logic; type mv4r_logic_vector is array (natural range <>) of mv4r_logic;

Note that you need to use a subtype declaration to incorporate the resolution function.

So there will be both a resolved and unresolved type for the multi-value system



Type and Subtype Declaration BNF

type_declaration::= full_type_declaration | incomplete_type_declaration full_type_declaration::= TYPE identifier IS type_definition incomplete_type_definition::= TYPE identifier type_definition::= scalar_type_definition | composite_type_definition | access_type_definition | file_type_definition

Can follow the BNF for a TYPE definition but find no resolution function here



Type and Subtype Declaration BNF It is, however, in the SUBTYPE definition

subtype_declaration::= SUBTYPE identifier IS subtype_indication subtype_indication::=[resolution_function_name] type_mark [constraint] type_mark::= type_name | subtype_name constraint::= range_constraint | index_constraint



VHDL specification cont. Had declaration for a function resolved

function resolved(s : mv4_logic_vector) RETURN mv4_logic; Then the body of the resolution function is given in the package body

where you will find: TYPE mv4_logic_table IS array (mv4_logic,mv4_logic) of mv4_logic; CONSTANT resolution_table : mv4_logic_table :=( -- --------------------------------- -- | X Z 0 1 | | -- --------------------------------- ( ‘X’, ‘X’, ‘X’, ‘X’ ), --| X | ( ‘X’, ‘Z’, ‘0’, ‘1’ ), --| Z | ( ‘X’, ‘0’, ‘0’, ‘X’ ), --| 0 | ( ‘X’, ‘1’, ‘X’, ‘1’ )); --| 1 |

And having the resolution table can write the body of the resolution func.



The resolution function function resolved (s : mv4_logic_vector) RETURN mv4_logic IS variable result : mv4_logic := Z; – weakest state BEGIN IF (s’length = 1) then return s(s’low) ELSE FOR i IN s’range LOOP result := resolution_table(result,s(i)); END LOOP; END IF; return result; END resolved;

Execution could be shortened by adding exit when result=‘X’



The big picture After posting of a

transaction(s) to the current value of one or more of the drivers, a vector composed of the current values of the drivers is sent to the resolution function for determination of the resolved value.

1st Process for a <= equation ….1st Driver for a

CV ‘Z’ t

2nd Process for a <= 2nd equation ….2nd Driver for a

CV ‘0’ t

nth Process for a <= nth equation ….nth Driver for a

CV ‘Z’ t

* * *

ResolvedValue



Completeness of a MVL package Having a MVL type with resolution is only

part of creating a MVL system. ALSO need

Overloaded function for standard operators Type conversion functions to convert from other

type to this type and the reverse ieee_1164 standard MVL package is a

standard package for a multi-value logic system and contains all of these.



Example of overloading for our 4 state logic system In the declarative part of the MVL package

function “and” (l,r : mv4_logic) RETURN mv4_logic; In the body of the package for this MVL

type mv4logic_table is array (mv4_logic,mv4_logic) of mv4_logic; CONSTANT and_table : mv4logic_table := ( -- --------------------------------- -- | X Z 0 1 | | -- --------------------------------- ( ‘X’, ‘X’, ‘0’, ‘X’ ), --| X | ( ‘X’, ‘X’, ‘0’, ‘X’ ), --| Z | ( ‘0’, ‘0’, ‘0’, ‘0’ ), --| 0 | ( ‘X’, ‘X’, ‘0’, ‘1’ )); --| 1 | function “and” (l,r : mv4_logic) RETURN mv4_logic IS BEGIN return (and_table(l,r)); END “and”;



Use of Resolved signals Must use a resolved signal

type for any signals of mode INOUT PORT ( ABUS : INOUT

mv4r_logic; …

Within an ARCHITECTURE they are needed whenever the signal will have more than one driver

ARCHITECTURE abcd OF wxyz IS … SIGNAL a,b,c : mv4r_logic; …BEGIN a <= ‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns;

p1: process begin a <= ‘Z’; wait … end process;

p2: process begin a <= ‘0’; wait … end process;END abcd;

Driver 1 of a

Driver 2 of a

Driver 3 of a



Standard logic 1164 Package is online in the

course directory Opens with comments

on the code

What is the first part of declaring an MVL system in a package?

-- -------------------------------------------------------------------- -- -- Title : std_logic_1164 multi-value logic system -- Library : This package shall be compiled into a library -- : symbolically named IEEE. -- : -- Developers: IEEE model standards group (par 1164) -- Purpose : This packages defines a standard for designers -- : to use in describing the interconnection data types -- : used in vhdl modeling. -- : -- Limitation: The logic system defined in this package may -- : be insufficient for modeling switched transistors, -- : since such a requirement is out of the scope of this -- : effort. Furthermore, mathematics, primitives, -- : timing standards, etc. are considered orthogonal -- : issues as it relates to this package and are therefore -- : beyond the scope of this effort. -- : -- Note : No declarations or definitions shall be included in, -- : or excluded from this package. The "package declaration" -- : defines the types, subtypes and declarations of -- : std_logic_1164. The std_logic_1164 package body shall be -- : considered the formal definition of the semantics of -- : this package. Tool developers may choose to implement -- : the package body in the most efficient manner available -- : to them. -- : -- -------------------------------------------------------------------- -- modification history : -- -------------------------------------------------------------------- -- version | mod. date:| -- v4.200 | 01/02/92 | -- --------------------------------------------------------------------



Declaration Part of the Package Declare MVL logic

system types Declare the resolution

function Declare the resolved

type And declare the array

types for vectors Declare subtype of

reduced logic systems

PACKAGE std_logic_1164 IS ------------------------------------------------------------------- -- logic state system (unresolved) ------------------------------------------------------------------- TYPE std_ulogic IS ( 'U', -- Uninitialized 'X', -- Forcing Unknown '0', -- Forcing 0 '1', -- Forcing 1 'Z', -- High Impedance 'W', -- Weak Unknown 'L', -- Weak 0 'H', -- Weak 1 '-' -- Don't care ); ------------------------------------------------------------------- -- unconstrained array of std_ulogic for use with the resolution function ------------------------------------------------------------------- TYPE std_ulogic_vector IS ARRAY ( NATURAL RANGE <> ) OF std_ulogic; ------------------------------------------------------------------- -- resolution function ------------------------------------------------------------------- FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic; ------------------------------------------------------------------- -- *** industry standard logic type *** ------------------------------------------------------------------- SUBTYPE std_logic IS resolved std_ulogic; ------------------------------------------------------------------- -- unconstrained array of std_logic for use in declaring signal arrays ------------------------------------------------------------------- TYPE std_logic_vector IS ARRAY ( NATURAL RANGE <>) OF std_logic; ------------------------------------------------------------------- -- common subtypes ------------------------------------------------------------------- SUBTYPE X01 IS resolved std_ulogic RANGE 'X' TO '1'; -- ('X','0','1') SUBTYPE X01Z IS resolved std_ulogic RANGE 'X' TO 'Z'; -- ('X','0','1','Z') SUBTYPE UX01 IS resolved std_ulogic RANGE 'U' TO '1'; -- ('U','X','0','1') SUBTYPE UX01Z IS resolved std_ulogic RANGE 'U' TO 'Z'; -- ('U','X','0','1','Z')



Overload operators All operators are

overloaded Can find the package in

~degroat/ee762_assign/std_1164.vhd

------------------------------------------------------------------- -- overloaded logical operators ------------------------------------------------------------------- FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01; -- function "xnor" ( l : std_ulogic; r : std_ulogic ) return ux01; FUNCTION "not" ( l : std_ulogic ) RETURN UX01; ------------------------------------------------------------------- -- vectorized overloaded logical operators ------------------------------------------------------------------- FUNCTION "and" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "and" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "nand" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nand" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "or" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "or" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "nor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "nor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; FUNCTION "xor" ( l, r : std_logic_vector ) RETURN std_logic_vector; FUNCTION "xor" ( l, r : std_ulogic_vector ) RETURN std_ulogic_vector; -- ----------------------------------------------------------------------- -- Note : The declaration and implementation of the "xnor" function is -- specifically commented until at which time the VHDL language has been -- officially adopted as containing such a function. At such a point, -- the following comments may be removed along with this notice without -- further "official" ballotting of this std_logic_1164 package. It is -- the intent of this effort to provide such a function once it becomes -- available in the VHDL standard. -- ----------------------------------------------------------------------- -- function "xnor" ( l, r : std_logic_vector ) return std_logic_vector; -- function "xnor" ( l, r : std_ulogic_vector ) return std_ulogic_vector; FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector; FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector;



Type conversion functions and edge detection To convert from built

in logic types of BIT and BIT_VECTOR

And there are similar conversion functions for the reduced logic systems

Also have functions for rising and falling edge

------------------------------------------------------------------- -- conversion functions ------------------------------------------------------------------- FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT; FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR; FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR; FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic; FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector; FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector; FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector; FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector;

------------------------------------------------------------------- -- edge detection ------------------------------------------------------------------- FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN; FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN;



Now have the package body Starts with a header First code is for the

resolution function

Note initial state Note sink state

Sink state is state that overrides all others

PACKAGE BODY std_logic_1164 IS ------------------------------------------------------------------- -- local types ------------------------------------------------------------------- TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic; TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic; ------------------------------------------------------------------- -- resolution function ------------------------------------------------------------------- CONSTANT resolution_table : stdlogic_table := ( -- --------------------------------------------------------- -- | U X 0 1 Z W L H - | | -- --------------------------------------------------------- ( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X | ( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 | ( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z | ( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L | ( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H | ( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - | ); FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS VARIABLE result : std_ulogic := 'Z'; -- weakest state default BEGIN -- the test for a single driver is essential otherwise the -- loop would return 'X' for a single driver of '-' and that -- would conflict with the value of a single driver unresolved -- signal. IF (s'LENGTH = 1) THEN RETURN s(s'LOW); ELSE FOR i IN s'RANGE LOOP result := resolution_table(result, s(i)); END LOOP; END IF; RETURN result; END resolved;



The various functions The AND table The OR table

------------------------------------------------------------------- -- tables for logical operations ------------------------------------------------------------------- -- truth table for "and" function CONSTANT and_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W | ( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H | ( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - | ); -- truth table for "or" function CONSTANT or_table : stdlogic_table := ( -- ---------------------------------------------------- -- | U X 0 1 Z W L H - | | -- ---------------------------------------------------- ( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 | ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W | ( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L | ( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H | ( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | - | );



For operation on single logic values and vectors Single values and

vectors

------------------------------------------------------------------- -- overloaded logical operators ( with optimizing hints ) ------------------------------------------------------------------- FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (and_table(l, r)); END "and"; FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (not_table ( and_table(l, r))); END "nand"; FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS BEGIN RETURN (or_table(l, r)); END "or";

------------------------------------------------------------------- -- and ------------------------------------------------------------------- FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'and' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := and_table (lv(i), rv(i)); END LOOP; END IF; RETURN result; END "and"; --------------------------------------------------------------------- FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l; ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r; VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ); BEGIN IF ( l'LENGTH /= r'LENGTH ) THEN ASSERT FALSE REPORT "arguments of overloaded 'and' operator are not of the same length" SEVERITY FAILURE; ELSE FOR i IN result'RANGE LOOP result(i) := and_table (lv(i), rv(i)); END LOOP; END IF; RETURN result; END "and";



Example of transactions on resolved values The model Note that there is a

resolved signal res that is driver both by a concurrent signal assignment statement and in a process. Each is a driver.

Even though the process has two statements that generate transactions for res, it is one driver of res.

ENTITY ex1 IS END ex1; -- the entity LIBRARY ieee; USE ieee.std_logic_1164.all; ARCHTIECTURE one OF ex1 IS SIGNAL res : std_logic; -- res is a resolved signal BEGIN -- concurrent signal assignment statement for signal res -- this concurrent signal assignment statement is driver 1 res <= ‘0’ after 1 ns, ‘1’ after 10 ns, ‘0’ after 20 ns; -- this process assigns values to res and is driver 2 PROCESS BEGIN WAIT FOR 5 ns; res <= ‘L’ after 1 ns; WAIT FOR 20 ns; res <= ‘1’ after 1 ns; END PROCESS; END one;



Time 0- and time 0 At startup simulate

each process till it suspends

Each driver is set to the initial value of ‘U’

Concurrent stmt is driver 1 of res and generates the transactions shown

The process immediately suspends until 5 ns

res

‘U’

‘U’

Dr1

Dr2 ‘U’

0

Dr1

Dr2

CV – ‘U’(‘0’,1ns)(‘1’,10ns)(‘0’,20ns)

CV – ‘U’



Advance time till time when something occurs = 1 ns At 1 ns driver 1 (the

concurrent stmt) goes to a value of ‘0’

Resolved value is still a ‘U’

res

‘U’

‘U’

Dr1

Dr2 ‘U’

0

Dr1

Dr2

CV – ‘0’(‘1’,10ns)(‘0’,20ns)

CV – ‘U’

1

‘0’



Avdance time to 5 ns when the process resumes Process generates

transaction of an ‘L’ for res at 6 ns

Process then suspends until 25 ns

res

‘U’

‘U’

Dr1

Dr2 ‘U’

0

Dr1

Dr2

CV – ‘0’(‘1’,10ns)(‘0’,20ns)

CV – ‘U’

1

‘0’

5

CV – ‘U’(‘L’,6ns)



Advance time to 6 ns Transaction on

driver 2 becomes the current value on driver 2

Re-evaluate resolution fucntion

res

‘U’

‘U’

Dr1

Dr2 ‘U’

0

Dr1

Dr2

CV – ‘0’(‘1’,10ns)(‘0’,20ns)

CV – ‘U’

1

‘0’

5

CV – ‘U’(‘L’,6ns)

6

CV – ‘L’

L

‘U’ ‘0’



Advance time to next time Process is

suspended until 25 ns

Transaction on Driver 1 at 10 ns

Advance time to 10 ns and post transaction and re-evaluate resolution function

res

‘U’

‘U’

Dr1

Dr2 ‘U’

0

Dr1

Dr2

CV – ‘0’(‘1’,10ns)(‘0’,20ns)

CV – ‘U’

1

‘0’

5

CV – ‘U’(‘L’,6ns)

6

CV – ‘L’

L

‘U’ ‘0’

10

CV – ‘1’(‘0’,20ns)

‘1’

‘1’



Advance time to next time at which something occurs At 20 ns last

transaction for Driver 1 is posted

Process is suspended until 25 ns

res

‘U’

‘U’

Dr1

Dr2 ‘U’

0

Dr1

Dr2

CV – ‘0’(‘1’,10ns)(‘0’,20ns)

CV – ‘U’

1

‘0’

5

CV – ‘U’(‘L’,6ns)

6

CV – ‘L’

L

‘U’ ‘0’

10

CV – ‘1’(‘0’,20ns)

‘1’

‘1’

20

CV – ‘0’

‘0’

‘0’



Adance time again, to 25 ns At 25 ns process resumes Generates transaction for res of (‘1’,26ns) Process then suspens until 30 ns



Advance to 26 ns Post a value of

‘1’ to res Now resolving a

‘0’ with a ‘1’ Simulation never

goes quiescent as the process will always be waiting

res

‘U’

‘U’

Dr1

Dr2 ‘U’

0

Dr1

Dr2

CV – ‘0’(‘1’,10ns)(‘0’,20ns)

CV – ‘U’

1

‘0’

5

CV – ‘U’(‘L’,6ns)

6

CV – ‘L’

L

‘U’ ‘0’

10

CV – ‘1’(‘0’,20ns)

‘1’

‘1’

20

CV – ‘0’

‘0’

‘0’

25 26

CV – ‘1’CV – ‘L’(‘1’,26ns)

‘1’

‘X’



A 2nd example of transactions on resolved values The model is similar to the

first Again there is a resolved

signal res that is driver both by a concurrent signal assignment statement and in a process. Each is a driver. However, this time res is initialized to ‘1’

Again there are two drivers of res

ENTITY ex2 IS END ex2; -- the entity LIBRARY ieee; USE ieee.std_logic_1164.all; ARCHTIECTURE one OF ex2 IS SIGNAL res : std_logic :=’1’; -- res is a resolved signal BEGIN -- this concurrent signal assignment statement is driver 1 res <= ‘0’ after 1 ns, ‘1’ after 10 ns, ‘0’ after 20 ns; -- this process assigns values to res and is driver 2 -- and slightly different from the process in ex1 PROCESS BEGIN res <= ‘Z’ after 2 ns; WAIT FOR 5 ns; res <= ‘L’ after 25 ns; WAIT FOR 20 ns; res <= ‘1’ after 1 ns; END PROCESS; END one;



Time 0- and time 0 At startup simulate

each process till it suspends

Each driver is set to the initial value of ‘1’

Concurrent stmt is driver 1 of res and generates the transactions shown

Process generates the signal transaction, suspends until 5 ns

res

‘1’

‘1’

Dr1

Dr2 ‘1’

0

Dr1

Dr2

CV – ‘1’(‘0’,1ns)(‘1’,10ns)(‘0’,20ns)

CV – ‘1’(Z,2ns)



Advance time till time when something occurs = 1 ns At 1 ns driver 1 (the

concurrent stmt) goes to a value of ‘0’

Resolved value is now an ‘X’

res

‘1’

‘1’

Dr1

Dr2 ‘1’

0

Dr1

Dr2

CV – ‘0’(‘1’,10ns)(‘0’,20ns)

CV – ‘1’(Z,2ns)

1

‘0’

‘X’



Advance time till time when something occurs = 2 ns At 2 ns driver 2, the

process, is updated with a value of ‘Z’ for res.

Resolved value is now an ‘0’

Still have process suspended until 5ns

res

‘1’

‘1’

Dr1

Dr2 ‘1’

0

Dr1

Dr2

CV – ‘0’(‘1’,10ns)(‘0’,20ns)

1

‘0’

‘X’

2

‘Z’

‘0’

CV – ‘Z’



Avdance time to 5 ns when the process resumes Process generates

transaction of an ‘L’ for res after 25 ns or 30 ns into simulation


res

‘1’

‘1’

Dr1

Dr2 ‘1’

0

Dr1

Dr2

CV – ‘0’(‘1’,10ns)(‘0’,20ns)

1

‘0’

‘X’

2

‘Z’

‘0’

CV – ‘Z’(‘L’,30ns)

5



Advance time to 10 ns Posting

transaction on Driver 1.

Re-evaluate resolution fucntion

Process 2 still suspeneded until 25 ns.

res

‘1’

‘1’

Dr1

Dr2 ‘1’

0

Dr1

Dr2

1

‘0’

‘X’

2

‘Z’

‘0’

CV – ‘Z’(‘L’,30ns)

5 10

CV – ‘1’(‘0’,20ns)

‘1’

‘1’



Advance time to next time, 20 ns Post transaction

on Driver 1 Process still

suspended till 25ns

res

‘1’

‘1’

Dr1

Dr2 ‘1’

0

Dr1

Dr2

1

‘0’

‘X’

2

‘Z’

‘0’

CV – ‘Z’(‘L’,30ns)

5 10

CV – ‘0’

‘1’

‘1’

20

‘0’



Advance time to next time, 25 ns Time resume

process First generate a

transaction of res(‘1’,26ns) This is before the

transaction on the project output waveform so that old transaction is deleted and this new transaction posted.

res

‘1’

‘1’

Dr1

Dr2 ‘1’

0

Dr1

Dr2

1

‘0’

‘X’

2

‘Z’

‘0’

CV – ‘Z’(‘1’,26ns)

5 10

CV – ‘0’

‘1’

‘1’

20

‘0’

25



Advance time to next time, 25 ns Process continues at

top and executes res<=‘Z’ after 5 ns;

Generates transaction res(‘Z’,27ns)

Now must add this transaction to driver 2


res

‘1’

‘1’

Dr1

Dr2 ‘1’

0

Dr1

Dr2

1

‘0’

‘X’

2

‘Z’

‘0’

CV – ‘Z’(‘1’,26ns)

5 10

CV – ‘0’

‘1’

‘1’

20

‘0’

25



Adding transaction to driver 2 Run the algorithm for posting transactions to

drivers (Lect 16). Step 1 no at or after to delete Step2 – append the transaction

POW – CV - res(‘1’,26ns) - res(‘Z’,27ns) Now run part II of the algorithm



Part II of the Update algorithm Step 1 - Mark new transactions

POW – CV - res(‘1’,26ns) - Xres(‘Z’,27ns) Step 2 - An old transaction is marked if it immediately

precedes a marked transactions and its value component is the same as that of the marked transaction. Here the values are different so it is not marked POW – CV - res(‘1’,26ns) - Xres(‘Z’,27ns)

Step 3 – The CV is marked POW – xCV - res(‘1’,26ns) - Xres(‘Z’,27ns)

Step 3 – All unmarked are deleted POW – CV - res(‘Z’,27ns)



Resulting inres

‘1’

‘1’

Dr1

Dr2 ‘1’

0

Dr1

Dr2

1

‘0’

‘X’

2

‘Z’

‘0’

CV – ‘Z’(‘Z’,27ns)

5 10

CV – ‘0’

‘1’

‘1’

20

‘0’

25



Advance time to 27ns Post transaction on

Driver 2 Process suspended

until 30 ns As values assigned

by process will result in no change of value will end here.

res

‘1’

‘1’

Dr1

Dr2 ‘1’

0

Dr1

Dr2

1

‘0’

‘X’

2

‘Z’

‘0’

CV – ‘Z’

5 10

CV – ‘0’

‘1’

‘1’

20

‘0’

25 27

1/8/2007 - l17 resolved siganlscopyright 2006 - joanne degroat, ece, osu1 resolved signals what are...

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