1/8/2007 - l20 project step 8 - data path copyright 2006 - joanne degroat, ece, osu1 state machine...

1/8/2007 - L20 Project Step 8 - Data Path

Copyright 2006 - Joanne DeGroat, ECE, OSU 1

State Machine Design with an HDL A methodology that works for documenting the design, simulation and verification of the design, and synthesis for FPGA, or a custom ASIC generated using synthesis.



Lecture overview State machine basics HDL methodology State machine example



State Machine Basics In basic digital designs there are two fundamental

ways that state machines are implemented Mealy Machine

Outputs are a function of the current state and the inputs

NextStateLogic

StateMemory(F/Fs)

OutputLogic

OutputsInputs

CurrentState

Excitation(next state)

Mealy Machine

clk



State Machine Basics Moore Machine

Outputs are a function of the current state only

NextStateLogic

StateMemory(F/Fs)

OutputLogic

OutputsInputs

CurrentState

Excitation(next state)

Moore Machine

clk



HDL code Coding a state machine in an HDL

Can simply implement an algorithm Documents poorly Cannot be synthesized

Can code for a Mealy or Moore machine in a single process Documents poorly Synthesis results are unpredictable

Can follow a structured style Documents very well Synthesizes very well and predictable

Simulation of the three possibilities is ~ the same



The coding style The style applies to any HDL – VHDL, Verilog,

System C Documents well Easily maintainable – excellent during development

as changes are easily made Style maps to physical logic – using this style can

predict the number of state elements that should be produced by systhesis

All three styles on the last slide simulate equally well, but this style also synthesizes well.



Style guide Use a process to describe the next state logic. Often

in the form of a case statement. Will see this in the example.

Use a process to representing the latching/loading of the calculated next_state such that it becomes the current_state. This is the only process that generate sequential elements (F/Fs). The other processes represent combinational logic.

Use a third process to represent the generation of the outputs. This process will have inputs of the current state and, depending on the type of state machine, the inputs.



An example The T-Bird tail light problem

The turn signal indicator had a light sequence on each lamp.



State machine description State Diagram and Transition table Output is associated with state



Design with HDL You still start with a state diagram You may or may not generate a transition

table

Will now look at the code Where to start – THE INTERFACE

What are the inputs and the outputs?



The Entity Inputs are a signal for

Right turn signal Left turn signal Hazard Clock

Outputs are the signals for the lights lc, lb, la rc, rb, ra



The Entity Inputs are a signal for

Right turn signal Left turn signal Hazard Clock

Outputs are the signals for the lights lc, lb, la rc, rb, ra

ENTITY t_bird IS PORT (rts,lts,haz : IN BIT; clk : IN BIT; lc,lb,la : OUT BIT; ra,rb,rc : OUT BIT); END t_bird;



The architecture Will use 3 processes Start of architecture and the process to specify the F/Fs is

given here.ARCHITECTURE state_machine OF t_bird IS

TYPE state_type IS (idle,l1,l2,l3,r1,r1,r3,lr3); SIGNAL state, next_state : state_type; BEGIN --Process to Specify F/F PROCESS BEGIN WAIT UNTIL clk=’1’ AND clk’event; state <= next_state; END PROCESS;



Notes on start of architecture Signal declaration for the state machine state

First declare and enumeration type that has an element for each state of the state machine Here- idle, l1,l2,l3, r1,r2,r3, lr3

Then declare signals state and next_state to be of this type.

An aside: you can count the number of elements in this type to see that number of states and predict the number of F/Fs the state machine requires.



The F/F process Have a process that specifies latching the next_state

into the signal state. This process will synthesize into F/Fs Process specifies that this happens on the clock edge. Note that state and next_state have an initial state of

idle. Process will hold waiting for an edge on the clock

signal clk



The next state process The second of the

processes for the state machine.

What is the next state given the current state and the state of the input signals

Process can be of considerable size

-- Next State Logic Process PROCESS (state,lts,rts,haz) BEGIN CASE state IS WHEN idle => IF (haz=’1’ OR (lts=’1’ AND rts=’1’) THEN next_state <= lr3; ESLIF(haz=”0’ AND (lts=’0’ AND rts=’1’)) THEN next_state <= r1; ELSIF(haz=’0’ AND (lts=’1’ AND rts=’0’)) THEN next_state <= l1; ELSE next_state <= idle; END IF;

Continued on next slide



The next state process Continued Note that a case is

used to switch to actions based on the current_state

Then the value of the inputs directs the next_state for the state machine

WHEN l1 => IF (haz = ‘1’) THEN next_state <= lr3; ELSE next_state <= l2; END IF; WHEN l2 => IF (haz = ‘1’) THEN next_state <= lr3; ELSE next_state <= l3; END IF; WHEN l3 => next_state <= idle; WHEN r1 => IF (haz = ‘1’) THEN next_state <= lr3; ELSE next_state <= r2; END IF;

WHEN r2 => IF (haz = ‘1’) THEN next_state <= lr3; ELSE next_state <= r3; END IF; WHEN r3 => next_state <= idle; WHEN lr3 => next_state <= idle; END CASE; END PROCESS;



The output process Use a separate process

to specify the outputs In this case there is a

specific set of outputs for each state.

The outputs are only dependent on the state which makes this a Moore Machine

-- State Machine Outputs Process PROCESS (state) BEGIN CASE state IS WHEN idle =>

lc<=’0’;lb<=’0’;la<=’0’;ra<=’0’;rb<=’0’;rc<=’0’; WHEN l1 =>



lc<=’1’;lb<=’1’;la<=’1’;ra<=’0’;rb<=’0’;rc<=’0’; WHEN r1 =>



lc<=’0’;lb<=’0’;la<=’0’;ra<=’1’;rb<=’1’;rc<=’1’; WHEN lr3 =>

lc<=’1’;lb<=’1’;la<=’1’;ra<=’1’;rb<=’1’;rc<=’1’; END CASE:

END PROCESS; END state_machine;



Once you have state machine description Simulate it in a test suite to verify the design meets

specifications. This is the HDL topic of verification (ECE 764 – even years and a terminal grad course)

Then can synthesize the design to generate an FPGA implementation or use standard cells and generate the standard cells which can be sent to a place and route program for automatic generation of the circuit for a custom IC.



If this is done What would you expect

How many F/Fs??? In this case you would expect 3 FFs.

Why? There are 8 states You could even ballpark the number of gates,

but that is a bit much.



The synthesis result Note the

number of F/Fs

The VHDL Style 3 Processes

One process for the F/Fs One process for the Next State Generation

Breaks down nicely using a case state structure Documents the state transitions nicely and easy to

maintain

One process for the Output Generation from the state or from the state and current inputs



The F/F process The form presented in the example is a simple

latch PROCESS BEGIN

WAIT UNITL clk=‘1’ AND clk’event; state <= next_state;

END PROCESS;



A more complete F/F specification PROCESS (clk,preset,clear) BEGIN -- active low preset and clear

IF (preset = ‘0) THEN state <= pr_state; --preset state ELSIF (clear = ‘0’) THEN state <= clr_state; --clear state ELSIF (clk = ‘1’ AND clk’event) THEN --rising edge state <= next_state; END IF;

END PROCESS;1/8/2007 - L20 Project Step 8 - Data Path


1/8/2007 - l20 project step 8 - data path copyright 2006 - joanne degroat, ece, osu1 state machine...

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