12 comparison of nn and fs.ppt - auburn universitywilambm/nn/cn_org/12 comparison of nn and...
TRANSCRIPT
NEURAL NETWORKS (ELEC 5240 and ELEC 6240)
Comparison of NN and FSComparison of NN and FS
Bodgan M. Wilamowskig
1
1 1
-0.5
0
0.5
-0.5
0
0.5
05
1015
20
05
10
1520-1
05
1015
20
05
10
1520-1
required surface triangular
1 1
required surface triangular
0 5
0
0.5
1
0 5
0
0.5
1
510
1520
5
10
1520-1
-0.5
510
1520
5
10
1520-1
-0.5
2
05
05
05
05
Mamdani fuzzy with MIN trapezoidal Gaussian
1 1
-0.5
0
0.5
-0.5
0
0.5
05
1015
20
05
10
1520-1
05
1015
20
05
10
1520-1
required surface triangular
1 1
required surface triangular
-0.5
0
0.5
-0.5
0
0.5
510
1520
5
10
1520-1
510
1520
5
10
1520-1
3
00 00
Mamdani fuzzy with producttrapezoidal Gaussian
11
-0.5
0
0.5
-0.5
0
0.5
05
1015
20
05
10
1520-1
05
1015
20
05
10
1520-1
required surface triangular
1 1
required surface triangular
0 5
0
0.5
1
0 5
0
0.5
1
510
1520
5
10
1520-1
-0.5
510
1520
5
10
1520-1
-0.5
4
05
05
05
05
TSK fuzzy with MINtrapezoidal Gaussian
11
-0.5
0
0.5
-0.5
0
0.5
05
1015
20
05
10
1520-1
05
1015
20
05
10
1520-1
required surface triangularrequired surface triangular
0
0.5
1
0
0.5
1
1520
10
1520-1
-0.5
1520
10
1520-1
-0.5
50
510
05
10
05
10
05
10
TSK fuzzy with producttrapezoidal Gaussian
1
0.5
1
-0.5
0
0.5
-1
-0.5
0
0.5
05
1015
20
05
10
1520-1
required surface 05
1015
20
05
10
1520
-1.5
required surface
0
0.5
1
0
0.5
1
1520
10
1520-1
-0.5
1520
10
1520-1
-0.5
6Neural network with one hidden layer
05
10
05
05
10
05
1
0.5
1
-0.5
0
0.5
-1
-0.5
0
0.5
05
1015
20
05
10
1520-1
required surface0
510
1520
05
10
1520
-1.5
required surface
0
0.5
1
0
0.5
1
1015
20
10
1520-1
-0.5
1015
20
10
1520-1
-0.5
7Neural network with cascade
05
10
05
05
10
05
two inputs cases
Fuzzy with 6 membership Neural networks
Mamdani fuzzy controllers require: 2*6 6 18 l l
Fuzzy with 6 membership functions
Neural networks
2 hidden neurons2*3+5= 11 analog values2*6+6 =18 analog values
+ rule table 36*3= 108 bits2 3+5= 11 analog values
3 hidden neurons3*3+5= 14 analog valuesTSK fuzzy controllers require:
2*6+6*6 =48 analog valuesNo rule table has to be stored
3*3+5= 14 analog values
4 hidden neurons*4*3+6= 18 analog values
-0 5
0
0.5
1
-0 5
0
0.5
1
-0 5
0
0.5
1
80
510
1520
05
10
1520-1
-0.5
05
1015
20
05
10
1520-1
-0.5
05
1015
20
05
10
1520-1
-0.5
Comparison of various fuzzy and neural controllers
Type of controller length of processin ErrorType of controller length of code
processing time (ms)
Error MSE
Mamdani with trapezoidal 2324 1.95 0.945
Mamdani with triangular 2324 1.95 0.671
Mamdani with Gaussian 3245 39.8 0.585
Tagagi-Sugeno with trapezoidal 1502 28.5 0.309
Tagagi-Sugeno with triangulal 1502 28.5 0.219
Tagagi-Sugeno with Gaussian 2845 52.3 0.306
Neural network with 3 neurons in cascade
680 1.72 0.00057
Neural network with 5 neurons in 1070 3 3 0 00009
9
Neural network with 5 neurons in cascade
1070 3.3 0.00009
Neural network with 6 neurons in one hidden layer
660 3.8 0.00030
Neuro fuzzy systems multiplication
zifie
r
X
sumfuzzification divisionall weights equalexpected values
-0.5
0
0.5
1
out
Fuzz
0
510
1520
05
10
1520-1
out
Fuzz
ifier
y
er all weights 0 5
0
0.5
1
Fuzz
ifiez all weightsequal 1
05
1015
20
05
10
1520-1
-0.5
10Fuzzy neural networks
Neuro fuzzy systems
yu v w x y z
ff
A
d
e
d
e
A
B
b
c
b
cC
x
a
0,0
a
u v w x y z
TSK f t ll fuzzy controller with sigmoidal
11
TSK fuzzy controller fuzzy controller with sigmoidal membership functions
Neuro fuzzy systems
yu v w x y z
ff
B
d
ee
B
b
c
d
b
c
d
A C
x
a
0,0
b
u v w x y z
C
12fuzzy controller with sigmoidal membership functions
a
1
Full control of information process
Neuro fuzzy systems
0
0.5
1
all thresholds are
thresholds are set
by values a to z
a
1015
20
5
10
1520-1
-0.5
x
all thresholds areequal to 3
A
Bc
b
a
05
05
s eq
ual 1
e
d
fout
0
0.5
1
all w
eigh
ts
weights areequal to theaverage ofw
u
v
1015
20
10
1520-1
-0.5y expected valuein the selected
region
Cw
x
y+1
13
05
10
05z -1
fuzzy controller with sigmoidal membership functions
Fuzzy systems VLSI implementation
fuzzy current variables
VIN
I1 I2 I3 I4 I5 I6
10[uA
]
Fuzzyfier with Six Diffrent Membership
e v
olta
ge
s
7
8
9I1 I2 I3
refe
ren
ce
3
4
5
6
Cur
rent
s
(a)
0 1 2 3 40
1
2
3
0 1 2 3 4VIN
F ifi ( ) i it di f f ifi (b) l f th SPICE i l ti
14
Fuzzifier (a) circuit diagram of fuzzifier, (b) example of the SPICE simulation
Fuzzy systems VLSI implementation
+VDD
I1 I2
10 6
10.8
11
MAX1
Comparison of MAX circuits
[uA]
IMAX
M4 M51 2
M6 M7 M8 10
10.2
10.4
10.6
I1
MAX2
rrent
s
M1 M3M2 3
VBIAS6 7 8
5M6 M7 M8
9.4
9.6
9.8
I2
Cur
IBIAS0 0.5 1 1.5 2 2.5 3 3.5 4
9
9.2
TIME [s]
MAX t ( ) t di d (b) i l ti lt f MAX1 d f th
15
MAX operators (a) concept diagram and (b) simulation results for MAX1 and for the proposed MAX2.
Fuzzy systems VLSI implementation
16Microphotograph of the analog fuzzy .
Fuzzy systems VLSI implementation zy
fier
X Array of out
fuzz
yfie
rs
64 M
INop
erat
ors
8+8(fuzzy)
64(fuzzy)
2 inputs(analog)
1 output(analog)
wei
ghte
dsu
m
rmal
izar
ion
64(fuzzy)
Fuzz
yfie
r
Array ofcluster cells
weightedcurrents
voltages
Block diagrams of the fuzzy VLSI chip
f o w
no
Fuzz
yY
Block diagrams of the fuzzy VLSI chip
10 200 8
10
2
4
6
8
50
100
150
100
2
4
6
0
5
10
0
5
100
0
5
10
05
10150
0
5
0
5
100
XY
17
Control surfaces: (a) desired control surface, (b) information stored in defuzzifier as weights, and (c) measured control surface of VLSI chip
Implementing a Fuzzy System on Field Programmable Gate Arraye d og b e G e y
AddressProvider
Look UpTable
StoreData
MostSignificant4 Bits ofthe 7 Bitthe 7 BitInputs
Fine ControlSurface
(W i ht d
ProcessingUnit
LeastSignificant
3 Bit f th (WeightedSum)
3 Bits of the7 Bit Inputs
18
The Xilinx 4000 series FPGA chip was chosen to implement this design on. The design was then synthesized using FPGA Express. This program does the fitting, place and route, timing, and generates the bitstream that is used to program the chip.
Implementing a Fuzzy System on Field Programmable Gate Array
vide
r
cant
ROM
e d og b e G e y
ess
Pro
v
nit
t Sig
nific
4 B
itsROMLook Up
TableA
ddre
sing
U
Mos
t Table
Pro
ces
nific
ant
ts ntro
ld
Sum
)
Fuzzy P
east
Sig
n3
Bit
Fine
Con
(Wei
ghte
d
ycontroller
19
Le
(
Implementing a Fuzzy System on Field Programmable Gate Arraye d og b e G e y
Desired Surface Actual Output from FPGA
The design fit on the 4010 FPGA using 97% of the chips resources The maximum delay between
20
The design fit on the 4010 FPGA using 97% of the chips resources. The maximum delay between flip-flops determines the clock frequency. The maximum clock frequency for this design is 9.6MHz.