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Sequential LogicThe Forbidden Zone

Ellen SpertusMCS 111

September 10 and 12, 2002

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What does a computer do?

Calculates mathematical functions Allows different operations to be

specified• • •

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Combinational logic

• Everything we’ve done so far• Outputs depend only on the inputs• No cycles (loops)

A

B

C

Y

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Sequential logic

• What we’ll look at this week• Outputs depend on

– inputs– previous values (“state”)

• Cycles (loops) in circuits • Purpose?

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Useful memory unit

• Remember old value• Set to high• Reset to low

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RS-latch symbol and truth table

R S Q(n+1) ~Q(n+1) 0 0 Q(n) ~Q(n) 0 1 1 0 1 0 0 1 1 1 0 0

RS

Q~Q

Q = R + ~Q

~Q = S + Q

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RS-latch implementation

R

S

Q

~Q

Q = R + ~Q

~Q = S + Q

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RS-latch timing diagram

R

S

~Q1

0

1

0Q

1

0

1

0

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RS-latch dangerous transition

R

S

Q

~Q

1 0

1 0 0

0

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Low-level summary

• Meaning of RS?– R– S

• Behavior– R=0, S=0 – R=0, S=1 – R=1, S=0 – R=1, S=1

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High-level summary: RS latch

• Capabilities:

• Limitations:

• What improvements would we like?

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Preventing forbidden transition

How can we prevent R and S from simultaneously changing from 1 to 0?

R

S

Q

~Q

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D-latch

R

S

Q

~QDE

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D-latch behavior

D E R S behavior 0 0 0 1 1 0 1 1

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4-bit D-latchenable

data Q

~QD

enable

data Q

~QD

enable

data Q

~QD

enable

data Q

~QD

enable

data Q

~QD

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Counter: first attempt

enable

data QD

latch

ALU

1

44

4

4

clock

Behind the Curtain 18

Behind the curtain

Behind the Curtain 19

Representation of 0s and 1s

• Logical zero (false): 0 – .8 Volts• Logical one (high): 2 – 5 Volts

• What is:• .4 Volts• 3.5 Volts• 1.2 Volts

Behind the Curtain 20

The Forbidden Zone A range of voltages that represent

neither zero nor one; specifically:

Behind the Curtain 21

Inverter (not gate) behavior• If input voltage is low, output is: • If input voltage is high, output is:• In input voltage is in between, output is:

0 5

0

5

Behind the Curtain 22

How to deal with forbidden zone?

• Never allow any point in the circuit to have a voltage in the forbidden zone.

Behind the Curtain 23

A closer look at a “square” wave

time

volta

ge

Behind the Curtain 24

We can’t avoid the forbidden zone

You can’t get from here to there without going in between.

Behind the Curtain 25

How to deal with forbidden zone?

• Never allow any point in the circuit to have a voltage in the forbidden zone.

• Never allow a value in the forbidden zone to be an input to a gate.

Behind the Curtain 26

Propagation delays

• Every gate has a propagation delay, the time it takes to make the complete transition.

• During this period, the result may be in the forbidden zone.

• After the propagation delay, the result will not be in the forbidden zone.

Behind the Curtain 27

Combined propagation delays If each gate has a propagation delay of

5 ns, what is the total propagation delay?

Meaning:

A

B

C

Behind the Curtain 28

How to deal with forbidden zone?

• Never allow any point in the circuit to have a voltage in the forbidden zone.

• Never allow a value in the forbidden zone to be an input to a gate.

Don’t look at an output until after the propagation delay.

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Counter: first attempt

enable

data QD

latch

ALU

1

44

4

4

clock

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The problem

If we have cycles in our circuit, values in the forbidden region will propagate through the circuit, contaminating all data.

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How to deal with forbidden zone?

Don’t look at an output until after the propagation delay- If no loops, just wait out propagation delay- If loops, insert a barrier to prevent

forbidden values from contaminating the rest of the circuit

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D flip-flop

QD

~Q

data Q data Qdata

enable enable

clock

Q

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D flip-flop behavior

• Only accept new data when

• Otherwise, keep the same data

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Counter: correct

data QD

flipflop

ALU

1

44

4

4

clock

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Counter: correct (close-up)Q0

Dflipflop

ALU

1

4

clock

Q1Q2

Q3

D3 D2 D1 D0

D3

D1D0

D2

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Timing diagram

Clock

Q0

D01

0

1

0

1

0

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LS377: octal D-type flip-flop

• OE = output enable (active low)• Inputs D7-D0• Outputs Q7-Q0• Clock input

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Wiring diagrams

• Shows logical shape• Has chip number• Includes pin numbers

in logical order (outside chip)

• Includes signal names (inside chip)

• Bubble indicates active-low input

• “nc” stands for:

d0d1d2d3

d7..d4

3478

nc

q0q1q2q3

d7..d4

2569

nc

enable

1

LS377

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Looking ahead

• Assignments– Lab 1 due tomorrow (September 13)– Homework 3 due Tuesday (September 19)– Lab 2 due next Friday (September 20)

• Topics– You now know the basics– Start studying assembly language from

Hennessy and Patterson