0930 - balog - spadic simulations

8/3/2019 0930 - Balog - SPADIC Simulations

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Simulationstudy of SPADICFEE in overloadsituations

Tomáš Balog

18th CBM Collaboration meeting, Beijing,China, 26-30th September 2011



Outlook

Brief overview of n-XYTER simulation andit’s results

SPADIC chip

Data flow and overload simulation

Results

18th CBM Collaboration meeting, Beijing,China, 26-30th September 2011, Tomáš Balog

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What have we done to n-XYTER?

Goal was to find mechanism to controldata losses in self-triggered FEE.

Simulated electronics based on n-XYTERchip.


asynchronous synchronous! ?

And why?

• The data rate can temporarily exceed theavailablebandwidth.

• Overload can lead to asynchronous data losses.

• Potentially a large fraction of the events isincomplete.

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What have we done to n-XYTER?(2)


Simulation overview

System sizes 1, 10, 100, 1000 chips

No. of channels ineach chip

128

FIFO depths 4, 8, 16 & 32 cells

Channel dead-time 30 ns

Pile-up time perchannel

300 ns

Token Ringfrequency

32 MHz

Investigated datarates

64 MHz, 52 MHz, 40 MHz, 32 MHz,16 MHz, 8 MHz

• System avoids central decisionpoint – channels are independent.

• Time is the only one synchronizationpoint – definition of epoch time.

• Epoch time is defined as timeneeded for Token Ring to readall data if all FIFO's in chip are full.

• Dead-time of self-triggering systemis defined by software.

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HitCounter

Discarding data which come after FIFO is closed

Closing aFIFO

What have we done to n-XYTER?(results)

Synchronous!

10% of all FIFOsare closed

Data rate:64MHz

Token Ringfrequency:

32MHz

FIFO depth:4

Shorter dead-time!

better performance

• Add counter of hits into the channel.If counter reaches number whichcorresponds to depth of FIFO,particular FIFO is closed – doesn't

have to be filled.

fixed frame size withsoftware dead-timeis working approach

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Towards SPADIC simulation

• results from n-XYTER simulation as a reference point

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Simulated SPADIC chip

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Simulated SPADIC chip (2)

- every channel has its own data hit generator (16 channels)- if more hits occur within one clock-cycle all of them are visible in

the end of the clock-cycle – to prevent overload of order FIFOthat could occur just because of the different timing of signals

- if both channel FIFO and order FIFO have free cell for writing data

then hit is stored into FIFO- channel FIFOs have 7 cells - message has 9 words and the depth

of channel FIFO in real SPADIC is 64 - 7 messages to be stored inone FIFO (number of cells tells how many messages can bestored in channel FIFO)

- one clock-cycle has 40ns (accordingly to 25MHz in reading part)

– writing and reading part uses the same clock to generateclock-cycle

- reading from channel FIFOs is according to information in order FIFO

- reading from channels by "Token Chain“ - if channel is full then particular data information is lost

- if order FIFO is full then all data within this clock-cycle are lost8




Simulated SPADIC chip (3)

Two types of simulation have been done: - holding – to simulate full message reading – each message is 9

words, so if channel FIFO has hit stored and it is being read thenthe reading takes 9 clock-cycles, meanwhile writing messages isnot blocked

(reading is 25*2Mbits) - non-holding – full hit information is read within one clock-cycle,

whole message is read at once (output frequency is 25*9Mword)

For comparison even n-XYTER chip has been simulated in the same

conditions:

- 16 channels which use the same hit generators as the SPADIC chip – same hit environment as SPADIC- structure is similar to SPADIC - channel FIFOs have depth of 7 cells

- reading made by Token Ring- only one clock to synchronize whole

chip with clock-cycles

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Simulated SPADIC chip – results

Chip performance:

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Simulated SPADIC chip – results (2)

Size of Order FIFO:

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Data losses within SPADIC chip (different chip sizes):- higher amount of channels result to lower data rate per channel since output bandwidth is keptto be the same

SPADIC chip losses

0

10

20

30

40

50

60

70

80

2 3 4 5 6 7 8 9 10 11

Data rate [MHz]

D a t a l o s s e s [ % ]

9/ 138

9/ 128

7/64

7/90

7/100

4/52

7/90

8/ 103

9/ 116

12/ 154

4/ 103

7/180

8/205

9/231

12/3 08

4/205

7/359

8/ 410

9/461

12/ 615

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data losses in 80% sized Order FIFO at different data rates and different sizes of the system[In legends: number of cells in channel FIFO / number of cells in Order FIFO]



Data losses within Order FIFO of SPADIC chip:

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Data losses within SPADIC chip:

data losses in

Order FIFO ofchips withdifferent size ofchannel FIFO atdifferent datarates

[In legend:number ofchannels (size ofOrder FIFO)]

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18th CBM Collaboration meeting, Beijing,China, 26-30th September 2011, Tomáš BalogSimulated SPADIC chip – results

overviewor better – Conclusions

SPADIC type of reading gives similar amount oflosses than Token Ring in n-XYTER if put in similar conditions

SPADIC chip losses are distributed into channel

losses and order FIFO losses Order FIFO should have 80% of all cells within all

channels

Channel FIFO should have depth accordingly tothe size of the message

Data losses handling and software dead-timestudies from simulation point of view - to be done!

Simulation of performance of both chips in “real”station (with noise?)

Thank you! 15




Backup

slides




Backup slide 1

Time window30 ns

Pile-up timewindow 300 ns

FIFO depths4, 8, 16 & 32

TokenRing withfrequency

32MHz

Writing datawith Uniformdistribution

128 channelsper chip

Data rates64 MHz,32 MHz,16 MHz,8 MHz

n-XYTER simulation graphical preview:



10% of all FIFOsare closed

Data rate:64MHz

Token Ringfrequency:

32MHz

FIFO depth:

4

Stillasynchronous !


Backup slide 2

Software dead-time for n-XYTER chip without fixed frame rate(only closing channels):




Backup slide 3

SPADIC simulation explanations:

- Data rate is basically the "word rate" so per chip it can be 25 Mwords(MHz) but reading takes 9 words per message, so reading isca. 2.8 Mmessages (here named as output reading frequency alsoshown in MHz).

- Tried to simulate signals - input rate of hits/signals is (at equilibrium) 2.8 MHz- Everything in simulation is synchronized for 25MHz rate which means

that hits can differ in 40 ns within channel- Reading signals are controlled every 40 ns if there is nothing read- If there is reading than every signal is read for 9*40 ns and next reading

is checked after another 40 nsexample:signal at 0ns in channel 5 – into channel and into order FIFOsignal at 80ns in channel 7 – into channel and into order FIFOreading at 40ns – on channel 5 – waiting (reading) for 360nschecking for another signal in order FIFO and at time 400ns – finds that there is signal in channel 7so it starts to read and finishing reading at time 760ns from beginningMeanwhile every 40ns one signal can come into channel BUT for equilibrium situation (output and inputare same) average data rate per channel is 173 kHz.




Backup slide 4

- Simulation itself is about overloading the chip so when higher data ratesare introduced that hit can occur (theoretically) every 40ns in channel.

- So one can argue that there can be stored only one hit every 360nssince this is time needed to write all words into

- BUT - if 7 hits are stored in a row and FIFO is than filled for at least 360ns

(1 message reading cycle) and one looses 9 hitsthis is the same situation as if one stores one hit per 9 cycles so 9 hitsare lost either way (in this moment FIFO would be real size of 54 cells)

- Holding and non-holding situations (as said before) – holding means

thatone can write into FIFO but reading takes 9 cycles, non holding justmeans,that hit is read at once so output word rate is really 9*25 Mwords(this was just to show that holding-and non holding situations are inprinciple

the same, the only difference is the bandwidth)

0930 - balog - spadic simulations

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