© copyright 2010 – cmosis nv sun sensor on a chip – esa mpd 2010 werner ogiers – cmosis –...

© copyright 2010 – CMOSIS nv

Sun Sensor on a Chip – ESA MPD 2010Werner Ogiers – CMOSIS – Antwerp (B)

© copyright 2010 – CMOSIS nv 2

Project Background

• Sensor on a Chip study (ESA 20252/06/NL/JA)

– Selex Galileo prime– feasibility of single-chip Star Tracker and Sun Sensor

• ESA Avionics Workshop 2007– confirms market for micro-miniature, robust, versatile,

high-accuracy digital sun sensor

• ESA call– “Digital Sun Sensor on a Chip Prototype Design and

Manufacture”– ► ESA 21835/08/NL/ST (S.P.Airey, TEC-ECC)– potential follow-up for EQM/FM


Contract SoW

• To design a highly miniaturised, plug and play, medium to high accuracy digital sun sensor suitable for use on all classes of mission from nano s/c (<10Kg) to GEO telecoms (18year lifetime) and planetary rovers (e.g. high dust environment).

• To demonstrate, via the production and testing of prototype hardware, the feasibility, characteristics and performances of a medium to high accuracy highly miniaturised digital sun sensor.

dimensions 40 x 40 x 30 mmmass 60 glifetime 18 years GEOSEU, LU immunesupply 5 V nominalpower 300 mW peaksun position update rate 2 - 10 Hzaccuracy 0.05 degrees, over FOVinterface SpaceWire, UARTuser interaction none


Project team

• Selex Galileo (I)– prime– instrument design

• BAE Systems (UK)– optics

• THAS (F)– client side (S/C)

• CMOSIS– sensor chip design


And now for something completely different ...

• We don’t want to make a single-chip SUN SENSOR

• Long-term, we want a single-chip high-performance autonomous STAR TRACKER

• The work starts here. After all, the sun is a star too ...


A Micro-Miniature STR?

APS Image Sensor + ADC

Readout control

Image processing

μProcessor (LEON)

1Mb RAM

4Mb NVM (software, star

catalogue)

SpaceWire / LVDS

3.3V regulator

1.8V regulator

3.3V regulator

clock oscillator POR

quaternions


A Micro-Miniature Sun Sensor?

APS Image Sensor + ADC

Readout control

Image processing

Tracker State Machine

SpaceWire / LVDS

3.3V regulator

1.8V regulator

3.3V regulator

clock oscillator POR

(X,Y) or (α,β)


Overview

• Quick overview of the chip

• Three particular challenges– CMOS process selection & IP– Optical performance– Power consumption

• Layout, present status


SSoC chip diagram

512 x 512 Pixel Array (10 μm)

512 Column Amps

512 Column ADCs (10b)

X Multiplexer

Y D

ecod

ers

Bias

Gen

erat

ors

Temp. Sensor

Readout Sequencer Pixel and Object Processing

SpaceWire / UART TC/TM Interface

Sun Tracker State Machine

Digital IO (LVDS)Supply IO

3.3V Reg

3.3V Reg

Anal

ogue

IO (t

est o

nly)

1.8V Reg

OSC

POR

• Digital camera– looks at sky– identifies sun– tracks sun– centroid to high

accuracy– (X,Y) to AOCS

• System links– 5V supply– TC/TM interface


SSoC operating modes

1. Acquisition Mode1. Full-frame images (512x512 pixels) @ 5 Hz

2. Search for the sun

X

Y

FPA

X

Y

FPA


SSoC operating modes (2)

1. Tracking Mode1. Windowed images (80 x 80) @ 10 – 60 Hz

1. Track while spinning: 90°/s up to 600°/s

2. Centroid: 1/100 pixel pitch accuracy ► 0.05° in 128° FOV

X

Y

FPA

X

Y

FPA


Sun detection (the fun bit)

1. Reject singular bright/dark pixels1. = sensor defects

2. = SEU streaks

2. 2D clustering of bright pixels1. grow potential sun cluster

2. reject too small, too large

3. 1..4 potential suns concurrently1. pick the one closest to last-known sun position

2. export sun position as 16-bit coordinates (X,Y)


Sun detection


2. = SEU streaks






Challenge 1: CMOS process selection

• Circuit density, power– ►180 n

• Radiation hardness – FASTRAD simulation at system level

• chip parts > 300 krad• commercial logic libs risky

– IMEC DARE libs ► UMC 180n Logic


Challenge 1: CMOS process selection (2)

• Electro-optical performance– Pinned photodiode: lowest dark current & noise

• dark current is next barrier in STR performance• each pixel ~ single-cell CCD• ►dedicated CMOS Image Sensor process (CIS)

– Old saying ‘APS = commodity CMOS’ is broken!

• UMC 180n CIS ≠ 180 nm Logic– thinner stack (parasitics!), only 4 metals, ...– DARE libs not compatible

• Noordwijk, we have a problem ...


Who DAREs wins

• A Miracle ...– ESA agreed CCN to DARE90 (20896/07/NL/JD)

• Redesign selected IO cells for UMC 180 CIS• Recharacterise all core cells• Additional cells & functions (mask-programmable flipflop, LVDS power-down)

– IMEC initiated work • well before contracts signed

– IMEC finished work• almost before libs were needed (a big THANK YOU!)

• Problem remains for space Image Sensor SoC:– most interesting IP is NOT compatible with best process


Challenge 2: optical performance

• Pinned Photo Diode pixel– part science, part art

• Standard development flow– test chip

– 100s of pixel variants, pick the best one

• Now– first time use of UMC process

– no time, budget for test chip

• partial test chip in ‘similar’ TSMC process

• Risky business!


Challenge 3: Power

• Supply = 5V from S/C secondary bus– peaks up to 7V <> 180nm process tolerates 3.5V– cascoded linear regulators, tolerant to ... 5.5V

• STR will need DC/DC for 1.8V logic

• Power optimisation– 99% of service life in tracking mode

• 20 ms capture, 80 ms idle– Analogue: unclocked when idle– Logic: data-driven automatic clock gating

• dark pixel ► clocks OFF

Clocks ON


Power (2)

• Acquisition Mode (5Hz, full image)– 240 mW @ 5V

• Tracking Mode (10Hz, 80x80 window)– 170mW @ 5V

• BUT ...– 93 mW in SpaceWire LVDS drivers– 50% of chip ( = system!) power in Tracking Mode!!!

• Wouldn’t it be nice if someone sat down and designed low-power LVDS for UMC 180nm?


Layout

• Large die– 11 x 11 mm– pixel array ~central

• wastes Si– few power/ground pads– large metal rings

• low-R for ESD– floorplan = interface to

optics

512 x 512 pixels

512 ADCs

Logi

c


Layout (2)

• Immersed optics– glass die with pinhole bonded onto

silicon die– brings radiation shielding– MEMS stack must not impede

wire bond tool• few, spaced IO pad cells

– prototyped on LCMS sensor


Timeline

• February 2009: initiated project– Requirements analysis

– Architectural design

– Algorithm (re)development for robustness

• May 2009: detailed design– initially 1 jr analogue designer, 1 sr logic

– team grew, company too (+100%)

• November 2009: transfer to IMEC for back-end– synthesis, clock gating, ATPG, layout

• March 2010: tapeout


Timeline (2)

• 13 months– Longer than planned, but still faster than LCMS (FillFactory)

• Tempting Murphy– First-time use of UMC process / foundry

• Critical for pixel development!

• January 2010: UMC offered foundry process experiments / optimisation

– ► setup delayed tape out– ► partially offsets lack of pixel test chip

– First-time use of ported core and IO cell libs + debug

• Annoying tool problems

• Devised new ESD strategy


Conclusions

• System on Chip Sun Sensor– evaluate through 2010 (inc. radiation)– EQM / FM in 2011?

• Step towards SoC Star Trackers– DARE CMOS Image Sensor logic libs– Pinned diode pixels with very high performance– IP: regulators, POR, OSC, ...– Low power techniques– CIS process supply voltage tolerance

© copyright 2010 – cmosis nv sun sensor on a chip – esa mpd 2010 werner ogiers – cmosis –...

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